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WO2001059571A3 - Command-driven test modes - Google Patents

Command-driven test modes Download PDF

Info

Publication number
WO2001059571A3
WO2001059571A3 PCT/US2001/040030 US0140030W WO0159571A3 WO 2001059571 A3 WO2001059571 A3 WO 2001059571A3 US 0140030 W US0140030 W US 0140030W WO 0159571 A3 WO0159571 A3 WO 0159571A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
mode
memory device
selectively
special
Prior art date
Application number
PCT/US2001/040030
Other languages
French (fr)
Other versions
WO2001059571A2 (en
Inventor
Jin-Lien Lin
Takao Akaogi
Ali K Al-Shamma
Lee Edward Cleveland
Yong Kim
Boon Tang Teh
Kendra Nguyen
Original Assignee
Advanced Micro Devices Inc
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Fujitsu Ltd filed Critical Advanced Micro Devices Inc
Publication of WO2001059571A2 publication Critical patent/WO2001059571A2/en
Publication of WO2001059571A3 publication Critical patent/WO2001059571A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)

Abstract

A system and a method for selectively placing a computer memory device (100), even when its data/address pins (104) are multiplexed, into a special test mode. In order to allow the manufacturer of a memory device to selectively enter into one of a plurality of special high-speed tests, while preventing an ordinary user of the memory device from accidentally entering into such test modes, a combination of one or more high voltage pins and a sequence of test-mode commands (303, 304) are used to selectively enter into a special test mode. The high voltage pin serves as an enable signal input to a test-mode command decoder (202) to enable it for receiving and recognizing a specific sequence of test-mode commands (303, 304). The specific sequence of test-mode commands (303, 304) is supplied to selectively put the memory device in one of a plurality of test modes.
PCT/US2001/040030 2000-02-11 2001-02-05 Command-driven test modes WO2001059571A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US18166700P 2000-02-11 2000-02-11
US60/181,667 2000-02-11
US69380900A 2000-10-20 2000-10-20
US09/693,809 2000-10-20

Publications (2)

Publication Number Publication Date
WO2001059571A2 WO2001059571A2 (en) 2001-08-16
WO2001059571A3 true WO2001059571A3 (en) 2002-06-20

Family

ID=26877401

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/040030 WO2001059571A2 (en) 2000-02-11 2001-02-05 Command-driven test modes

Country Status (1)

Country Link
WO (1) WO2001059571A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3938376B2 (en) 2004-03-29 2007-06-27 シャープ株式会社 Test terminal invalidation circuit
JP2011248952A (en) * 2010-05-25 2011-12-08 Fujitsu Ltd Flash memory with test mode and connection test method for the same
US20150019775A1 (en) * 2013-03-14 2015-01-15 Microchip Technology Incorporated Single Wire Programming and Debugging Interface
US20150155039A1 (en) * 2013-12-02 2015-06-04 Silicon Storage Technology, Inc. Three-Dimensional Flash NOR Memory System With Configurable Pins

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3903714A1 (en) * 1988-03-14 1989-09-28 Mitsubishi Electric Corp SEMICONDUCTOR MEMORY DEVICE WITH A TEST MODE SETTING CIRCUIT
US5153509A (en) * 1988-05-17 1992-10-06 Zilog, Inc. System for testing internal nodes in receive and transmit FIFO's
US5919269A (en) * 1995-10-11 1999-07-06 Micron Technology, Inc. Supervoltage detection circuit having a multi-level reference voltage
US5942000A (en) * 1996-08-14 1999-08-24 Micron Technology, Inc. Circuit and method for testing an integrated circuit
US5953273A (en) * 1997-05-29 1999-09-14 Nec Corporation Semiconductor integrated circuit device having confirmable self-diagnostic function
US6005814A (en) * 1998-04-03 1999-12-21 Cypress Semiconductor Corporation Test mode entrance through clocked addresses

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3903714A1 (en) * 1988-03-14 1989-09-28 Mitsubishi Electric Corp SEMICONDUCTOR MEMORY DEVICE WITH A TEST MODE SETTING CIRCUIT
US5153509A (en) * 1988-05-17 1992-10-06 Zilog, Inc. System for testing internal nodes in receive and transmit FIFO's
US5919269A (en) * 1995-10-11 1999-07-06 Micron Technology, Inc. Supervoltage detection circuit having a multi-level reference voltage
US5942000A (en) * 1996-08-14 1999-08-24 Micron Technology, Inc. Circuit and method for testing an integrated circuit
US5953273A (en) * 1997-05-29 1999-09-14 Nec Corporation Semiconductor integrated circuit device having confirmable self-diagnostic function
US6005814A (en) * 1998-04-03 1999-12-21 Cypress Semiconductor Corporation Test mode entrance through clocked addresses

Also Published As

Publication number Publication date
WO2001059571A2 (en) 2001-08-16

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