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WO2001050594A1 - Commande de tension de polarisation - Google Patents

Commande de tension de polarisation Download PDF

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Publication number
WO2001050594A1
WO2001050594A1 PCT/FI2000/001133 FI0001133W WO0150594A1 WO 2001050594 A1 WO2001050594 A1 WO 2001050594A1 FI 0001133 W FI0001133 W FI 0001133W WO 0150594 A1 WO0150594 A1 WO 0150594A1
Authority
WO
WIPO (PCT)
Prior art keywords
error signal
vgs
ldmos device
err
arrangement
Prior art date
Application number
PCT/FI2000/001133
Other languages
English (en)
Inventor
Jonas Lundell
Original Assignee
Nokia Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Corporation filed Critical Nokia Corporation
Priority to US10/169,196 priority Critical patent/US7078967B2/en
Priority to AU23802/01A priority patent/AU2380201A/en
Publication of WO2001050594A1 publication Critical patent/WO2001050594A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3223—Modifications of amplifiers to reduce non-linear distortion using feed-forward
    • H03F1/3229—Modifications of amplifiers to reduce non-linear distortion using feed-forward using a loop for error extraction and another loop for error subtraction

Definitions

  • the invention relates to a method and an arrangement for maintaining an optimal operating point of LDMOS semiconductor devices stable.
  • the invention is especially useful in a feedforward amplifier arrangement.
  • Figure 1 illustrates the formation of intermodulation products (IM-products) causing distortion to an output signal.
  • An undistorted input signal 12 consisting of two frequency components ⁇ 1 and ⁇ 2 is fed into an amplifier 14.
  • a distorted signal 16 which includes desired signal components at frequencies ⁇ 1 and ⁇ 2 and also two strong undesired signal components close to the desired signal components at the frequencies 2 * ⁇ 1- ⁇ 2 and 2 * ⁇ 2- ⁇ 1.
  • These undesired signals may appear in the desired signal band, and thereby corrupt the output signal.
  • LDMOS Laterally Diffused Metal Oxide Semiconductor
  • IM-products are relatively new semiconductor devices, which have improved characteristics compared to conventional semiconductor devices. For example, they have im- proved IM performance, i.e. they produce less IM-products at the same input power than the conventional semiconductor devices.
  • Typical input power/IM- products curves of a conventional semiconductor device and of an LDMOS device are illustrated in Figure 2 by a dashed line and a solid line, respectively.
  • the amount of IM-products increases as the input power increases.
  • the advantage of an LDMOS device is that it has an optimal operating point called "sweet point" producing an optimal input power/IM-products ratio.
  • LDMOS devices make them especially well suited for power amplification. However, they are not widely used at the mo- ment. A reason for this is a considerable drift in gate-source bias voltage, or Vgs.
  • the Vgs is a DC voltage which is used to provide a certain drain-source quiescent current, or Idq.
  • Idq drain-source quiescent current
  • the location of the "sweet point" on the input power axis in Figure 2 is dependent on this quiescent current. Therefore, the Vgs can be used to set the "sweet point", i.e. optimal operating point, to the preferred input power level.
  • the Vgs is kept constant, the Idq decreases in the course of time because of aging of the LDMOS transistors.
  • the Vgs corresponding to a certain Idq changes in the course of time.
  • This kind of drift in bias voltage due to transistor aging also appears in "normal" semiconductor devices, but it is a considerable problem with LDMOS transistors, in particular. Therefore, a method of keeping the Idq constant is needed for LDMOS devices in order to maintain their "sweet point" at the desired signal level. This object can be achieved by reducing the Vgs drift or by adjusting the Vgs for keeping the Idq constant.
  • Vgs drift Since the Vgs drift has been reduced from more than 25% to 5% for 900 MHz parts and to 12-15% for 2GHz parts by device manufacturers, the problem of the drift has diminished. However, the problem has not disappeared, because a 10% drift may produce 5-10 dB IM-products, which is still relatively much in a linear amplifier.
  • One proposed method of adjusting the Vgs to keep the Idq con- stant is to measure the Idq and make Vgs adjustments on the basis of the measured Idq.
  • the problem in this kind of an arrangement is that the amplifier has to be shut down during the measurement. Additionally, the transistor characteristics that vary from one transistor to another have an effect on the measurement results.
  • An object of the present invention is to overcome or alleviate the above described problems by providing a method and an arrangement for keeping the Idq constant in an LDMOS device.
  • the object is achieved by a method and an arrangement which are characterized by what is disclosed in the attached independent claims.
  • Preferred embodiments of the invention are disclosed in the attached dependent claims.
  • the bias voltage Vgs of an LDMOS device is adjusted to keep the Idq of the device constant and consequently to maintain an optimal operating point, i.e. the "sweet point", of the device stable.
  • the invention employs a method known from a feedforward amplifier arrangement.
  • a feedforward amplifier arrangement is one possible solution to achieve high power amplification, high efficiency and low distortion.
  • a feedforward amplifier arrangement distortion in the output signal of the arrangement is reduced by separating an error signal component from the output signal of the amplifier and then subtracting this error signal component from the output signal of the amplifier containing the error signal component.
  • the error signal components cancel each other out and the resulting output signal contains considerably less distortion than the original output signal of the amplifier.
  • this kind of separate error signal com- ponent is used for controlling the Vgs of an LDMOS device to maintain the optimal operating point of the LDMOS device stable.
  • the absolute value of the error signal component at the output of the LDMOS device is defined and the Vgs is adjusted in response to this error signal component so that the error signal component at the output of the LDMOS device reaches its minimum.
  • This invention provides a simple way to control the operating point of LDMOS devices.
  • the invention suits especially well for a feedforward amplifier arrangement, since it employs an error signal that is already generated in a feedforward arrangement and therefore, only few extra components are needed.
  • An advantage of a preferred embodiment of the invention is also that the amplifier does not need to be completely shut down during the Vgs adjustment.
  • Figure 1 illustrates formation of IM-products
  • Figure 2 illustrates typical input power/IM-products curves of a conventional semiconductor device and of an LDMOS device
  • Figure 3A is a block diagram illustrating an arrangement according to the invention
  • Figure 3B is a block diagram illustrating an embodiment according to the invention.
  • Figure 4 is a block diagram illustrating another embodiment ac- cording to the invention
  • Figure 5 is a flow chart illustrating the operation of the Vgs control block according to the invention.
  • FIG. 3A illustrates a block diagram of an arrangement according to the invention including an LDMOS device 32, error signal separating means 30 and Vgs control means 39.
  • the LDMOS device 32 receives an input signal In and produces, on the basis of this input signal In, an output signal including distortion.
  • This output signal of the LDMOS device is connected to the error signal separating means 30 together with the input signal In.
  • the error signal separating means 30 produce an error signal component err which is connected to the Vgs control means 39.
  • FIG. 3B illustrates an embodiment of the invention including a basic feedforward arrangement 31 and Vgs control means 39.
  • the feedforward arrangement includes an LDMOS amplifier 32, attenuation means 35, time (delay) adjusting means 33 and 36, adders 34 and 37 and an error signal amplifier 38.
  • An input signal In is connected to an input of the LDMOS amplifier 32.
  • the input signal is adjusted in time (delayed) with time adjusting means 36 for producing signal A and the output signal of the LDMOS amplifier 32 is attenuated with attenuation means 35 for obtaining signal B.
  • signals A and B which are fed into the adder 37, have equal amplitudes and a 180° phase difference relative to each other, and the error signal component err is obtained as an output of the adder 37.
  • the error signal component err is amplified by the error signal amplifier 38 for obtaining signal C and the output signal of the LDMOS amplifier 32 is adjusted in time (delayed) with time adjusting means 33 for obtaining signal D.
  • signals C and D which are fed into the adder 34, have equal amplitudes and a 180° phase difference relative to each other, and the output signal Out, in which the error signal component is canceled, is obtained as an output of the adder 34.
  • the error signal component err is also connected to the Vgs control means 39.
  • the Vgs control means produce the Vgs for the LDMOS amplifier 32 on the basis of the error signal component err, as will be described later in connection with Figure 5.
  • FIG 4 illustrates another embodiment of the invention including a feedforward arrangement 40 and Vgs control means 39.
  • the feedforward arrangement 40 includes an LDMOS amplifier 32, adders 34 and 37, time (delay) adjusting means 33 and 36 and an error signal amplifier 38, all of which operate essentially in the same way as in the arrangement of Figure 3B.
  • Gain/phase adjustment means 41 are added for adjusting the phase ⁇ and gain A of the input signal In before amplification.
  • the arrangement 40 includes down converter means 44 for converting the error signal and the input signal to a lower frequency, and A/D converters 45 and 46 for converting respective downconverted signals to a digital form for digital signal processing.
  • signal processing means 47 In response to the output signals of the A/D converters 45 and 46, signal processing means 47 produce a control signal which is connected to adjustment means 41 via sample & hold means 48 and a D/A converter 49.
  • the error signal component err obtained as an output of the A/D converter 45 is also connected to the Vgs control means 39.
  • the Vgs control means produce the Vgs for the LDMOS amplifier 32 on the basis of the error signal component err.
  • the error signal component err is handled in digital domain by the Vgs control means, and the Vgs is produced in a digital form and then converted to an analog form by the Vgs control means.
  • FIG. 5 is a flow chart illustrating the operation of a possible implementation of the Vgs control means 39 in Figures 3 and 4. This implementation tries several Vgs values, each attempt having an attempt number N. In step 51 , the power level of the Nth error signal err(N) is measured. Then Vgs is increased in step 52 and the power level of the (N+1)th error signal err(N+1) is measured in step 53.
  • step 54 the power levels of Nth and (N+1)th error signal are compared and, if err(N) > err(N+1), N is incremented in step 55 and steps 52 to 54 are repeated. Otherwise, the Vgs is first decreased to the value corresponding the Nth error signal in step 56 and then decreased again in step 57. Next, the power level of the (N+1)th error signal err(N+1) is measured in step 58, and the power levels of Nth and (N+1)th error signal are compared in step 59. If err(N) > err(N+1), N is incremented in step 60, and steps 57 to 59 are repeated. Otherwise, the Vgs is increased to the value corresponding the Nth error signal in step 61 , and the operation is terminated in step 62.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un procédé destiné à maintenir stable un point de fonctionnement optimal d'un dispositif LDMOS (32), ce dispositif LDMOS (32) produisant un signal de sortie comprenant un composant de signal erreur (err). Le procédé consiste à séparer le composant de signal erreur (err) du signal de sortie du dispositif LDMOS (32) et à utiliser le composant de signal erreur (err) afin de commander la tension de polarisation porte-vers-source, ou Vgs, du dispositif LDMOS (32) dans le but de maintenir stable le point de fonctionnement optimal du dispositif LDMOS (32).
PCT/FI2000/001133 1999-12-30 2000-12-21 Commande de tension de polarisation WO2001050594A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/169,196 US7078967B2 (en) 1999-12-30 2000-12-21 Control of bias voltage
AU23802/01A AU2380201A (en) 1999-12-30 2000-12-21 Control of bias voltage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI992827A FI108686B (fi) 1999-12-30 1999-12-30 Bias-jännitteen säätö
FI19992827 1999-12-30

Publications (1)

Publication Number Publication Date
WO2001050594A1 true WO2001050594A1 (fr) 2001-07-12

Family

ID=8555841

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI2000/001133 WO2001050594A1 (fr) 1999-12-30 2000-12-21 Commande de tension de polarisation

Country Status (3)

Country Link
AU (1) AU2380201A (fr)
FI (1) FI108686B (fr)
WO (1) WO2001050594A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2839165A1 (fr) * 2002-04-30 2003-10-31 Koninkl Philips Electronics Nv Appareil radioelectrique comportant un amplificateur pour signaux a radiofrequence, amplificateur pour signaux a radiofrequence et procede pour amplifier de tels signaux
WO2003030354A3 (fr) * 2001-09-28 2004-02-19 Powerwave Technologies Inc Circuit de commande a rapport d'energies parasites pour amplificateurs lineaires a correction aval
EP1474865A2 (fr) * 2002-02-14 2004-11-10 Powerwave Technologies, Inc. Amplificateur de puissance radioelectrique a correction aval comprenant un amplificateur principal de rendement eleve et un amplificateur d'erreur a fonctionnement hautement lineaire

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9843292B2 (en) * 2015-10-14 2017-12-12 Knowles Electronics, Llc Method and apparatus for maintaining DC bias

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023491A1 (fr) * 1993-03-26 1994-10-13 Qualcomm Incorporated Circuit et procede de regulation de la synchronisation d'un amplificateur de puissance
US5973564A (en) * 1998-04-02 1999-10-26 Burr-Brown Corporation Operational amplifier push-pull output stage with low quiescent current
US6069530A (en) * 1998-09-16 2000-05-30 Motorola, Inc. Apparatus and method for linear power amplification
US6107880A (en) * 1998-08-06 2000-08-22 Motorola, Inc. Method and apparatus for increasing the linearity of the phase and gain of a power amplifier circuit
US6111464A (en) * 1999-07-23 2000-08-29 Nokia Networks Oy Amplifier having bias circuit self-compensating for VGS process variation and IDS aging

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994023491A1 (fr) * 1993-03-26 1994-10-13 Qualcomm Incorporated Circuit et procede de regulation de la synchronisation d'un amplificateur de puissance
US5973564A (en) * 1998-04-02 1999-10-26 Burr-Brown Corporation Operational amplifier push-pull output stage with low quiescent current
US6107880A (en) * 1998-08-06 2000-08-22 Motorola, Inc. Method and apparatus for increasing the linearity of the phase and gain of a power amplifier circuit
US6069530A (en) * 1998-09-16 2000-05-30 Motorola, Inc. Apparatus and method for linear power amplification
US6111464A (en) * 1999-07-23 2000-08-29 Nokia Networks Oy Amplifier having bias circuit self-compensating for VGS process variation and IDS aging

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003030354A3 (fr) * 2001-09-28 2004-02-19 Powerwave Technologies Inc Circuit de commande a rapport d'energies parasites pour amplificateurs lineaires a correction aval
US7231191B2 (en) 2001-09-28 2007-06-12 Powerwave Technologies, Inc. Spurious ratio control circuit for use with feed-forward linear amplifiers
US7693497B2 (en) 2001-09-28 2010-04-06 Powerwave Technologies, Inc. Spurious energy correlation for control of linear power amplifiers
EP1474865A2 (fr) * 2002-02-14 2004-11-10 Powerwave Technologies, Inc. Amplificateur de puissance radioelectrique a correction aval comprenant un amplificateur principal de rendement eleve et un amplificateur d'erreur a fonctionnement hautement lineaire
EP1474865A4 (fr) * 2002-02-14 2006-03-08 Powerwave Technologies Inc Amplificateur de puissance radioelectrique a correction aval comprenant un amplificateur principal de rendement eleve et un amplificateur d'erreur a fonctionnement hautement lineaire
FR2839165A1 (fr) * 2002-04-30 2003-10-31 Koninkl Philips Electronics Nv Appareil radioelectrique comportant un amplificateur pour signaux a radiofrequence, amplificateur pour signaux a radiofrequence et procede pour amplifier de tels signaux
WO2003094342A3 (fr) * 2002-04-30 2004-07-01 Koninkl Philips Electronics Nv Appareil radio comprenant un amplificateur pour signaux de radiofrequence, amplificateur pour signaux de radiofrequence et procede pour amplifier ces signaux
US7091782B2 (en) 2002-04-30 2006-08-15 Koninklijke Philips Electronics N.V. Radio apparatus comprising an amplifier for radio-frequency signals, amplifier for radio-frequency signals and method for amplifying such signals
CN100438331C (zh) * 2002-04-30 2008-11-26 Nxp股份有限公司 包含射频信号放大器的无线电设备、射频信号放大器和放大这种信号的方法

Also Published As

Publication number Publication date
AU2380201A (en) 2001-07-16
FI19992827L (fi) 2001-07-01
FI108686B (fi) 2002-02-28

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