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WO2000039848A3 - Procede et ensemble de test comportant une microplaquette de test de microplaquette equipee - Google Patents

Procede et ensemble de test comportant une microplaquette de test de microplaquette equipee Download PDF

Info

Publication number
WO2000039848A3
WO2000039848A3 PCT/US1999/030916 US9930916W WO0039848A3 WO 2000039848 A3 WO2000039848 A3 WO 2000039848A3 US 9930916 W US9930916 W US 9930916W WO 0039848 A3 WO0039848 A3 WO 0039848A3
Authority
WO
WIPO (PCT)
Prior art keywords
die
test
product
circuitry
testing
Prior art date
Application number
PCT/US1999/030916
Other languages
English (en)
Other versions
WO2000039848A2 (fr
Inventor
Benjamin N Eldridge
Igor Y Khandros
David V Pedersen
Ralph G Whitten
Original Assignee
Formfactor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/224,166 external-priority patent/US6429029B1/en
Priority claimed from US09/224,673 external-priority patent/US6551844B1/en
Application filed by Formfactor Inc filed Critical Formfactor Inc
Priority to JP2000591661A priority Critical patent/JP3754616B2/ja
Priority to EP99968547A priority patent/EP1141735A2/fr
Priority to KR10-2004-7015516A priority patent/KR100522070B1/ko
Priority to KR1020037015241A priority patent/KR100554324B1/ko
Publication of WO2000039848A2 publication Critical patent/WO2000039848A2/fr
Publication of WO2000039848A3 publication Critical patent/WO2000039848A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Measuring Leads Or Probes (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

La présente invention concerne un ensemble test( 2000) permettant de tester des circuits fabriqués (202, 302, 304) équipant une microplaquette produite (2011, 300). Dans un des modes de réalisation, l'ensemble test comprend une microplaquette de test (2010, 400) et un substrat d'interconnexion (2008) permettant de coupler électriquement la microplaquette de test à un contrôleur hôte (2002) communiquant avec la microplaquette de test. Cette microplaquette de test peut être conçue selon une méthodologie de conception (100) de microplaquette de test et de microplaquette produite, consistant à réaliser simultanément en un seul ensemble (102) des circuits de test (202A, 402, 404) et des circuits produits. En outre, on peut généralement concevoir les circuits de test pour couvrir le plus largement possible les cas de défauts des circuits produits correspondants, sans avoir à prendre en considération la surface de silicium qu'exigeront les circuits de test. La méthodologie de conception consiste ensuite à diviser (104) l'ensemble précité en microplaquette de test et en microplaquette produite. La microplaquette de test comprend le circuit de test, et la microplaquette produite comprend le circuit produit. La microplaquette produite peut comprendre certains circuits de test. Les microplaquettes produites et les microplaquettes de test peuvent alors être fabriquées sur des plaquettes de semi-conducteurs distincts. En séparant les circuits de produit et les circuits de test en puces distinctes, les circuits de test inclus sont soit éliminés, soit ramenés à un minimum dans la puce produite. Ceci permet de réduire à la fois la taille de la microplaquette et son coût de fabrication tout en couvrant le plus largement possible les cas de défauts des circuits produits dans la microplaquette. En outre, on peut utiliser cette microplaquette de test pour tester de multiples microplaquettes produites sur une ou plusieurs plaquettes.
PCT/US1999/030916 1998-12-31 1999-12-22 Procede et ensemble de test comportant une microplaquette de test de microplaquette equipee WO2000039848A2 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000591661A JP3754616B2 (ja) 1998-12-31 1999-12-22 半導体製品ダイのテスト方法及び同テストのためのテストダイを含むアセンブリ
EP99968547A EP1141735A2 (fr) 1998-12-31 1999-12-22 Procede et ensemble de test comportant une microplaquette de test de microplaquette equipee
KR10-2004-7015516A KR100522070B1 (ko) 1998-12-31 1999-12-22 반도체 제품 다이 테스트용 테스트 다이를 포함하는테스트 장치 및 반도체 제품 다이 테스트 방법
KR1020037015241A KR100554324B1 (ko) 1998-12-31 1999-12-22 반도체 제품 다이 테스트용 테스트 다이를 포함하는테스트 장치 및 반도체 제품 다이 테스트 방법

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US09/224,166 US6429029B1 (en) 1997-01-15 1998-12-31 Concurrent design and subsequent partitioning of product and test die
US09/224,673 1998-12-31
US09/224,673 US6551844B1 (en) 1997-01-15 1998-12-31 Test assembly including a test die for testing a semiconductor product die
US09/224,166 1998-12-31

Publications (2)

Publication Number Publication Date
WO2000039848A2 WO2000039848A2 (fr) 2000-07-06
WO2000039848A3 true WO2000039848A3 (fr) 2000-11-23

Family

ID=26918470

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/030916 WO2000039848A2 (fr) 1998-12-31 1999-12-22 Procede et ensemble de test comportant une microplaquette de test de microplaquette equipee

Country Status (5)

Country Link
EP (1) EP1141735A2 (fr)
JP (4) JP3754616B2 (fr)
KR (4) KR100522070B1 (fr)
TW (1) TW580744B (fr)
WO (1) WO2000039848A2 (fr)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338953A (ja) * 2000-05-29 2001-12-07 Mitsubishi Electric Corp 半導体試験装置、半導体試験方法および半導体装置
US6603323B1 (en) 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
JP2004317162A (ja) * 2003-04-11 2004-11-11 Masaki Esashi プローブカード、プローブピン及びその製造方法
US7202687B2 (en) * 2004-04-08 2007-04-10 Formfactor, Inc. Systems and methods for wireless semiconductor device testing
JP4679274B2 (ja) * 2005-07-07 2011-04-27 日本電子材料株式会社 プローブの製造方法
JP2007157944A (ja) 2005-12-02 2007-06-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
US7615861B2 (en) 2006-03-13 2009-11-10 Sandisk Corporation Methods of promoting adhesion between transfer molded IC packages and injection molded plastics for creating over-molded memory cards
US7986146B2 (en) * 2006-11-29 2011-07-26 Globalfoundries Inc. Method and system for detecting existence of an undesirable particle during semiconductor fabrication
WO2008119179A1 (fr) * 2007-04-03 2008-10-09 Scanimetrics Inc. Test de circuits électroniques utilisant un circuit intégré de sonde active
US8717053B2 (en) * 2011-11-04 2014-05-06 Keithley Instruments, Inc. DC-AC probe card topology
KR101378506B1 (ko) * 2012-02-17 2014-03-27 주식회사 오킨스전자 디스플레이 패널 검사장치
US9500675B2 (en) 2013-07-15 2016-11-22 Mpi Corporation Probe module supporting loopback test
TWI493194B (zh) * 2013-07-15 2015-07-21 Mpi Corp Probe module with feedback test function
TWI489113B (zh) * 2013-07-15 2015-06-21 Mpi Corp A probe card that switches the signal path
TWI510798B (zh) * 2015-02-24 2015-12-01 Powertech Technology Inc 通用型測試平台及其測試方法
KR101913274B1 (ko) 2016-11-18 2018-10-30 주식회사 에스디에이 프로브 카드의 전기적 특성 측정장치
KR102148840B1 (ko) * 2018-11-27 2020-08-28 주식회사 에스디에이 프로브 카드
JP7561563B2 (ja) 2020-10-05 2024-10-04 三菱電機エンジニアリング株式会社 半導体装置
CN115308563A (zh) * 2021-07-02 2022-11-08 台湾积体电路制造股份有限公司 测试集成电路的方法和测试系统
KR102736430B1 (ko) * 2023-01-20 2024-12-02 주식회사 이노웰 메모리 모듈 검사 방법 및 이를 적용하는 시스템

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0028091A1 (fr) * 1979-10-18 1981-05-06 Sperry Corporation Détection de défauts dans des plaquettes à circuit intégré et dans des plaquettes à circuit imprimé et systèmes contenant de telles plaquettes
EP0670552A1 (fr) * 1994-03-03 1995-09-06 International Computers Limited Procédé de mettre au point automatiquement pour circuits électroniques digitaux
US5497079A (en) * 1992-09-01 1996-03-05 Matsushita Electric Industrial Co., Ltd. Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card
US5576554A (en) * 1991-11-05 1996-11-19 Monolithic System Technology, Inc. Wafer-scale integrated circuit interconnect structure architecture
WO1997043656A2 (fr) * 1996-05-17 1997-11-20 Formfactor, Inc. Deverminage et essai au niveau plaquette
US5719449A (en) * 1996-09-30 1998-02-17 Lucent Technologies Inc. Flip-chip integrated circuit with improved testability
EP0845680A1 (fr) * 1990-02-16 1998-06-03 LEEDY, Glenn J. Fabrication et test de circuits intégrés avec des points de test de haute densité
EP0855651A2 (fr) * 1997-01-22 1998-07-29 Matsushita Electric Industrial Co., Ltd. Méthode de conception en vue du test et méthode de génération de séquence de test

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0304868A3 (fr) * 1987-08-28 1990-10-10 Tektronix Inc. Sonde multiple pour circuits intégrés en forme de galette
JPH01302850A (ja) * 1988-05-31 1989-12-06 Toshiba Corp テスト容易化半導体集積回路の製造方法
US5053700A (en) * 1989-02-14 1991-10-01 Amber Engineering, Inc. Method for wafer scale testing of redundant integrated circuit dies
JPH0582605A (ja) * 1991-09-24 1993-04-02 Mitsubishi Electric Corp 半導体集積回路素子およびウエハテスト検査方法
JPH05267405A (ja) * 1992-03-19 1993-10-15 Data Puroobu:Kk プローブカード
US5461573A (en) * 1993-09-20 1995-10-24 Nec Usa, Inc. VLSI circuits designed for testability and methods for producing them
JP3821171B2 (ja) * 1995-11-10 2006-09-13 オー・エイチ・ティー株式会社 検査装置及び検査方法
JP2940483B2 (ja) * 1996-08-28 1999-08-25 日本電気株式会社 Ｍｃｍ検査治具

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0028091A1 (fr) * 1979-10-18 1981-05-06 Sperry Corporation Détection de défauts dans des plaquettes à circuit intégré et dans des plaquettes à circuit imprimé et systèmes contenant de telles plaquettes
EP0845680A1 (fr) * 1990-02-16 1998-06-03 LEEDY, Glenn J. Fabrication et test de circuits intégrés avec des points de test de haute densité
US5576554A (en) * 1991-11-05 1996-11-19 Monolithic System Technology, Inc. Wafer-scale integrated circuit interconnect structure architecture
US5497079A (en) * 1992-09-01 1996-03-05 Matsushita Electric Industrial Co., Ltd. Semiconductor testing apparatus, semiconductor testing circuit chip, and probe card
EP0670552A1 (fr) * 1994-03-03 1995-09-06 International Computers Limited Procédé de mettre au point automatiquement pour circuits électroniques digitaux
WO1997043656A2 (fr) * 1996-05-17 1997-11-20 Formfactor, Inc. Deverminage et essai au niveau plaquette
US5719449A (en) * 1996-09-30 1998-02-17 Lucent Technologies Inc. Flip-chip integrated circuit with improved testability
EP0855651A2 (fr) * 1997-01-22 1998-07-29 Matsushita Electric Industrial Co., Ltd. Méthode de conception en vue du test et méthode de génération de séquence de test

Also Published As

Publication number Publication date
KR20030096418A (ko) 2003-12-24
WO2000039848A2 (fr) 2000-07-06
JP2007201471A (ja) 2007-08-09
JP2005049336A (ja) 2005-02-24
JP3754616B2 (ja) 2006-03-15
KR100554324B1 (ko) 2006-02-24
JP2002533738A (ja) 2002-10-08
TW580744B (en) 2004-03-21
KR100580405B1 (ko) 2006-05-16
KR20040094894A (ko) 2004-11-10
KR20010100002A (ko) 2001-11-09
EP1141735A2 (fr) 2001-10-10
JP2010249824A (ja) 2010-11-04
KR100522070B1 (ko) 2005-10-18
KR100548103B1 (ko) 2006-02-02
KR20050063812A (ko) 2005-06-28

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