+

WO2000011709A1 - Transistors à film mince et leur fabrication - Google Patents

Transistors à film mince et leur fabrication Download PDF

Info

Publication number
WO2000011709A1
WO2000011709A1 PCT/EP1999/005777 EP9905777W WO0011709A1 WO 2000011709 A1 WO2000011709 A1 WO 2000011709A1 EP 9905777 W EP9905777 W EP 9905777W WO 0011709 A1 WO0011709 A1 WO 0011709A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
gate
thin film
insulator layer
semiconductor
Prior art date
Application number
PCT/EP1999/005777
Other languages
English (en)
Inventor
Ian D. French
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Priority to EP99941553A priority Critical patent/EP1048067A1/fr
Priority to JP2000566881A priority patent/JP2002523898A/ja
Publication of WO2000011709A1 publication Critical patent/WO2000011709A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Definitions

  • TFTs thin film transistors
  • top-gate TFTs are commonly employed in flat panel displays (for example, an active-matrix liquid-crystal display) and in other types of large-area electronic devices.
  • the invention also relates to such devices.
  • TFTs which may form the switching elements in a cell matrix, for example in a flat panel display as described in United States Patent US-A-5, 130,829, the whole contents of which are hereby incorporated herein as referenced material.
  • the TFT devices may be fabricated with portions of an amorphous or polycrystalline semiconductor film to form the body of the transistor devices.
  • top-gate TFT structure compared to a bottom-gate TFT, is the ease with which a low resistance gate line can be made with a highly conductive top-gate metal such as aluminium.
  • top gate TFT One difficulty in the manufacture of a top gate TFT is the production of a vertical profile in the gate dielectric, which is aligned with the metal gate, using a process that does not etch away the underlying semiconductor layer. This difficulty arises because the top gate insulator layer is required to have a sufficient thickness to provide insulation between the gate conductor and the source conductor at the positions over the substrate where these two conductors overlap. However, as the thickness of the gate insulator increases, the difficulty of avoiding damage to the underlying silicon layer during etching also increases.
  • an insulated-gate top-gate thin film transistor wherein the insulated gate structure comprises a first gate insulator layer over the semiconductor body of the transistor, an intermediate conductive layer over the first gate insulator layer, a second gate insulator layer over the intermediate conductive layer and a gate conductor over the second gate insulating layer, the second gate insulator layer being thicker than the first gate insulator layer.
  • the intermediate conductive layer which forms part of the gate insulating structure, can act as an etch stop layer to enable the top, second gate insulator layer to be etched under the optimum conditions for producing a vertical profile aligned with the gate conductor, without having to compromise by using etching conditions which do not attack the underlying semiconductor layer.
  • the lower, first gate insulator layer is then only a relatively thin layer, which allows etching to be performed for a much shorter time with less risk of damage to the underlying semiconductor layer.
  • the intermediate conductive layer also acts as a field plate at a uniform potential, so that satisfactory operation of the transistor is ensured provided there is correct alignment of the field plate.
  • the exact profile of the thicker second gate insulator layer is therefore less critical than in known processes.
  • the first gate insulator layer may have a thickness of between 40 and 80 nm.
  • the semiconductor layer may have a thickness of approximately 40 nm, so that the lower insulator layer has a comparable thickness to that of the semiconductor layer.
  • the thicker, second gate insulator layer may have a thickness of between 200 and 300 nm, and thereby provides insulation at cross-over points of the upper gate electrodes and the lower source or drain electrodes of the transistor.
  • Both gate insulator layers preferably comprise silicon nitride
  • the first gate insulator layer may preferably comprise silicon-rich silicon nitride. This may improve the on conductance of the TFT.
  • the transistor is preferably an amorphous silicon TFT.
  • the invention also provides an electronic device comprising an array of thin film transistors of the invention, and the device may, for example, comprise a liquid-crystal display.
  • the invention also provides a method of manufacturing a thin film transistor having an insulated gate structure provided over a semiconductor layer which defines the body of the transistor and which is arranged as a semiconductor island, the insulated gate structure being formed by: depositing a first insulator layer, an intermediate conductor layer and a second insulator layer over the semiconductor layer; depositing and patterning a gate conductor layer over the second insulator layer; patterning the second insulator layer by etching to the intermediate conductor layer; and patterning the intermediate conductor layer and the first insulator layer by etching to the semiconductor layer.
  • the two gate insulator layers are etched by separate etching processes, so that these processes may be optimised for the individual layers.
  • second insulator layer etching is carried out to the intermediate conductor layer so that no account needs to be taken of the underlying silicon layer in the selection of the etching process for the upper insulator layer.
  • the method preferably initially comprises the steps of: depositing and patterning a metallic layer over an insulating substrate to define source and drain electrodes; and depositing the semiconductor layer over the patterned metallic layer.
  • This provides a top gate staggered TFT structure.
  • the first insulator layer and the semiconductor layer may both be patterned to define the semiconductor island before the deposition of the intermediate conductor layer. This enables the optimum conditions to be maintained for the interface between the semiconductor layer and the adjacent first insulator layer.
  • Figure 1 shows in plan view a pixel of a display device incorporating a thin film transistor of the invention
  • Figure 2 is a cross sectional view of a thin film transistor at stages in its manufacture by a known method
  • FIG 3 illustrates undercut problems which can result during the method illustrated in Figure 2;
  • FIG 4 is a cross sectional view of a TFT at stages in its manufacture by a method in accordance with the invention. It should be noted that these Figures are diagrammatic and not drawn to scale. Relative dimensions and proportions of parts of these Figures have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings.
  • Top-gate TFTs may form the switching elements of a display matrix or other large area electronic device, for example, as disclosed in US- A-5, 300,449.
  • Figure 1 shows the whole area of one cell of an active switching matrix of a flat panel display manufactured in accordance with the invention.
  • a cell comprises an electrode pattern 11 and 12 of, for example, ITO formed on an insulating substrate 10.
  • the substrate 10 may comprise a back plate of the display, for example a glass plate or polymer film.
  • Column conductors 11 of the pattern 11 , 12 form common source lines of the switching TFTs in the matrix columns.
  • Another part 12a of the pattern 11 , 12 forms a drain electrode of the TFT.
  • the bulk of Part 12 of the pattern 11 ,12 forms a pixel electrode 12b.
  • This pixel electrode 12b is integral with the drain electrode part 12a and also, in this example, with a part 12c which forms the bottom electrode of a pixel storage-capacitor with a row conductor 25 of a neighbouring cell.
  • the row conductors 25 form common gate lines of the TFTs in the matrix rows.
  • the switching TFT of each cell comprises a silicon transistor body 20a.
  • these bodies 20a are in the form of separate islands of a silicon film pattern.
  • the silicon film 20 is of, for example, a-Si:H.
  • polycrystalline silicon may be preferred for some displays and/or other large- area electronic devices.
  • Figure 2 illustrates some steps in a known manufacturing process for producing thin film transistors suitable for use in the device described with reference to Figure 1.
  • the cross sectional views in Figure 2 are taken along the line X-X in Figure 1.
  • the process comprises the steps of forming a source and drain electrode pattern 11 , 12 on a substrate 10.
  • a source and drain electrode pattern 11 , 12 may be deposited on a glass substrate 10, and wet etching may be performed in order to define the source and drain electrode pattern.
  • a silicon film 20 is deposited on the source and drain electrode pattern 11 , 12 to provide the transistor body 20a comprising the channel area 20c of the TFT.
  • a first gate insulator layer 30 is provided over the semiconductor layer 20, and the first gate insulator layer 30 and the semiconductor layer 20 are patterned using the same mask to define the semiconductor island forming the transistor body 20a. This results in the structure illustrated in Figure 2 Part A.
  • the deposition of the first gate insulator layer 30 over the semiconductor layer 20 before patterning of the semiconductor 20 improves the electrical characteristics of the interface between the insulator layer 30 and the semiconductor layer 20.
  • a second, upper gate insulating layer 32 is then deposited over the array and a gate conductor 34 is provided over the upper gate insulator 32.
  • the two gate insulator layers and the gate conductor layer 34 are patterned together using a common photolithographic mask on the gate conductor 34.
  • the source and drain regions 20s and 20d may be doped, for example using plasma doping with the top gate structure 30, 32, 34 masking the underlying intrinsic semiconductor channel area 20c.
  • the source and drain regions 20s, 20d of the semiconductor layer 20 may be formed by ion implantation, using the top-gate structure as an implantation mask.
  • FIG. 3 part B illustrates schematically the effect of positive undercut during the etching of the gate insulator. The effect is that part of the channel 20b beneath the gate is not modulated by the gate. This part of the channel is not doped and therefore the increased series resistance again results.
  • Figure 4 illustrates a method in accordance with the invention, for the manufacture of a thin film transistor of the invention.
  • Figure 4 Part A corresponds to Figure 2 Part A, so that known photolithographic and etching techniques have been employed to form the electrode pattern 11 , 12 from a film of electrode material deposited on the insulating substrate 10.
  • the electrode material may, for example, comprise ITO.
  • the semiconductor layer 20 is an undoped silicon film, and preferably comprises hydrogenated amorphous silicon, and the lower, first gate insulating layer 30 may for example comprise silicon nitride.
  • the silicon layer 20 may have a thickness of approximately 40 nm, and the lower gate insulator layer 30 preferably has a thickness of between 40 and 80 nm.
  • the silicon nitride layer 30 may comprise silicon-rich silicon nitride, which has been found to reduce the interface state density at the insulator/semiconductor boundary.
  • a two- layer gate insulator 4 for an insulated-gate TFT structure is described in the article "Amorphous Silicon Thin Film Transistors with Two-layer Gate Insulator" from Appl. Phys. Lett. 54 (21), 22 May 1989, pages 2079 to 2081.
  • an additional conducting layer 31 is deposited over the array as shown in Figure 4 Part B, and using known techniques.
  • This conductive layer 31 may comprise a metal layer, for example aluminium, or may comprise a semiconductor layer which is preferably subsequently doped to increase the conductivity.
  • the upper, second gate insulator layer 32 and the gate electrode layer 34 are then deposited, in the manner described with reference to Figure 2 Part B.
  • the gate electrode layer 34 for example aluminium, is etched in a conventional manner using an appropriate etchant and a photolithographic mask.
  • the metal gate may be wet etched.
  • the upper, second gate insulator layer 32 is then etched using the same photolithographic mask, and using an etchant for which the conductive layer 31 acts as an etch stop.
  • a dry, reactive ion etching process may be employed for this purpose, which can be controlled to provide vertical side walls for the insulator layer 32.
  • the conductor layer 31 is etched, and the lower insulator layer 30 may then be removed using a wet etching process. This wet etching process should produce a minimum undercut because the thickness of the lower gate insulator 30 can be kept to a minimum.
  • the gate conductor layer 34 may itself be used as a mask for the etching of the insulator layers 30 and 32.
  • the conducting layer 31 acts as a field plate in the TFT structure, so that if the upper, first gate insulator layer 32 is over etched (for example as shown in dotted lines in Figure 4 Part C) or if there is some undercut, the field plate defined by the conductor layer 31 provides a uniform potential layer which redistributes the electric field over the entire width of the channel.
  • a silicide-forming metal for example chromium may also be deposited to enable suicide areas to be formed over the source and drain areas of the TFT structure, to reduce the contact resistance at the source and drain of the TFT. This process is described in International Patent Application IB 97/01529.
  • the TFT may also have doped source and drain regions, which may be formed by plasma doping using the top-gate structure 30, 31 , 32, 34 to mask the underlying channel area, or they may be formed by ion implantation, using the top-gate structure 30, 31 , 32, 34 as an implantation mask.
  • the doping may alternatively be performed by doping the silicon film 20 from the bottom source and drain electrode pattern 11 , 12, for example as described in European Patent Application EP-A-0 221 ,361.
  • the vertical side-walls of the gate structure, and particularly the avoidance of undercuts as shown in Figure 3 is particularly important when ion implanted source and drain regions of the semiconductor layer 20 are to be formed. It is desirable that the ion implanted regions butt against the modulated channel area of the semiconductor layer.
  • the invention enables positive or negative undercut to be substantially avoided, particularly in the gate dielectric layer 30 between the intermediate conductor layer 31 and the silicon layer 20. This enables accurate ion implantation of the source and drain regions 20s, 20d of the silicon layer 20, which assists in limiting series resistances in the TFT structure.
  • the function of the conductor layer 31 as a field plate ensures that the full channel area is modulated by the gate, thereby avoiding the problems associated with positive undercut as described with reference to Figure 3 part B. If some negative undercut in the upper gate insulator layer cannot be avoided, shadowing as described with reference to Figure 3 part A is also avoided, because the lower gate insulator provides the insulator/channel interface.

Landscapes

  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Liquid Crystal (AREA)

Abstract

Selon cette invention, dans un transistor à film mince à grille supérieure et à grille isolée, la structure de la grille isolée comprend un première couche isolante placée au-dessus du corps semiconducteur du transistor, une couche conductrice intermédiaire placée au-dessus de la première couche isolante, une seconde couche isolante placée au-dessus de la couche conductrice intermédiaire et un conducteur de grille placé au-dessus de la seconde couche isolante. La couche conductrice intermédiaire permet d'attaquer séparément à l'acide les deux couches isolantes, et elle joue également le rôle d'une plaque de champ pour réduire l'effet de la découpe sous-jacente négative dans la couche isolante supérieure.
PCT/EP1999/005777 1998-08-22 1999-08-06 Transistors à film mince et leur fabrication WO2000011709A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99941553A EP1048067A1 (fr) 1998-08-22 1999-08-06 Transistors film mince et leur fabrication
JP2000566881A JP2002523898A (ja) 1998-08-22 1999-08-06 薄膜トランジスタおよびその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9818310.6 1998-08-22
GBGB9818310.6A GB9818310D0 (en) 1998-08-22 1998-08-22 Thin film transistors and their manufacture

Publications (1)

Publication Number Publication Date
WO2000011709A1 true WO2000011709A1 (fr) 2000-03-02

Family

ID=10837660

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1999/005777 WO2000011709A1 (fr) 1998-08-22 1999-08-06 Transistors à film mince et leur fabrication

Country Status (4)

Country Link
EP (1) EP1048067A1 (fr)
JP (1) JP2002523898A (fr)
GB (1) GB9818310D0 (fr)
WO (1) WO2000011709A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7838527B2 (en) 2002-11-13 2010-11-23 Novartis Vaccines And Diagnostics, Inc. Methods of treating cancer and related methods
US8586425B2 (en) 2009-12-31 2013-11-19 Au Optronics Corporation Thin film transistor
US8614216B2 (en) 2005-05-23 2013-12-24 Novartis Ag Crystalline and other forms of 4-amino-5-fluoro-3-[6-(4-methylpiperazin-1-yl)-1H-benzimidazol-2-yl]-1H-quinolin-2-one lactic acid salts

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132472A (ja) * 1984-07-25 1986-02-15 Hitachi Ltd 薄膜電界効果トランジスタの製造方法
US5008218A (en) * 1988-09-20 1991-04-16 Hitachi, Ltd. Method for fabricating a thin film transistor using a silicide as an etch mask
JPH0582787A (ja) * 1991-09-19 1993-04-02 Sony Corp 薄膜トランジスタ型不揮発性半導体メモリ装置
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
EP0718895A2 (fr) * 1994-12-20 1996-06-26 Sharp Kabushiki Kaisha Mémoire non-volatile et son procédé de fabrication
US5751037A (en) * 1995-07-27 1998-05-12 Sony Corporation Non-volatile memory cell having dual gate electrodes
JPH10125810A (ja) * 1996-10-21 1998-05-15 Nec Corp 不揮発性半導体記憶装置およびその製造方法
WO1998027583A1 (fr) * 1996-12-19 1998-06-25 Koninklijke Philips Electronics N.V. Dispositifs electroniques et leur fabrication

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6132472A (ja) * 1984-07-25 1986-02-15 Hitachi Ltd 薄膜電界効果トランジスタの製造方法
US5008218A (en) * 1988-09-20 1991-04-16 Hitachi, Ltd. Method for fabricating a thin film transistor using a silicide as an etch mask
JPH0582787A (ja) * 1991-09-19 1993-04-02 Sony Corp 薄膜トランジスタ型不揮発性半導体メモリ装置
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
EP0718895A2 (fr) * 1994-12-20 1996-06-26 Sharp Kabushiki Kaisha Mémoire non-volatile et son procédé de fabrication
US5751037A (en) * 1995-07-27 1998-05-12 Sony Corporation Non-volatile memory cell having dual gate electrodes
JPH10125810A (ja) * 1996-10-21 1998-05-15 Nec Corp 不揮発性半導体記憶装置およびその製造方法
US5929479A (en) * 1996-10-21 1999-07-27 Nec Corporation Floating gate type non-volatile semiconductor memory for storing multi-value information
WO1998027583A1 (fr) * 1996-12-19 1998-06-25 Koninklijke Philips Electronics N.V. Dispositifs electroniques et leur fabrication

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Method of Matching the Gate to the Source Drain Ga in a Tft. September 1964.", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 7, no. 4, New York, US, pages 338 - 339, XP002122294 *
DATABASE WPI Section EI Week 199830, Derwent World Patents Index; Class U11, AN 1998-339405, OYAMA K: "Non volatile semiconductor memory with floating gate for multivalue information storage - has second control gate electrode arranged on second floating gate electrode via fourth gate insulating film" *
NAM-DEOG KIM ET AL: "AMORPHOUS SILICON THIN-FILM TRANSISTORS WITH TWO-LAYER GATE INSULATOR", APPLIED PHYSICS LETTERS,US,AMERICAN INSTITUTE OF PHYSICS. NEW YORK, vol. 54, no. 21, pages 2079-2081, XP000080572, ISSN: 0003-6951 *
PATENT ABSTRACTS OF JAPAN vol. 010, no. 184 (E - 415) 27 June 1986 (1986-06-27) *
PATENT ABSTRACTS OF JAPAN vol. 017, no. 418 (E - 1408) 4 August 1993 (1993-08-04) *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7838527B2 (en) 2002-11-13 2010-11-23 Novartis Vaccines And Diagnostics, Inc. Methods of treating cancer and related methods
US8614216B2 (en) 2005-05-23 2013-12-24 Novartis Ag Crystalline and other forms of 4-amino-5-fluoro-3-[6-(4-methylpiperazin-1-yl)-1H-benzimidazol-2-yl]-1H-quinolin-2-one lactic acid salts
US8586425B2 (en) 2009-12-31 2013-11-19 Au Optronics Corporation Thin film transistor

Also Published As

Publication number Publication date
EP1048067A1 (fr) 2000-11-02
JP2002523898A (ja) 2002-07-30
GB9818310D0 (en) 1998-10-14

Similar Documents

Publication Publication Date Title
US6204520B1 (en) Thin film transistor, liquid crystal display and fabricating methods thereof
US5371025A (en) Method of making thin film transistors
US5793072A (en) Non-photosensitive, vertically redundant 2-channel α-Si:H thin film transistor
EP0304657B1 (fr) Cellule matricielle active et son procédé de fabrication
KR100292922B1 (ko) 박막트랜지스터,박막트랜지스터의제조방법및액정표시장치
KR100205373B1 (ko) 액정표시소자의 제조방법
US6395586B1 (en) Method for fabricating high aperture ratio TFT's and devices formed
US6180438B1 (en) Thin film transistors and electronic devices comprising such
KR20020032586A (ko) 박막 트랜지스터 및 그 제조 방법
WO2002050917A1 (fr) Transistor en couches minces
EP0780892B1 (fr) Méthode de fabrication d'un transistor à couches minces inversé
US5981317A (en) Method of fabricating a thin film transistor
US6580127B1 (en) High performance thin film transistor and active matrix process for flat panel displays
US5347146A (en) Polysilicon thin film transistor of a liquid crystal display
KR20020050085A (ko) 박막 트랜지스터
US6534350B2 (en) Method for fabricating a low temperature polysilicon thin film transistor incorporating channel passivation step
KR20050052475A (ko) Ｔｆｔ, ｔｆｔ의 제조 방법, ｔｆｔ를 포함하는 디바이스및 ａｍｌｃｄ
CN100481491C (zh) 薄膜晶体管及其制造方法
JP2659976B2 (ja) 薄膜トランジスタとその製造方法
WO2000011709A1 (fr) Transistors à film mince et leur fabrication
JP3292240B2 (ja) 薄膜トランジスタ素子及びその製造方法
US6057182A (en) Hydrogenation of polysilicon thin film transistors
US6482685B1 (en) Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step
JPH10173195A (ja) 薄膜トランジスタ及びその製造方法
KR100193652B1 (ko) 액정 표시 소자의 박막 트랜지스터 제조방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1999941553

Country of ref document: EP

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWW Wipo information: withdrawn in national office

Ref document number: 1999941553

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1999941553

Country of ref document: EP

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载