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WO1999038085A1 - Procede et appareil d'application d'execution ordonnee de lecture et d'ecriture a travers une interface de memoire - Google Patents

Procede et appareil d'application d'execution ordonnee de lecture et d'ecriture a travers une interface de memoire Download PDF

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Publication number
WO1999038085A1
WO1999038085A1 PCT/US1999/001387 US9901387W WO9938085A1 WO 1999038085 A1 WO1999038085 A1 WO 1999038085A1 US 9901387 W US9901387 W US 9901387W WO 9938085 A1 WO9938085 A1 WO 9938085A1
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WO
WIPO (PCT)
Prior art keywords
memory
requests
processor
interface
reordering
Prior art date
Application number
PCT/US1999/001387
Other languages
English (en)
Inventor
Robert F. Sproull
Original Assignee
Sun Microsystems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems, Inc. filed Critical Sun Microsystems, Inc.
Priority to JP2000528921A priority Critical patent/JP2002510079A/ja
Priority to AU23361/99A priority patent/AU2336199A/en
Priority to EP99903307A priority patent/EP1047996A1/fr
Publication of WO1999038085A1 publication Critical patent/WO1999038085A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency

Definitions

  • the present invention relates to read/write interfaces between processors and memories. More generally, it relates to interfaces between clients of a memory mapped resource and that resource. In a particular embodiment, the invention provides a solution to the problem of efficiently using the interface while still ensuring that reads and writes are performed in proper sequence when a particular sequence is required.
  • Memory refers to a memory system, which may include data paths, controller chips, buffers, queues, and memory chips. While this disclosure describes the problems and solutions in data storage memory, it should be understood that the problems and solutions can be generalized in many cases for memory-mapped circuits which perform more than just storage of data (e.g,, memory-mapped I/O, memory-mapped compute devices) .
  • a “memory location” (or simply “a location”) is an individually addressable unit of the memory that can be addressed and that holds data (or transports the data to and/or from an I/O device or a compute device) .
  • a "client” is a central processing unit (CPU) , processor, I/O controller or other device which uses the services provided by the memory system.
  • CPU central processing unit
  • processor processor
  • I/O controller I/O controller
  • a "request” is an action performed by a client in using the services of a memory system.
  • a "read request” (or simply “a read”) is a request from a client to the memory requesting the contents of a memory location specified by an address of the memory location to be read; the read request is accompanied by the address of the read memory location.
  • a "write request” (or simply “a write”) is a request from a client to the memory requesting that the memory place a write value into a write memory location; the write request is accompanied by the write value and the address of the write memory location.
  • An “acknowledgment” (or simply “an ack”) is an indication returned by the memory to the client indicating that a request has been satisfied; an acknowledgment to a read request includes the data read from the specified memory location.
  • Pending reads is the set of read requests which are pending; a read request is “pending” from the time it is accepted by the memory until the memory issues an ack.
  • Pending writes analogous to pending reads, is the set of write requests which are pending; a write request is “pending” from the time it is accepted by the memory until the memory issues an acknowledgment.
  • concurrency When building memory systems for large computers, one feature which provides for high performance is concurrency, wherein more than one memory operation is in progress at the same time.
  • concurrency One limitation on concurrency is that a CPU, or other client, requires memory consistency. A memory appears consistent when a "read" of a memory location returns a value most recently "written” in that location. In some systems with concurrency, reads and writes are reordered into an optimized execution order to achieve higher performance, however this may lead to loss of consistency.
  • Consistency is easy to implement if memory requests are always processed in exactly the same order as they are issued by the client. Preserving the order exactly, however, is often not possible in high-performance memory designs which may need to reorder requests to speed up processing. For example, the system requirements might be such that read requests must be completed faster than writer requests because pending read requests hold up processing until the read data is returned. However reordering of requests is done, it must not violate the consistency that is inherent in the one-request-at-a-time memory model described above.
  • One set of reordering constraints are as follows:
  • Rule 1 A read of location X followed by a write of location X cannot be reordered among themselves.
  • Rule A is often implemented by adding "store buffers" to the processor.
  • Rule B is almost never implemented because its performance advantage is very slight. Nonetheless, Rules A and B give some insight into what can be done at the processor to increase concurrency and thus improve performance while still maintaining consistency.
  • MEMBAR An MEMBAR instruction provides a way for a programmer to enforce an order of reads and writes issued by client.
  • MEMBAR instructions are interspersed in instructions codes executed by a processor. When a processor is executing instructions and encounters a MEMBAR instruction, it holds up further read and write operations until the operations which preceded the MEMBAR instructions have completed.
  • Sproull -Sutherland discloses a method of determining whether the read and write operations have been completed (that patent/application is 5 commonly assigned to the assignee of the present application and is incorporated herein by reference for all purposes) .
  • SUN SPARC-V9 manual that reference explains how the ordering constraints are enforced by the processor. There, given a first operation and a second operation, if the second operation must not be performed before the first operation, the execution unit delays the submission of the second operation to the memory until the first operation is no longer pending.
  • the client maintains its record of pending reads and writes by noting (a) when it issues each new request and (b) when each request is eventually acknowledged, signifying that the request is no longer pending.
  • the processor holds up an operation instead of using a bandwidth-limited interface whenever the interface is available, performance may be lost as extra time would be needed to send the held-up request and the critical path involving that request would be lengthened. 6
  • Fenwick appears to show how barrier instructions operate in the context of the Alpha 21164 microprocessor, built by Digital Equipment Corporation.
  • a barrier instruction MB or "memory barrier”
  • the MB instruction is reported off-chip, and may be used at the interface between the microprocessor and the memory bus, but the MB instructions do not apparently pass over the memory bus .
  • the MB information is not needed beyond the bus.
  • a similar instruction is used in the memory interface of most microprocessors (for example, waiting for all pending memory transactions to complete before allowing any new memory requests to be issued) , but the interface circuitry is commonly provided on the microprocessor chip itself.
  • processor-memory interface which allows the processor to enforce execution order of concurrently submitted operations, even when multiple operations required to be ordered are submitted to the memory which may reorder operations for its own purposes.
  • a memory interface is provided between a processor and a memory which is capable of multiple concurrent transactions or accesses.
  • the interface between the processor and the memory carries read and write operations as well as "barrier" operations, where a barrier operation signals the non-reorderability of operations.
  • the barrier operations are used in connection with resolved regions and unresolved regions of a processor system's architecture.
  • the unresolved region is a region wherein operations may be reordered for efficiency or other reasons and the resolved region is a region wherein the 8 operations are in a fixed order from which they cannot be reordered.
  • reordering constraints can survive the travel through the unresolved region so that any necessary reordering between the unresolved region and the resolved region can occur. Since the unresolved region extends into the memory, it is possible for the memory to perform optimization reordering or other reordering of operations. Once the operations reach the boundary between the unresolved region and the resolved region, the operations are reordered, as needed, to comply with the constraints of the barrier operations .
  • the memory interface is an interface to one or more memory mapped input/output (I/O) devices or computational devices.
  • memory operations are initiated by more than one processor.
  • processor-memory boundary While the exact location of the processor-memory boundary might not be clear, the present invention is useful wherever reordering dictated by the memory system is being performed, as opposed to reordering dictated only by the processor.
  • FIG. 1 is a block diagram of a processing system according to the present invention.
  • FIG. 2 is a block diagram of a multiple processor processing system according to the present invention.
  • FIG. 3 shows an example of a request stream as might be used in the present invention.
  • FIG. 4 shows a variation of the request stream of
  • FIG. 3 as might be used in a dual -path request stream system.
  • FIG. 5 is a block diagram of a banked memory system according to the present invention. 9
  • a client specifying the sequence must be able to also specify when a portion of the sequence must be handled in the order specified and not reordered.
  • a processor might specify a sequence of memory requests. The memory requests are executed at a memory, after passing through processor logic and buffers, a processor-memory bus (which might be shared with more than one processor and/or more than one memory) , and an memory interface circuits interposed between the bus and the memory . Any of these intermediate elements might be adapted to reorder the sequence of memory requests.
  • a memory interface circuit includes a paging unit, for loading and unloading pages of memory from a slow, large memory to a fast, core memory where all memory requests happen within the core memory
  • the memory interface circuit might reorder memory requests so that all the requests to be done within one page of memory are done at once to reduce the number of page swaps required to fulfill all of the memory requests.
  • the order of the requests can be determined at any point in the path of these memory requests from a processor to a memory. However, if a system does reorder requests, there are some points in the path where the order of the memory requests is not 10 necessarily resolved or resolvable. The collection of these points is referred to herein as the "unresolved region" of the path and an "unresolved" pathway is a pathway, such as a network or a bus, which carries requests in an unresolved order. When a processor must be able to specify a particular order of handling, at some point the unresolved region must end. Beyond that point is referred to herein as the "resolved region" of the path.
  • operations are in a fixed order from which they will not be further reordered.
  • FIGS. 1-2 processor systems in which an order enforcing system according to the present invention might be used as there shown.
  • FIG. 1 shows a processor system 100 comprising a processor 102, a memory subsystem 104, an I/O subsystem 106 and a compute subsystem 108. Each of these components is coupled via a communications link 110. Each of the three subsystems is memory-mapped, i.e., processor 102 interfaces with the subsystem using addressed read and write requests as if the subsystem were an addressable memory. Communications link 110 could be a memory bus, a network, or the like.
  • Memory subsystem 104 is shown comprising a memory interface circuit 120 and a memory array 122.
  • processor 102 sends a read request or a write request over communications link 110 to memory subsystem 104, it is received and handled by memory interface circuit 120 and interface circuit 120 handles the storage and retrieval of data in the specified locations of memory array 122.
  • I/O subsystem 106 is shown comprising a memory-mapped I/O interface circuit 130 and the I/O devices are shown generally as 132.
  • Interface circuit 130 receives and handles requests from processor 102 in much the same way as interface circuit 120 handles memory requests.
  • Memory-mapped I/O is not the focus of this description and is well known, so many details are omitted here for brevity. 11
  • Compute subsystem 108 is shown comprising a memory-mapped compute interface circuit 140 and a compute device 142.
  • interface circuit 140 receives and handles requests from processor 102 over communications link 110.
  • Interface circuit 140 converts requests, which are formatted as requests to a particular memory location, into messages to and from compute device 142 according to a predetermined memory map and convention.
  • computer device 142 might be a floating point processor and, by convention, a read request from a particular memory address might be a request for the results of a floating point operation, while a write request to a particular memory address might be an operand used in a floating point operation.
  • the reordering enforcement system according to the present invention is not limited to bus-based systems.
  • I/O subsystem 106 and compute subsystem 108 are not as important as the understanding that ordering of requests can be important in these subsystems. For example, if processor 102 sends a write request to I/O subsystem 106 to configure an external I/O device (such as initializing a serial communications circuit) then processor 102 sends a read request to gather data from that I/O device, those requests should appear at the I/O device in the order required by processor 102.
  • interface circuit 140 or communications link 110 should return those requests to an order relative to each other that is the order in which processor 102 sent the requests, if either of those devices reordered the requests for its own internal efficiency.
  • the request stream shows read requests, write requests and barrier requests.
  • a barrier is sent to the memory subsystem to signal that the subsystem should not reorder requests across the barrier, i.e., that all requests received prior to the barrier must be handled before any request received after the barrier.
  • the barrier requests are indicated by the label "MEMIBAR" which is short for "memory interface barrier.” MEMIBAR requests should not be confused with MEMBAR instructions, which are instructions inserted into a program to control the operation of a processor. By contrast, the MEMIBAR requests are sent from the processor to the memory subsystem to enforce ordering.
  • requests are shown being sent to a memory subsystem, in order, from request 1 to request 14.
  • read requests include an address
  • write requests include an address and the data to be written (as the actual data is not relevant here, it is shown in FIG. 3(a) as "xx") .
  • requests 5 and 11 are barriers, and therefore the memory subsystem is free to reorder requests 1-4 among themselves, 6-10 among themselves and 12-14 among themselves.
  • the memory subsystem might otherwise group requests dealing with one page (requests 1, 4 and 6) to perform them before a page swap and group the remainder of the requests to perform them after the page swap.
  • request 5 is a barrier
  • request 6 cannot be reordered for execution before the page swap because that would require it to be executed before requests 2-3.
  • the barrier at request 5 ensures that request 6 (a write to address 309F) does not get reordered relative to request 4 (a read from address 309F) . This is necessary to ensure that the correct, pre-write, value is returned for the read request.
  • FIG. 3(b) shows an example of an alternate form of a request stream, wherein the over-restrictiveness can be avoided.
  • the barrier requests include an address to indicate the requests for which the barrier applies.
  • request 5 (“MEMIBAR 309F")
  • that barrier constrains only the relative reordering of requests which deal with address 309F, namely requests 4 and 6.
  • the memory subsystem can reorder requests 4 and 6 relative to requests 2 and 3 for more efficient paging.
  • request 14 can be reordered relative to requests 10-13, thereby allowing two read requests to be handled with a single read, as might occur when two processors are reading the same memory address .
  • barrier requests include addresses
  • excess of barrier requests e.g., a multitude of consecutive barrier requests, one per address being constrained by a barrier
  • the processor need not introduce barrier requests to enforce ordering of requests when one of the requests has already been acknowledged by the memory system. For example, the writes to location 3108 that appear on lines 3 and 13 must be ordered, but this example assumes that by the time the request on line 13 is issued, the request on line 3 has been acknowledged. In the Sproull-Sutherland dual-path memory, a more complex barrier procedure is needed.
  • the client a processor, in this example
  • HB half barrier
  • the client retains a record of pending reads and pending writes, and checks a new request before sending it to the memory. If there is a possible conflict, the client first 15 sends the HB markers and then issues the new request .
  • the memory system obeys the following rules:
  • Rule M3 requires that the paths be synchronized by HB markers. One way to do this is, when one path (read or write) processes an HB marker, the memory must hold that path up until the other path (write or read, respectively) reaches an HB marker. Intermediate elements which handle requests, but which are elements that need not serialize memory accesses, need not hold up for HB markers. Thus, Rule M3 should be applied only to elements which must serialize requests, such as the read/write interface at a memory chip.
  • read requests, write requests and HB markers travel through the memory system, they eventually come to a "memory chip" itself.
  • reads and writes may be traveling in separate paths, much like a two-ported memory (i.e., having separate read and write ports) . These ports may be designed with a "recursive interface" as described by Sproull -Sutherland. Inside this memory chip, the read and write paths finally meet, both potentially accessing the same memory location. To avoid consistency problems, Rule M3 is enforced there.
  • HB markers is inserted into the memory system by the client and those markers meet together at the memory chip, where they are used to synchronize the read and write channels.
  • the memory system may then apply arbitrary policies to requests, give priority to reads, reorder writes with respect to each 16 other (e.g., to take advantage of fast "page mode" on memory chips) , etc.
  • FIG. 4 shows the half barriers with addresses, as is the case in FIG. 3(b), but the dual -path memory system could also be implemented without half barrier addresses, as is the case in FIG. 3(a) .
  • the HB markers would be more powerful than necessary to establish the required ordering constraints if they did not include addresses. If an HB marker must be inserted before a read of location X or before a write of location X, it is because there is a pending read or write request for location X that might conflict. In such cases, the memory subsystem need only guarantee that pending requests for location X are not reordered with respect to the marker. Therefore, if the address X is attached to the HB marker, potential conflicts can be avoided without excessive restraint.
  • address bits to use in the marker might vary depending on the configuration of the memory system or the characteristics of the client.
  • the subset might be the "low order" bits of the address, or the "high order” bits of the address. Those skilled in the art of memory design will recognize that these are only examples and that other subsets of address bits could be used. 17
  • the objective in associating full or partial addresses with a marker is to reduce the frequency with which markers must be introduced into the memory system. The reason is that markers will prevent the memory system from reordering memory requests to achieve maximum performance.
  • bank With full or partial address tags, order enforcement can also be used with "banked” memory.
  • Large memories are often composed of memory banks, i.e., each bank is responsible for a range of memory locations.
  • the memory system has some form of “distributor” that accepts memory requests and distributes them to the proper bank, i.e., the bank that contains the memory location specified in the read or write request.
  • One special form of bank structure is known as "interleaving" in which low-order address bits select a memory bank. For example, in a two-bank system, even addresses are located in one bank and odd addresses in another.
  • the distributor delivers memory requests according to which bank contains the addressed location. It must also deliver markers. Markers without addresses must be delivered to every bank, because the memory system cannot know which requests are being prevented from reordering. Thus, for example, in a two-bank system, when the distributor receives a marker along the read path, it must send a marker to each of the two banks along their respective read paths. However, if a marker contains an address, it is necessary to forward that marker only to the one bank that contains that address . Note that partial address tags can be used with banked memory to the same effect, so long as the tag identifies the bank.
  • FIGS. 3-4 show operations on single memory addresses, it should be understood that the amount of memory processed as part of a particular request is not fixed, but can vary.
  • a memory system might be configured to handle several sizes of requests, such as a single word read, a cache line read (e.g., 16 words in a cache line), single word write, cache line write, or writing selected bytes within a word.
  • the "address" of the read or write request is the address of the first word of what may be a multi-word request. This may be important in deciding 18 whether a barrier that contains an address (first word address) can be reordered with respect to another request.
  • FIG. 5 is a block diagram of a banked memory subsystem 500 illustrating these points.
  • Banked memory subsystem 500 is shown with an interface circuit 501 coupling subsystem 500 and a processor and a distributor 502 which routes memory requests to the appropriate memory bank.
  • Two bank memories 503 are shown, but it should be understood that the memory can be divided into more than two banks.
  • read requests and write requests travel along separate paths, namely read path 504 and write path 506.
  • Distributor 502 examines the address of each request and, in this example, routes requests with odd addresses to bank memory 503 (1) using a bank read path 508(1) and a bank write path 510(1) and routes requests with even addresses to bank memory 503(2) using a bank read path 508(2) and a bank write path 510(2) . Reordering for memory optimization might occur at either interface circuit 501, distributor 502 or at the inputs of bank memories 503. The flow of barrier requests will now be described.
  • interface circuit 501 sends one half barrier along path 504 and one half barrier along path 506. As explained above, this will allow bank memory controller 500 to prevent reordering of read and write requests relative to each other even though they travel along separate paths .
  • the half barriers are detected by distributor 502
  • the half barrier from read path 504 is sent along bank read paths 508 and the half barrier from write path 506 is sent along bank write paths 510. Since a half barrier received on one of bank paths 508 or 510 will hold up memory accesses until the matching half barrier arrives, the broadcasting of half barriers to all bank memories 503 might be overly restrictive.
  • the barriers can include addresses as described above, or can include enough of a partial address so that distributor 502 can identify the bank to which the barrier applies. If such addresses or partial addresses are included, distributor 502 19 can selectively route the half barriers to only the bank memory containing the address for which the barrier applies.
  • distributor 502 does not need to hold up for half barrier markers to synchronize, but will send along half barrier markers and read or write request as received.
  • a processor has an interface to a distributed memory having both local memory and "remote" memory, where the remote memory is connected to the processor by a high speed network, a bus extension, or the like.
  • Half barrier markers will be sent to the remote memories just as they are sent to banks in the example shown in FIG. 5.
  • the systems described above implement marker (half barrier) synchronization at the memory chip interface, other variations are possible. All that is required is that the read and write paths synchronize at some point in their processing, beyond which no reordering is permitted (i.e., there is a nonzero "resolved” region). Such a synchronization point is possible at many different points in a memory system.

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Abstract

L'invention concerne une interface de mémoire située entre un processeur et un sous-système de mémoire capable de permettre plusieurs transactions ou accès concurrents. L'interface entre le processeur et la mémoire permet d'effectuer des opérations de lecture et d'écriture ainsi que des opérations de 'barrière', une opération de barrière signalant que des opérations ne peuvent être ordonnées de nouveau. Dans un autre aspect de l'invention, l'interface de mémoire fait interface avec un ou plusieurs dispositifs d'entrée/sortie (I/O) ou dispositifs de calcul à topographie mémoire.
PCT/US1999/001387 1998-01-23 1999-01-21 Procede et appareil d'application d'execution ordonnee de lecture et d'ecriture a travers une interface de memoire WO1999038085A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2000528921A JP2002510079A (ja) 1998-01-23 1999-01-21 メモリ・インタフェース間で読み書きの順序付けられた実行を強制する方法と装置
AU23361/99A AU2336199A (en) 1998-01-23 1999-01-21 Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
EP99903307A EP1047996A1 (fr) 1998-01-23 1999-01-21 Procede et appareil d'application d'execution ordonnee de lecture et d'ecriture a travers une interface de memoire

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US09/012,882 US6038646A (en) 1998-01-23 1998-01-23 Method and apparatus for enforcing ordered execution of reads and writes across a memory interface
US09/012,882 1998-01-23

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