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WO1999037048A1 - Remultiplexeur de flux de transport supportant un programme video - Google Patents

Remultiplexeur de flux de transport supportant un programme video Download PDF

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Publication number
WO1999037048A1
WO1999037048A1 PCT/US1999/000360 US9900360W WO9937048A1 WO 1999037048 A1 WO1999037048 A1 WO 1999037048A1 US 9900360 W US9900360 W US 9900360W WO 9937048 A1 WO9937048 A1 WO 9937048A1
Authority
WO
WIPO (PCT)
Prior art keywords
transport
packet
descriptor
program
packets
Prior art date
Application number
PCT/US1999/000360
Other languages
English (en)
Inventor
Regis Gratacap
William Slattery
Robert Robinett
Original Assignee
Skystream Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/007,212 external-priority patent/US6292490B1/en
Priority claimed from US09/006,964 external-priority patent/US6111896A/en
Priority claimed from US09/006,963 external-priority patent/US6246701B1/en
Priority claimed from US09/007,198 external-priority patent/US6064676A/en
Priority claimed from US09/007,199 external-priority patent/US6148082A/en
Priority claimed from US09/007,203 external-priority patent/US6195368B1/en
Priority claimed from US09/007,211 external-priority patent/US6351471B1/en
Priority claimed from US09/007,210 external-priority patent/US6351474B1/en
Priority to IL137277A priority Critical patent/IL137277A/en
Priority to CA002318415A priority patent/CA2318415C/fr
Priority to KR1020007007746A priority patent/KR20010034133A/ko
Application filed by Skystream Corporation filed Critical Skystream Corporation
Priority to BR9906963-6A priority patent/BR9906963A/pt
Priority to AU20304/99A priority patent/AU761704B2/en
Priority to JP2000540637A priority patent/JP2002510162A/ja
Priority to EP99900800A priority patent/EP1046253A4/fr
Publication of WO1999037048A1 publication Critical patent/WO1999037048A1/fr
Priority to NO20003599A priority patent/NO20003599L/no
Priority to HK01106995A priority patent/HK1036172A1/xx
Priority to NO20084376A priority patent/NO20084376L/no

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/236—Assembling of a multiplex stream, e.g. transport stream, by combining a video stream with other content or additional data, e.g. inserting a URL [Uniform Resource Locator] into a video stream, multiplexing software data into a video stream; Remultiplexing of multiplex streams; Insertion of stuffing bits into the multiplex stream, e.g. to obtain a constant bit-rate; Assembling of a packetised elementary stream
    • H04N21/23608—Remultiplexing multiplex streams, e.g. involving modifying time stamps or remapping the packet identifiers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation

Definitions

  • the present invention pertains to communication systems.
  • the present invention pertains to communication systems.
  • invention pertains to selectively multiplexing bit streams containing one or more programs
  • program means a collection of
  • MPEG-1 and MPEG-2 provide for hierarchically layered streams. That is, an audio-
  • video program is composed of one or more coded bit streams or "elementary streams"
  • ES such as an encoded video ES, and encoded audio ES, a second language encoded audio ES, a closed caption text ES, etc.
  • ES such as an encoded video ES, and encoded audio ES, a second language encoded audio ES, a closed caption text ES, etc.
  • Each ES in particular, each of the audio and video
  • ESs is separately encoded.
  • the encoded ESs are then combined into a systems layer
  • PS program stream
  • TS transport stream
  • TS is to enable extraction of the encoded ESs of a program, separation and separate
  • the TS or PS may
  • Audio ESs are typically encoded at a constant bit rate, e.g., 384 kbps.
  • Video ESs are typically encoded at a constant bit rate, e.g., 384 kbps.
  • Spatial encoding involves the steps of spatially and temporally encoding the video pictures. Spatial encoding
  • macroblocks e.g., a 4x4 array of luminance
  • I pictures are only spatially encoded, whereas other pictures, such as P and
  • B pictures are both spatially and motion compensated encoded (i.e., temporally predicted
  • Encoded I pictures typically have more bits than encoded P pictures and encoded P pictures typically have more bits than encoded B pictures. In any event,
  • MPEG-2 defines a buffer size constraint on encoded video ESs.
  • a buffer size constraint on encoded video ESs.
  • decoder is presumed to have a buffer with a predefined maximum storage capacity.
  • encoded video ES must not cause the decoder buffer to overflow (and in some cases, must
  • MPEG-2 specifically defines the times at
  • bit rate of the video ES the bit rate of the video ES
  • picture display rate the picture display rate and certain picture reordering
  • compressing a picture can be adjusted (as frequently as on a macroblock by macroblock
  • the data of each ES is formed into variable length program elementary stream or
  • PES packets contain data for only a single ES, but may contain data for
  • more than one decoding unit may contain more than one compressed picture, more
  • the PES packets are first
  • Each transport packet may carry payload data of only one type, e.g., PES
  • Each TS is provided with a four byte header that includes a
  • PID packet identifier
  • one PID is assigned to a video ES of a particular
  • a second, different PID is assigned to the audio ES of a particular program, etc.
  • the ESs of each program are encoded in relation to a single encoder system time
  • the decoder extracts the PCRs from the transport packets and uses the PCRs to recover the
  • the PES packets may contain decoding time stamps or "DTSs"
  • a DTS indicates the time, relative to the
  • the PTS indicates the
  • a TS may have transport packets that carry program data for more
  • Each program may have been encoded at a different encoder in relation
  • the TS enables the decoder to recover the specific system time clock of the program which the decoder desires to decode. To that
  • the TS must carry separate sets of PCRs, i.e., one set of PCRs for recovering the
  • the TS also carries program specific information or (PSI) in transport packets.
  • PSI program specific information
  • a program association table or "PAT" is provided which is carried in transport
  • the PAT correlates each program number with the PID of
  • mapping table (PMT).
  • the decoder can then extract from the transport packets the program
  • the decoder can then extract from the
  • the decoder recovers the encoder system time clock from the PCRs of the
  • ECMs entitlement management messages
  • EMMs entitlement management messages
  • CAT network information table
  • NIT network information table
  • ECMs are ES specific messages for controlling the ability of a decoder to interpret the ES
  • an ES may be scrambled and the descrambling
  • ECM ECMs associated with a particular ES.
  • EMMs in their own transport packets and are labeled with a unique PID.
  • condition access system is in a system referred to as a "conditional access system" to interpret portions of a TS.
  • a CAT is provided whenever
  • EMMs are present for enabling a decoder to locate the EMMs of the conditional access
  • the decoder is a part (i.e., of the set of decoders of which the decoder is a part (i.e., of the set of decoders of which the decoder is a part (i.e., of the set of decoders of which the decoder is a part (i.e., of the set of decoders of which the decoder is a part (i.e., of the set of decoders of which the decoder is
  • the NIT maintains various network parameters. For example, if multiple TSs
  • each program may indicate on which carrier frequency (the TS carrying) each program is modulated.
  • MPEG-2 requires that the TS be decoded by a decoder having
  • TS buffers of predefined sizes for storing program ES and PSI data.
  • MPEG-2 also defines
  • MPEG-2 requires that data
  • PCR indicates the time that the system time clock (recovered at the decoder) should have
  • Remultiplexing involves the selective
  • modification of the content of a TS such as adding transport packets to a TS, deleting
  • the PSI such as, the PAT and PMT, must be modified so that
  • bit rate of each program must not change to prevent TS and video decoder buffer underflow
  • the prior art has proposed a remultiplexer for MPEG-2 TSs.
  • remultiplexer is a sophisticated, dedicated piece of hardware that provides complete
  • a program encoder which compresses the video and audio of a single
  • the program encoder needs an unanticipated longer amount of time to encode the ESs and
  • the TS or ES data is transferred via an asynchronous communication
  • TS or ES functions over a network. For example, it is an object to place one or more TS or ES
  • TSs transport streams
  • Each TS is formed as a sequence of fixed
  • Each compressed program includes data for one or more
  • ESs compressed elementary streams
  • transport packets also carry program clock references (PCRs) for each program
  • Each program has a predetermined
  • bit rate is intended to be decoded at a decoder having a TS buffer and a video decoder
  • Each program is encoded in a fashion so as to prevent
  • PSI Program specific information
  • a remultiplexer node is provided with one or more
  • each adaptor including a cache, a data link control circuit connected to the cache
  • the adaptor is a synchronous
  • the data link control circuit has an input port for receiving
  • access circuit can be connected to an asynchronous communication link with a varying end-
  • the direct memory access circuit can access a memory
  • the memory can store one or more queues of descriptor storage
  • locations such as a queue assigned to an input port and a queue assigned to an output port.
  • the memory can also store transport packets in transport packet storage locations to which
  • the remultiplexer node includes a processor, connected to the bus, for processing transport
  • the data link control circuit When an adaptor is used to input transport streams, the data link control circuit
  • allocated descriptor is in a descriptor storage location of which the cache has obtained
  • the data link control circuit stores each retained transport packet at a transport
  • the direct memory access circuit obtains control of one
  • memory access circuit also obtains control of transport packet locations in the memory to
  • the data link control circuit When an adaptor is used to output transport packets, the data link control circuit
  • the data link control circuit also retrieves from the cache the transport
  • the data link control circuit outputs each retrieved transport packet in a unique time slot
  • the direct memory access circuit obtains from the memory for storage in the cache,
  • descriptor storage locations in which a last cached descriptor of the sequence is stored.
  • direct memory access circuit also obtains each transport packet stored in a transport packet
  • each descriptor is (also) used to record a receipt
  • time stamp indicating when a transport packet is received at an input port, or a dispatch time stamp, indicating the time at which a transport packet is to be transmitted from an
  • circuit records a receipt time stamp in the descriptor allocated to each received and retained
  • descriptors are maintained in order of receipt in the receipt queue. In the case of outputting
  • the data link control circuit sequentially retrieves
  • the data link control circuit transmits the retrieved transport packet to which
  • the remultiplexer node processor examines each descriptor in the
  • the processor allocates a descriptor of the transmit queue associated
  • the processor assigns a dispatch time to the allocated
  • the processor furthermore orders the descriptors of the
  • a unique PCR normalization process is also provided.
  • the processor schedules
  • each transport packet to be outputted in a time slot at a particular dispatch time
  • the PCR is adjusted based on a drift of the local reference
  • the data link control circuit that transmits such adjusted PCR
  • each such transport packet is outputted in a separate consecutive time slot.
  • processor calculates an estimated adjustment for each PCR in a transport packet scheduled
  • the estimated adjustment is based on a difference in output time
  • the processor adjusts the PCRs according to this estimated adjustment.
  • the descriptors are also used for controlling
  • the processor stores
  • control word information associated with contents of the transport packet in the control
  • the data link control circuit sets one or more of the processing indications of the allocated descriptor to indicate that the next step of processing of the sequence may be
  • a descrambler is provided for sequentially
  • descrambler processes the descriptor and transport packet to which it points. Specifically,
  • the descrambler if the descriptor points to a to-be-descrambled transport packet, the descrambler
  • the descrambler may be located on the (receipt) adaptor, in which case the
  • descrambler processing occurs after processing by the data link control circuit (e.g.,
  • the descrambler may access circuit (e.g., transfer to the memory).
  • the descrambler may access circuit (e.g., transfer to the memory).
  • control word information is a base address of a PLD
  • index-able control word table maintained by the processor.
  • the processor defines a sequence of one or more
  • the processor allocates a transmit descriptor of a transmit queue to
  • each to-be-transmitted transport packet and stores control word information associated with
  • the processor then sets one or more processing
  • a scrambler is provided for sequentially
  • the scrambler processes each accessed descriptor and
  • indications of the accessed descriptors are set to indicate that scrambling processing
  • the scrambler scrambles the transport packet pointed to by the accessed
  • the scrambler may be located on the (transmit) adaptor, in which case the scrambler
  • processing occurs after processing by the direct memory access circuit (e.g., transfer from
  • the scrambler may
  • descrambler processing occurs after processing by the processor (e.g., transmit queue
  • the control word information may be a base address
  • control word information is the control word itself, used to control
  • An asynchronous interface e.g., an Ethernet interface, ATM interface, etc.
  • An asynchronous interface is connected to the remultiplexer
  • node processor (e.g., via a bus) for receiving a video program bearing bit stream from a
  • Such as a transmit adaptor selectively transmits selected transport packets carrying received
  • the remultiplexer node memory stores packets containing data
  • the processor identifies each
  • the processor assigns as a transmit time to each of the identified
  • Such as a first adaptor selectively extracts only particular ones of the transport packets from
  • interface such as a second adaptor, reassembles selected ones of the extracted transport
  • the second adaptor receives packets, and, transport packets containing PSI, if any, into an outputted remultiplexed TS, according to the initial user specification for remultiplexed TS content.
  • processor dynamically receives one or more new user specifications for remultiplexed TS
  • processor causes the first and second adaptors to dynamically cease to extract or reassemble
  • the processor may generate substitute PSI that references different transport packets as per
  • this seamless remultiplexing variation technique can be used to
  • a controller may be provided for generating a user specification indicating one
  • the processor continuously captures program definitions of an inputted TS.
  • the processor continuously captures program definitions of an inputted TS.
  • the second adaptor outputs in the outputted TS each transport packet containing
  • (adaptor) receives a TS at a predetermined bit rate, which TS includes variably compressed
  • null transport packets is inserted into a time slot of the received TS to maintain the
  • transport packets are available for insertion into the received TS at the respective transport
  • the processor selectively replaces one or more of the null transport
  • transport packets may contain PSI data or even bursty transactional data
  • the processor extracts selected ones of the transport packets of the
  • the selected transport packets are stored in the memory by the processor and first
  • the processor schedules each of the stored fransport packets
  • a second interface (adaptor) outputs each of
  • null transport packets occupy less
  • synchronous interface provides a bit stream containing transport packets.
  • processor assigns dispatch times to each of one or more selected ones of the transport
  • commands are generated as follows.
  • the processor enqueues
  • processor assigns an adaptor of the remultiplexer node to servicing the fransmit queue on
  • a network is provided with one or more communication links, and a
  • a destination node receives a first bit stream containing data of one or more
  • the destination node can be a remultiplexer
  • node as described above and in any event includes a processor.
  • the processor chooses at
  • the communication links collectively form a shared
  • the nodes are divided into a first set of one or more nodes for
  • the nodes of the second set select portions of the transmitted
  • bit streams and transmit one or more remultiplexed TSs as a bit stream containing the
  • Each of the transmitted remultiplexed TSs are different than the received
  • a controller node is provided for selecting the first and
  • the shared communication medium according to one of plural different signal flow patterns
  • reference clock at each circuit that receives transport packets is for indicating a time at
  • transmits transport packets is for indicating when to transmit each transport packet
  • a master reference clock to which each other one of the reference clocks is to be synchronized, is designated.
  • the current time of the master reference clock is
  • Each other reference clock is adjusted according to a difference
  • the increased flexibility enhances multiplexing yet decreases overall system cost.
  • FIG 1 shows a remultiplexing environment according to another embodiment of the
  • FIG 2 shows a remultiplexer node using an asynchronous platform according to an
  • FIG 3 shows a flow chart which schematically illustrates how fransport packets are
  • FIG 4 shows a network distributed remultiplexer according to an embodiment of the
  • FIG 1 shows a basic remultiplexing environment 10 according to an embodiment
  • a controller 20 provides instructions to a remultiplexer 30 using,
  • RPC remote procedure call
  • DCE digital distributed computing environment protocol
  • open open
  • DCE and ONC are network protocols employing
  • protocol stacks that allow a client process to execute a subroutine either locally on the same
  • platform e.g., controller 20
  • a remote, different platform e.g., in remultiplexer 30.
  • the client process can issue control instructions by simple subroutine calls.
  • the DCE or ONC processes issue the appropriate signals and commands to the
  • the controller 20 may be in the form of a computer, such as a PC compatible
  • the controller 20 includes a processor 21, such as one or more IntelTM Pentium
  • the I/O device includes a keyboard/mouse 27 and one or more I/O devices 29 connected to a bus 24.
  • the I/O device includes a keyboard/mouse 27 and one or more I/O devices 29 connected to a bus 24.
  • I O device 29 examples include
  • an RS-422 interface an Ethernet interface, a modem, and a USB interface.
  • the remultiplexer 30 is implemented with one or more networked "black boxes”.
  • the remultiplexer 30 black
  • communications links such as Ethernet, ATM or DS3 communications links.
  • Ethernet such as Ethernet, ATM or DS3 communications links.
  • remultiplexer 30 includes one or more black boxes which each are stand alone PC compatible computers interconnected by an Ethernet network (10 BASE-T, 100 BASE-T
  • one or more to-be-remultiplexed TSs namely, TSl, TS2 and TS3, are shown.
  • one or more TSs namely, TS4 and TS5, are outputted from the
  • the remultiplexed TSs TS4 and TS5 illustratively, include at least some
  • At least one storage device 40 e.g., a disk memory or server, is also provided.
  • the storage device 40 e.g., a disk memory or server.
  • device 40 can produce TSs or data as inputted, to-be-remultiplexed information for
  • storage device 40 can store TSs information or data produced by the remultiplexer 30, such
  • extraction destinations 60 These sources 50 and destinations 60 may themselves be
  • the sources 50 may also be devices
  • destinations may be display monitors, video tape recorders, communications
  • the data injection sources 50 supply TS, ES or other data to
  • the remultiplexer 30 e.g., for remultiplexing into the outputted TSs TS4 and/or TS5.
  • the data extraction destinations 60 receive TS, ES or other data from the
  • remultiplexer 30 e.g., that is extracted from the inputted TSs TSl, TS2 and or TS3.
  • one data injection source 50 may be provided for producing each of the inputted
  • to-be-remultiplexed TSs, TSl, TS2 and TS3 and one data extraction destination 60 may be
  • the environment 10 may be viewed as a network.
  • networked black box of the remultiplexer 30 in the environment 10 may be viewed as a
  • Each node may be connected by a synchronous or
  • the devices 20, 40, 50 and 60 are part of the remultiplexer 30.
  • FIG 2 shows a basic architecture for one of the network black boxes or nodes 100
  • remultiplexer node 100 The particular
  • remultiplexer node 100 shown in FIG 2 can serve as the entire remultiplexer 30.
  • remultiplexer node 100 can be distributed in separate nodes that are interconnected to each
  • multiple remultiplexer nodes 100 having the same architecture as shown in FIG 2, are
  • the remultiplexer node 100 is a Windows NTTM compatible PC
  • the remultiplexer node 100 includes one or more adaptors 110. Each
  • bus 130 which illustratively is a PCI compatible bus.
  • a processor 160 such as an IntelTM Pentium
  • ⁇ TM integrated circuit is also connected to the bus 130. It should be noted that the single
  • bus architecture shown in FIG 2 may be a simplified representation of a more complex
  • interfaces 140 and 150 are provided. These interfaces 140 and 150 are provided. These interfaces 140 and 150 are provided. These interfaces 140 and 150 are provided. These interfaces 140 and 150 are provided.
  • I/O 150 are connected to the bus 130, although they may in fact be directly connected to an I/O
  • expansion bus (not shown) which in turn is connected to the bus 130 via an I/O bridge (not shown)
  • the interface 140 illustratively is an asynchronous interface, such as an Ethernet
  • the interface 150 is a synchronous interface, such as a Tl interface. Communication on the
  • FIG 2 also shows that the remultiplexer node 100 can have an optional
  • scrambler/descrambler (which may be implemented as an encryptor/decryptor) 170 and/or
  • the scrambler/descrambler 170 is for
  • the GPS receiver 180 is for receiving a uniform clock signal for purposes of synchronizing the remultiplexer node 100.
  • Each adaptor 110 is a specialized type of synchronous interface. Each adaptor 110
  • descriptor and transport packet caches 114 an optional scrambler/descrambler 115 and one
  • DMA control circuits 116 may be part of one or more processors.
  • finite state automata i.e., as in one or more ASICs
  • the reference clock generator 113 illustratively is a 32 bit roll-over counter that
  • the system time produced by the reference clock generator 113 can be
  • the processor 160 can directly
  • the processor 160 can read the current
  • the processor 160
  • the processor 160 can set the count frequency of the reference clock generator in
  • the purpose of the cache 114 is to temporarily store the next one or more to-be-
  • the cache 114 also stores descriptor data for each transport packet. The purpose and structure of such
  • the cache 114 stores a filter
  • the cache 114 may also store control word information for use in scrambling
  • cache 114 is accessed by the data link control circuit 112, the DMA control circuit 116 and
  • the cache memory 114 may posses a facsimile or modified copy
  • the cache 114 should obtain the
  • a single device such as the cache memory 114 or host memory 120, has permission to
  • the cache memory modifies the contents of a data storage location at any one time.
  • the cache memory modifies the contents of a data storage location at any one time.
  • memory 114 obtains control of the storage location and a facsimile copy of the data stored
  • the cache memory 114 relinquishes confrol to the host
  • the DMA control circuit 116 is for transferring transport packet data and descriptor
  • the DMA control circuit 116 can
  • the DMA control circuit 116 can also obtain
  • the DMA control circuit 116 obtains
  • the data link control circuit 112 is for receiving transport packets from an incoming packet
  • the data link control circuit 112 filters out and retains only selected transport
  • the data link control circuit 112 discards each other transport
  • the data link control circuit 112 allocates the next unused descriptor to the
  • the data link control circuit 112 furthermore obtains the reference time from the reference
  • control circuit 112 records this time as the receipt time stamp in the descriptor that points
  • the data link control circuit 112 retrieves descriptors for
  • the data link control circuit 112 furthermore performs any final PCR
  • transport packets is synchronized with the precise alignment of the transport packet in the
  • the processor 160 is for receiving control instructions from the external controller
  • the processor 160 In response, to such instructions, the processor 160
  • processor 160 generates
  • interrupt receive handlers for processing each received transport packet based on its PID.
  • Receipt interrupt handlers may cause the processor 160 to remap the PID of a transport
  • processor 160 formulates and
  • transport packets for output to generate dispatch times for each transport packet, to
  • processor 160 may also assist in scrambling and descrambling as described in greater detail
  • the host memory 120 is for storing transport packets and descriptors associated
  • the host memory 120 storage locations are organized as follows.
  • a buffer 122 122
  • Descriptor storage locations 129 are organized into multiple rings 124. Each ring 124 is a sequence of descriptor storage locations 129 from a starting
  • One ring 124 is provided for each outgoing TS transmitted from the remultiplexer node 100
  • ring 124 is provided for each incoming TS received at the remultiplexer node 100.
  • a queue is implemented in each ring 124 by designating a pointer 124-3 to a head
  • Descriptor storage locations 129 are allocated for incoming transport packets
  • each descriptor stored in each descriptor storage location 129 includes
  • the field 129-1 is for
  • the processor 160 can use individual bits of the command
  • the processor 160 can preset a bit in the field 129-1 of a
  • the field 129-2 is for storing software status bits. These bits are neither accessed
  • the field 129-3 is for storing the number of bytes of a to-be-outputted, outgoing
  • transport packet typically 188 bytes for MPEG-2 transport packets but can be set to a
  • the field 129-4 is for storing a pointer to the transport packet storage location to
  • the field 129-5 is for storing the receipt time for an incoming received fransport
  • the field 129-6 is for storing various exceptions/errors which may have occurred.
  • the bits of this field may be used to indicate a bus 130 error, a data link error on the
  • the field 129-7 is for storing status bits that indicate different status aspects of a
  • descriptor such as whether or not the descriptor is valid, invalid pointing to an errored packet, etc. For example, suppose that multiple devices must process the descriptor and/or
  • the first two of these bits can be set to the values 0,1,2 or 3.
  • the value 2 indicates that the descriptor is valid and may be processed by the
  • value 3 indicates that the descriptor is valid and may be processed by the third to last device
  • the field 129-8 contains a transfer count indicating the number of bytes in a
  • the field 129-9 is for storing a scrambling/descrambling control word or other
  • the processor 160 can store information for use in scrambling or descrambling.
  • the processor 160 can
  • Field 129-10 is for storing a scheduled estimated departure time, actual departure
  • processor 160 for ordering received incoming transport packets for output or for noting the
  • one ring 124 is needed for receiving transport packets at a single input port, and one data
  • one DMA control circuit 116 and one ring 124 is needed for
  • transmit descriptors stored in queues associated with output ports.
  • the input and output ports referred to above may be the input or output port
  • the adaptor 110 is shown as having only a single data link control
  • multiple data link control circuits 112 and DMA control circuits 116 can be provided on
  • TSl illustratively is received at a first adaptor 110
  • TS2 illustratively is received at a second adaptor 110
  • TS3 illustratively is transmitted from a third adaptor 110 of the
  • TS 1 and TS2 may instead be received via synchronous or asynchronous interfaces at the
  • TSl and TS2 may be same node or at different nodes, and selected portions of TSl and TS2 may be
  • the transport processor 160 To enable acquisition of the content information, the transport processor 160
  • the data link control circuit 112 allocates the next unused descriptor
  • the data link control circuit 112 stores each received fransport packet in a transport packet storage location of the cache 114
  • the DMA control circuit 116 writes each transport packet to its corresponding
  • the DMA control circuit 116 may furthermore obtain control of the
  • allocated descriptors and transport packet storage locations is provided to the cache 114 for
  • the data link control circuit 112 i.e., allocation to future transport packets received
  • the 116 generates an interrupt.
  • the number i may be selected by the operator
  • the interrupt causes the processor 160
  • the processor 160 illustratively has a set of PID
  • FIG 3 illustrates two types of PID handler subroutine sets
  • Each DMA control circuit 116 generates a recognizably different interrupt thereby enabling
  • the processor 160 to determine which set of PID handler subroutines to use. In response to
  • step S2 the processor 160 executes step S2
  • the processor 160 examines the PID of each transport packet pointed
  • the processor 160 consults a table of pointers to receipt PID handler subroutines
  • processor 160 determines to consult a table of pointers to receipt PID
  • pointers to receipt PID handler subroutines includes 8192 entries, including one entry
  • indexed entry contains a pointer to, or address of, RIV0, RIV1,...,RIV8191, a subroutine
  • the processor 160 uses the PID of each transport packet to be executed by the processor 160. Using the PID of each transport packet, the processor
  • Each subroutine is advantageously predefined and simply mapped by
  • Each subroutine is composed of a collection of one or more basic building block processes.
  • building block processes include:
  • the processor 160 illustratively extracts the section of the PAT carried in the currently
  • the processor 160 is capable of identifying different versions
  • the processor 160 is also capable of identifying which version
  • the processor 160 also uses information carried in each updated PAT
  • the processor 160 can modify the pointer table 402 for the receipt PID
  • handler subroutine to insert pointer for appropriate PLDs (labeling transport packets bearing
  • PMT section data Like the PAT, multiple versions of the PMT may be
  • the processor 160 can determine in which PMT to store the extracted PMT section or program definition data.
  • the processor 160 may use PMT information to update
  • MPEG-2 requires that transport packets carrying different contents
  • transport packets bearing a second type of data If the transport packets of the first and
  • the processor 160 deallocates the descriptor
  • Descriptor deallocation can be achieved by the
  • processor 160 adjusting the sequence of descriptors resident in the descriptor storage
  • the processor identifies all of the allocated descriptors that follow the descriptor of the to- be-deleted transport packet in the ring 124 and moves each to the descriptor storage space
  • descriptor storage space 129 in the receipt queue for reallocation is a descriptor storage space 129 in the receipt queue for reallocation.
  • the PMT indicates, for each program, the PIDs of the
  • the processor 160 sets a PCR flag bit in the attribute field 129-1 of the
  • processor 160 illustratively calculates the current drift of the
  • reference clock generators 113 relative to the encoder system time clock of the program of
  • Drift may be determined by the following formula:
  • ARTS 12 RTS2 - RTS 1 ;
  • ⁇ PCR12 PCR1 - PCR2
  • ⁇ PCR12 is a difference in successive PCRs for this program
  • PCR2 is the PCR in the currently processed transport packet
  • PCR1 is the previously received PCR for this program
  • ⁇ RTS12 is a difference in successive receipt time stamps
  • RTS2 is the receipt time stamp recorded for the currently processed fransport
  • RTS1 is a previous receipt time stamp for the transport packet containing PCR1.
  • PCR1 and RTS1 are set equal to PCR2 and RTS2, respectively.
  • the drift is used for adjusting the PCR (if necessary) as described below.
  • processor 160 estimates the (ideal) departure time of the transport packet. Illustratively,
  • the estimated departure time can be
  • the processor 160 writes the
  • Scrambling/descrambling control words can be ES specific or used for a group of ESs (over
  • Descrambling or scrambling control words may be
  • processor 160 in executing this process may insert the base address for the
  • control word table or the control word itself, into the field 129-9 of a descriptor.
  • the processor 160 selects a PID handler for acquiring the PAT of each
  • PIDs of other PSI bearing transport packets such as program
  • subroutine for the PLD of the PAT illustratively selects receipt PLD handler subroutines for
  • the processor 160 illusfratively transmits to the controller 20 the
  • information may be selective, e.g., just a channel map of each TS showing the program
  • service designations such as video, audio 1, second audio presentation, closed caption text,
  • the information may be exhaustive e.g., including the PIDs of each
  • the operator uses the information provided, the operator generates a user specification for the
  • This user specification may specify:
  • PIDs assigned to other information e.g., bursty data
  • the user specification is then transmitted from the controller 20 to the remultiplexer node
  • the processor 160 receives the user specification and responds by selecting the
  • the processor 160 selects a subroutine in which the
  • processor inserts the process for estimating the departure time. For each PID labeling a transport packet containing scrambled data, the processor 160 selects a subroutine
  • the processor 160 can select a subroutine containing the process for
  • the processor 160 allocates a transmit queue to each device that transmits a
  • the processor 160 receives the remultiplexed TS, i.e., the third adaptor 110 that outputs the TS TS3.
  • the processor 160 receives the remultiplexed TS, i.e., the third adaptor 110 that outputs the TS TS3.
  • the processor 160 illustratively
  • step S4 the processor 160 executes step S4.
  • processor 160 examines descriptors from the receipt queues (and/or possibly other queues
  • the number j may illusfratively be programmable and advantageously is set equal to
  • step S4 the processor 160 examines each receive queue for descriptors
  • Each indexed entry includes one entry for, and indexed by, each PID 0x0000 to OxlFFF. Each indexed entry
  • TIV0, TIV1,..., TIV8191 contains a pointer to, or address of, TIV0, TIV1,..., TIV8191, a subroutine to be executed
  • controller 20 the controller 20, and modified as described below.
  • processor 160 the PLD of such a transport packet maps to a subroutine containing only this
  • the processor 160 simply skips the fransport packet and
  • the examined descriptor is not counted as one of the j transport packets
  • the PID of such a transport packet maps to a subroutine
  • processor 160 allocates a transmit descriptor for this transport packet.
  • the processor 160 allocates a transmit descriptor for this transport packet.
  • the allocated transmit descriptor is then ordered
  • the processor 160 compares the estimated
  • each transmit descriptor of the sequence of transmit descriptors with later actual dispatch
  • transmit descriptor can then be stored in the descriptor storage location 129 made available
  • the processor 160 can determine the
  • the actual dispatch time is set by
  • the transport packet is presumed to be outputted at
  • transport packet slot time is assigned as the actual dispatch time.
  • the actual dispatch time is assigned as the actual dispatch time.
  • dispatch time is really an approximate time at which the data link control circuit 112 of the
  • third adaptor 110 (which outputs the remultiplexed TS TS3) submits the corresponding
  • the actual output time of the transport packet depends on the
  • TS2 may be different from the bit rate of the outputted TS, namely TS3.
  • TS3 the bit rate of the outputted TS
  • the transport packets will be internally buffered for a predetermined delay (that depends on
  • Both transport packets may have different estimated departure
  • estimated departure time (or receipt time) is assigned to the time slot and the actual dispatch
  • the other transport packet is assigned the next transport packet time
  • processor 160 illustratively takes steps to remove the latency incurred by this transport
  • the processor 160 determines that PCR latency adjustment is
  • PCR's are outputted. In the latter case, a different drift adjustment is used as described below. In all other cases, the time at which received PCR's are outputted is affected by
  • the transport packet containing the PCR is stamped with a receipt time
  • This receipt time stamp is used to
  • transport packets are dispatched according to their actual dispatch time relative to
  • reference clock generators 113 of all adaptors 110 are maintained in synchronicity.
  • remultiplexer node 100 in the outputted remultiplexed TS such as TS3.
  • the remultiplexer node 100 corrects for such drift.
  • part of the receipt handler subroutine for PCRs of each program is to maintain

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

L'invention concerne un procédé et un système (30, 30', 100, 100', 100'', 100''') de remultiplexage de données supportant un programme vidéo (TS1-TS5, TS10-TS20), utilisant un système (122, 124, 129-4) à base de descripteurs pour programmer la sortie opportune de paquets de transport, utilisant un descripteur et une technique de mise en antémémoire (116, 122, 124, 114) de paquets de transport pour découpler la réception et la transmission synchronisées de paquets de transport de tout traitement asynchrone (160, 120, 130, S2, 402, S4, 404), utilisant des descripteurs pour crypter et décrypter des mots de commande (129-9), optimiser la largeur de bande des flux de transport en remplaçant les paquets de transport nuls par des données de paquet de transport, et utilisant une technique (180) permettant de verrouiller des générateurs (113) d'horloge de référence internes multiples.
PCT/US1999/000360 1998-01-14 1999-01-07 Remultiplexeur de flux de transport supportant un programme video WO1999037048A1 (fr)

Priority Applications (10)

Application Number Priority Date Filing Date Title
EP99900800A EP1046253A4 (fr) 1998-01-14 1999-01-07 Remultiplexeur de flux de transport supportant un programme video
JP2000540637A JP2002510162A (ja) 1998-01-14 1999-01-07 ビデオプログラムを載せたトランスポートストリームの再多重化装置
AU20304/99A AU761704B2 (en) 1998-01-14 1999-01-07 Video program bearing transport stream remultiplexer
BR9906963-6A BR9906963A (pt) 1998-01-14 1999-01-07 Programa de vìdeo portando remultiplexador defluxo de transporte
IL137277A IL137277A (en) 1998-01-14 1999-01-07 A video program with a re-multiplication of a current carrier
KR1020007007746A KR20010034133A (ko) 1998-01-14 1999-01-07 트랜스포트 스트림 리멀티플렉서를 갖는 비디오 프로그램
CA002318415A CA2318415C (fr) 1998-01-14 1999-01-07 Remultiplexeur de flux de transport supportant un programme video
NO20003599A NO20003599L (no) 1998-01-14 2000-07-13 Remultiplekser for videoprogrambærende transportstrøm
HK01106995A HK1036172A1 (en) 1998-01-14 2001-10-05 Video program bearing transport stream remultiplexer
NO20084376A NO20084376L (no) 1998-01-14 2008-10-17 Fremgangsmate og anordning for remultipleksing av transportpakker i en transportstrom

Applications Claiming Priority (20)

Application Number Priority Date Filing Date Title
US720498A 1998-01-14 1998-01-14
US733498A 1998-01-14 1998-01-14
US09/007,212 US6292490B1 (en) 1998-01-14 1998-01-14 Receipts and dispatch timing of transport packets in a video program bearing stream remultiplexer
US09/007,210 1998-01-14
US09/007,211 1998-01-14
US09/006,964 1998-01-14
US09/007,210 US6351474B1 (en) 1998-01-14 1998-01-14 Network distributed remultiplexer for video program bearing transport streams
US09/007,199 1998-01-14
US09/007,203 1998-01-14
US09/007,211 US6351471B1 (en) 1998-01-14 1998-01-14 Brandwidth optimization of video program bearing transport streams
US09/007,198 1998-01-14
US09/007,203 US6195368B1 (en) 1998-01-14 1998-01-14 Re-timing of video program bearing streams transmitted by an asynchronous communication link
US09/007,334 1998-01-14
US09/007,199 US6148082A (en) 1998-01-14 1998-01-14 Scrambling and descrambling control word control in a remultiplexer for video bearing transport streams
US09/007,198 US6064676A (en) 1998-01-14 1998-01-14 Remultipelxer cache architecture and memory organization for storing video program bearing transport packets and descriptors
US09/006,963 1998-01-14
US09/006,963 US6246701B1 (en) 1998-01-14 1998-01-14 Reference time clock locking in a remultiplexer for video program bearing transport streams
US09/007,204 1998-01-14
US09/007,212 1998-01-14
US09/006,964 US6111896A (en) 1998-01-14 1998-01-14 Remultiplexer for video program bearing transport streams with program clock reference time stamp adjustment

Publications (1)

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WO1999037048A1 true WO1999037048A1 (fr) 1999-07-22

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Country Status (11)

Country Link
EP (1) EP1046253A4 (fr)
JP (1) JP2002510162A (fr)
KR (1) KR20010034133A (fr)
CN (1) CN100380853C (fr)
AU (1) AU761704B2 (fr)
BR (1) BR9906963A (fr)
CA (1) CA2318415C (fr)
HK (1) HK1036172A1 (fr)
IL (1) IL137277A (fr)
NO (2) NO20003599L (fr)
WO (1) WO1999037048A1 (fr)

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CN1293845A (zh) 2001-05-02
EP1046253A4 (fr) 2005-05-11
JP2002510162A (ja) 2002-04-02
HK1036172A1 (en) 2001-12-21
NO20084376L (no) 2000-09-13
IL137277A (en) 2006-10-05
CN100380853C (zh) 2008-04-09
EP1046253A1 (fr) 2000-10-25
KR20010034133A (ko) 2001-04-25
NO20003599L (no) 2000-09-13
BR9906963A (pt) 2001-10-30
NO20003599D0 (no) 2000-07-13
CA2318415C (fr) 2009-12-15
AU761704B2 (en) 2003-06-05
AU2030499A (en) 1999-08-02
IL137277A0 (en) 2001-07-24
CA2318415A1 (fr) 1999-07-22

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