WO1999035749A2

WO1999035749A2 - Reception of variable and run-length encoded data

Info

Publication number: WO1999035749A2
Application number: PCT/IB1998/002040
Authority: WO
Inventors: Howard Pein; John Dean; Michael Bakhmutsky; Richard Shen
Original assignee: Koninklijke Philips Electronics N.V.; Philips Ab
Priority date: 1997-12-30
Filing date: 1998-12-14
Publication date: 1999-07-15
Also published as: JP2001515685A; EP0963625A2; CN1252907A; WO1999035749A3

Abstract

In a receiver, a variable-length decoder (VLD) derives run-value pairs (RVP) from variable and run-length encoded data (ED) such as, for example, MPEG-encoded data. A run-value pair (RVP) comprises a coefficient value (CV) and a run length (RL). The run length (RL) indicates a number (N) of zero coefficients (0) which precede the coefficient value (CV), N being an integer. A processing circuit (PRC) processes the run-value pairs (RVP) to obtain a decoded data stream (DD). The processing circuit (PRC) comprises a clock circuit (CLC) and a control circuit (CON). The clock circuit (CLC) generates clock cycles (CC) which are synchronous with the decoded data stream (DD). With each run-value pair (RVP) having a run length (RL) unequal to zero, the control circuit (CON) stalls the variable-length decoder (VLD) a number (N) of clock cycles (CC). The number (N) of clock cycles is proportional to the number (N) of zero coefficients indicated by the run length (RL). In such a receiver, the processing circuit (PRC) requires relatively little buffer memory, thus allowing cost-efficient implementations.

Description

Reception of variable and run-length encoded data.

FIELD OF THE INVENTION

The invention relates to reception of variable and run-length encoded data. The variable and run-length encoded data may be, for example, video information which has been encoded in accordance with a Moving Pictures Expert Group (MPEG) standard.

BACKGROUND ART

The document ISO/TEC 13818-2 describes decoding steps for MPEG-2 encoded video. These steps include, amongst others, variable-length decoding, run-length decoding, inverse zig-zag scanning, inverse quantization and inverse discrete cosine transform. The variable-length decoding is typically the first decoding step which is carried out. It derives a series of run-value pairs from the MPEG-2 encoded video. A run-value pair comprises a coefficient value and a run length indicating a number of zero coefficients which precede the coefficient value. In the run-length decoding, the run length is used along with certain control signals to determine the correct position of the coefficient value within an 8-by-8 block of coefficients. The 8-by-8 block of coefficients is inversely zig-zag scanned and inversely quantized, before the inverse discrete cosine transform is carried out. The 8-by-8 block of coefficients thus transformed is further processed to obtain a decoded data stream comprising pixel values for pictures to be displayed.

SUMMARY OF THE INVENTION

It is an object of the invention to provide reception of variable and run-length encoded data which allows cost-efficient implementations.

The invention takes the following aspects into consideration. If a variable- length decoder decodes variable and run-length encoded data in a regular manner, the variable-length decoder will provide run-value pairs in an irregular manner. The reason is that, in the variable and run-length encoded data, run-value pairs are represented by respective codes which do not have a fixed size in terms of number of bits. Furthermore, a run-value pair will contribute to the decoded data stream by a number of bits which is not fixed either. Thus, if the decoded data stream is to have a constant bit rate, one or more buffer memories are required to absorb, as it were, non-synchroneity between various types of data.

In accordance with the invention, clock cycles being synchronous with the decoded data stream are generated and, with each run-value pair having a run length unequal to zero, the variable-length decoder is stalled for a number of clock cycles, the number of clock cycles being proportional to the number of zero coefficients indicated by the run length. As a result, the run-value pairs are effectively synchronized with the decoded data stream. Consequently, the run-value pairs can be processed in a regular manner to obtain the decoded data stream. Thus, processing steps subsequent to the variable-length decoding require a relatively small amount of buffer memory only, or even no buffer memory at all. Consequently, the invention allows cost-efficient implementations.

These and other aspects of the invention, as well as additional features which may be optionally used to implement the invention to advantage, are apparent from and will be elucidated with reference to the drawings described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

Fig. 1 illustrates basic features of the invention;

Fig. 2 illustrates an additional feature which may be optionally used to implement the invention to advantage;

Figs 3 illustrates an example of a receiver in accordance with the invention.

DETAILED DESCRIPTION OF THE DRAWINGS

First, some remarks will be made on the use of reference signs. Similar entities are denoted by an identical letter code throughout the drawings. Various similar entities may be shown in a single drawing. In that case, a numeral is added to the letter code, so as to distinguish similar entities from each other. The numeral will be between parentheses if the number of similar entities is a running parameter. In the description and the claims, any numeral in a reference sign may be omitted if this is appropriate.

Fig. 1 illustrates basic features of the invention. A variable-length decoder VLD derives run-value pairs RVP from variable and run-length encoded data ED. A run-value pair RVP comprises a coefficient value CV and a run length RL. The run length RL indicates a number N of zero coefficients 0 which precede the coefficient value CV, N being an integer. A processing circuit PRC processes the run-value pairs RVP to obtain a decoded data stream DD. The processing circuit PRC comprises a clock circuit CLC and a control circuit CON. The clock circuit CLC generates clock cycles CC which are synchronous with the decoded data stream DD. With each run-value pair RVP having a run length RL unequal to zero, the control circuit CON stalls the variable-length decoder VLD a number N of clock cycles : PAUSE=N*CC. The number N of clock cycles is proportional to the number N of zero coefficients indicated by the run length RL.

Fig. 2 illustrates an additional feature which may be optionally used to implement the invention to advantage. The processing circuit PRC comprises a selector SEL having a first and a second input II, 12. The first input II receives respective coefficient values CV from the variable-length decoder VLD. The second input 12 receives a zero-coefficient value 0. The selector SEL is switched to the second input 12 when the variable-length decoder VLD is stalled : PAUSE -> SEL=I2. If the Fig. 2 feature is applied, the selector SEL will provide a data stream which comprises coefficient values and, in between these coefficient values, a number of zero coefficients as indicated by the run length. Thus, if the Fig. 2 feature is applied, the run-length decoding is achieved without using a memory for this purpose. Consequently, the Fig. 2 feature contributes to cost-efficient implementations.

Fig. 3 illustrates an example of a receiver for MPEG-encoded data in accordance with the invention. The Fig. 3 receiver includes the features described hereinbefore with reference to Figs. 1 and 2. In addition, the Fig. 3 receiver includes an input memory INP in which received MPEG-encoded data is temporarily stored. It should be noted that the MPEG-2 standard prescribes such an input memory which must have a certain minimal size. The control circuit CON of the Fig. 3 receiver comprises a counter CNT. The processing circuit PRC of the Fig. 3 receiver includes an inverse quantizer IQ, a quantization matrix QMX, a block memory BLM, an address generator ADG, and an inverse discrete cosine transformer IDCT. Other processing elements which are needed to decode MPEG-encoded data, such as a motion compensator, are not shown. In this respect, reference is made to the document ISO/TEC 13818-2 in which such processing elements are described in detail.

The Fig. 3 receiver operates as follows. The variable-length decoder VLD decodes variable-length code words comprised in the MPEG-encoded data ED so as to obtain the run- value pairs RVP. The run-length RL of a run- value pair RVP is loaded into the counter CNT. The run-length RL is equal to the number N of zero coefficients which precedes the coefficient value CV of the run-value pair. Starting from the run-length RL, the counter CNT counts down one unit for every clock cycle CC it receives from the clock generator CLC. During the countdown, the counter CNT provides a control signal PAUSE which produces two effects. First, the variable-length decoder VLD is stalled so as to prevent it from supplying a new coefficient value to the selector SEL. Secondly, the selector SEL is switched to effectively provide a zero coefficient at each clock cycle during the countdown. The countdown continues until the contents of the counter CNT are zero. When the contents of the counter have been reduced to zero, the selector SEL is switched to provide the coefficient value CV belonging to the run- value pair, the run length of which was counted down. In a subsequent clock cycle, the counter CNT is loaded with the run length of the next run- value pair and the above-described process is repeated. Thus, run-length decoding is achieved by effectively stuffing zeroes into a processing pipeline.

Run-length decoded data LD provided by the selector SEL is passed through the inverse quantizer IQ and then stored in the block memory BLM in a synchronous manner. That is, every clock cycle CC, a new inversely quantized coefficient is supplied to the block memory BLM. The address generator ADG provides a new address every clock cycle CC. The addresses provided by the address generator ADG follow a certain cyclic pattern so as to implement an inverse zig-zag scan. The addresses are also used for reading out inverse quantization coefficients from the inverse quantization matrix QMX. The inverse quantizer IQ multiplies a non-zero coefficient in the run-length decoded data LD by the inverse quantization coefficient read out from inverse quantization matrix QMX. The inverse quantizer IQ simply passes non-zero coefficients in the run-length decoded data LD to the block memory BLM. Thus, in summary, in the Fig. 3 receiver, the run length RL comprised in each run-value pair RVP is used to stall the variable-length decoder VLD allowing it to be synchronous with a sequential coefficient processing in the processing circuit PRC. Hence, a buffer memory between the variable-length decoder VLD and the inverse quantizer IQ is not required. In this respect, it should be noted that most practical inverse discrete cosine transformers inherently include a block memory. Thus, the block memory BLM should effectively be considered as being a part of the inverse discrete cosine transformer IDCT.

The drawings and their description hereinbefore illustrate rather than limit the invention. It will be evident that there are numerous alternatives which fall within the scope of the appended claims. In this respect, the following closing remarks are made. There are numerous ways of physically spreading functions or functional elements over various units. In this respect, the drawings are very diagrammatic, each representing only one possible embodiment of the invention. For example, although Fig. 3 shows various logically independent functions as different blocks, these functions may be implemented as a single physical block.

Claims

CLAIMS:

1. A receiver for receiving variable and run-length encoded data (ED), the receiver comprising: a variable length decoder (VLD) for deriving run- value pairs (RVP) from the variable and run-length encoded data (ED), a run-value pair (RVP) comprising a coefficient value (CV) and a run length (RL) indicating a number (N) of zero coefficients (0) which precede the coefficient value (CV); and a processing circuit (PRC) for processing the run- value pairs (RVP) to obtain a decoded data stream (DD), wherein the processing circuit (PRC) comprises: a clock circuit (CLC) for generating clock cycles (CC) which are synchronous with the decoded data stream (DD); and a control circuit (CON) for stalling the variable-length decoder (VLD) a number (N) of clock cycles with each run-value pair (RVP) having a run length (RL) unequal to zero, the number (N) of clock cycles being proportional to the number (N) of zero coefficients indicated by the run length (RL).

2. A receiver as claimed in claim 1, wherein the processing circuit (PRC) comprises a selector (SEL) having a first input (II) for receiving respective coefficient values (CV) from the variable-length decoder (VLD), and a second input (12) for receiving a zero- coefficient value (0), the control circuit being arranged to provide a control signal (PAUSE) for switching the selector (SEL) to the second input (12) when the variable length decoder (VLD) is stalled.

3. A method of receiving variable and run-length encoded data (ED), the method comprising the steps of: carrying out a variable length decoding (VLD) to derive run-value pairs (RVP) from the variable and run-length encoded data (ED), a run- value pair (RVP) comprising a coefficient value (CV) and a run length (RL) indicating a number (N) of zero coefficients (0) which precede the coefficient value (CV); processing (PRC) the run-value pairs (RVP) to obtain a decoded data stream (DD); generating clock cycles (CC) which are synchronous with the decoded data stream (DD); and stalling the variable-length decoder (VLD) a number (N) of clock cycles with each run-value pair (RVP) having a run length (RL) unequal to zero, the number (N) of clock cycles being equal to the number (N) of zero coefficients (0) indicated by the run length (RL).

4. A method as claimed in claim 4, wherein the processing of the run-value pairs (RVP) includes the steps of: supplying respective coefficient values (CV) obtained from the variable-length decoding (VLD), to a first input (II) of a selector (SEL); supplying a zero-coefficient value (0) to a second input (12) of the selector (SEL); and switching the selector (SEL) to the second input (12) when the variable-length decoder (VLD) is stalled.