WO1999034435A1

WO1999034435A1 - Circuit board, manufacture thereof, and electronic device using circuit board

Info

Publication number: WO1999034435A1
Application number: PCT/JP1998/005865
Authority: WO
Inventors: Yasunori Narizuka; Hiroyuki Tenmei
Original assignee: Hitachi, Ltd.
Priority date: 1997-12-25
Filing date: 1998-12-24
Publication date: 1999-07-08
Also published as: JPH11186335A

Abstract

A method of manufacturing a low-cost circuit board having a structure capable of preventing defective connections due to thermal stresses appearing in thermal bonding when a circuit board is connected with another through their corresponding terminals. The circuit board includes connection electrodes formed on it to make external connections. Each of the connection electrodes has a portion raised more than 10 νm above the upper level of wiring conductors, and the raised portion is used for external connections.

Description

Description: Circuit board, method of manufacturing the same, and electronic equipment using the same

The present invention relates to a structure of a wiring board (circuit board) and a method of manufacturing the same for electronic devices in which an LSI is mounted on a substrate and functions, and is particularly suitable for an electronic device requiring reliability. The present invention relates to a structure of a wiring board and a manufacturing method thereof. Background art

Conventional methods for connecting an LSI on a wiring board include wire bonding (WB) or tape auto-measurement because the number of LSI connection terminals is not so large and the connection pitch is not so narrow. The main method was to connect with Dobong Ding (TAB).

In these methods, since the connection electrodes of the LSI and the connection electrodes on the wiring board are connected by flexible wiring, the thermal expansion of the LSI and the wiring board in the connection and in the heating process after the connection is performed. There was almost no failure such as disconnection due to the coefficient difference. This is because in the case of the WB method, ultrafine wires of metal such as Au, A1, and Cu are flexibly deformed. In the case of the TAB method, connection terminals are formed on a flexible resin sheet together with wiring. The reason is that the connection part can be prevented from being broken by flexible deformation in response to external force. However, in these connection methods, connection terminals have to be arranged only on four sides of the LSI device due to the connection method itself. However, there is a drawback that it is not possible to respond sufficiently. As a connection method that can cope with this, there is a connection method that combines the arrangement of the array and the connection by solder balls. It is called connection (.C4) and is applied only to limited products such as large computers, and has a proven track record. However, in this connection method, the connection terminals of the board and the LSI are directly connected with only minute solder balls, so if there is a difference in the coefficient of thermal expansion between the LSI and the wiring board, the heat Due to thermal stress in the process, the connection is broken after connection. In order to prevent this, it is necessary to select a material for the substrate so that the thermal expansion coefficient of the substrate matches the thermal expansion coefficient of the LSI, which significantly increases the manufacturing cost of the substrate and makes the process more difficult. However, it was only applied to products with high price and low production volume due to adverse effects such as reduced yield.

In order to overcome the drawbacks mentioned above and to interconnect the LSI and the wiring board electrodes by arranging the area array, a resin is poured between the LSI and the board, and the overall adhesion of the resin is reduced. A connection method has been proposed to prevent thermal stress from concentrating only on the connection terminals by fixing it to the substrate, and some have begun to be put into practical use. This resin is called an underfill material, and this has expanded the application range of the interconnection of the LSI and the electrodes of the wiring board by the arrangement of the rear array. However, even in this method, when the expansion coefficient is extremely different, for example, when the LSI is directly connected to a printed wiring board, the effect of dispersing the thermal stress is insufficient, so that a small LSI having a relatively small thermal stress can be obtained. Only applied, not yet enough.

In recent years, the degree of integration of LSI has rapidly increased, and the size of LSI has tended to increase accordingly. In particular, this tendency is remarkable in logic LSIs, and the state-of-the-art logic LSIs are now exceeding 10 mm square. This trend will continue in the future. It is currently expected. To cope with such a situation, a chip carrier having a thermal expansion coefficient intermediate between the two is placed between the LSI and the wiring board, and the LSI is temporarily soldered to the upper electrode of the chip carrier, and the lower electrode of the chip carrier is connected to the chip carrier. A method of solder connection to a connection electrode of a substrate has been proposed. The combination of this method and the underfill described above has broadened the scope of application of the interconnection of LSI and wiring substrate electrodes by area array arrangement. However, this method requires a separate chip carrier with a specific coefficient of thermal expansion and also requires two connection steps, which is disadvantageous in terms of cost and connection technology. It has not yet spread.

In order to overcome such a drawback, as shown in FIG. 18, as shown in FIG. Covering the conductive resin layer 3 and forming a large number of minute resin holes 4 on the connection electrode 1, filling these minute holes 4 with the plating film 5, and using the protruding part on the resin layer 3 Then, a method of connecting LSIs by a thermocompression bonding method or an ultrasonic bonding method has been devised. In this example, since only the fine plating film 5 filled in the fine holes contributes to the connection, there are disadvantages that the connection area is small, the connection resistance is high, and the connection strength is low. Also, in the connection process, since bonding is performed to the plating film 5 that has a dotted surface on the surface of the flexible resin layer 3, ultrasonic bonding is difficult, and heat is directly applied to the resin layer 3. As a result, it is not possible to raise the temperature to a sufficiently high level, and thermocompression bonding is virtually unsatisfactory. Therefore, there is a problem in the connection method in this example. In order to reduce the stress, it is necessary that the resin layer 3 is in a state where it can easily move in the direction in which the shear force acts, that is, in the direction parallel to the surface of the substrate 2. 1 Because it covers a large area on and around it, the resin and the miniaturized plating film are soft, but the entire resin layer 3 needs to be moved over a large area. Deformation do not do. Therefore, it was found that further contrivance is required to impart flexibility to the connection portion and reduce the stress.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the related art, and has as its object to connect a wiring board and an LSI by heating, and to provide an auxiliary board such as a chip carrier. It is an object of the present invention to provide a substrate structure that can be connected with high reliability without using such a method and a method of manufacturing the same. Disclosure of the invention

As a method of connecting the board and L3I by heating, in addition to the above-mentioned method using solder balls, recently, connection using conductive resin or conductive adhesive has begun to be applied to mass production. However, this also requires heating, although not as much as C4, to cure the resin or adhesive. As described above, in the method of heating at the time of connection, a shear stress is generated at the connection portion after cooling due to a difference in thermal expansion coefficient between the substrate and the LSI. It is widely known that when the difference in the coefficient of thermal expansion is large, the connection is broken immediately after the connection due to the shearing force, and the breakage proceeds over a period of time. To avoid this, it is necessary to reduce the shear force in some way. In the present invention, the thickness of the connection pad on the substrate surface or the LSI surface is set to a specific thickness or more, and the electrode itself is easily deformed using the thickness of the electrode. The effect of the shearing force on the surface is suppressed. It is necessary to suppress the easily deformed part to the deformation below the breaking limit, which determines the conditions regarding the electrode thickness (height). In addition, the ease with which the electrodes themselves are deformed depends not only on the height but also on the electrode area as described above, but as described above, the number of connection terminals of the LSI necessarily increases. The flexibility of the electrodes tends to increase because it leads to a smaller area. If the original electrode area does not provide enough flexibility, The flexibility is improved by increasing the thickness of only part of the electrode and apparently reducing the area of the connection electrode. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a cross-sectional view showing a layout of a connection portion between a substrate and an LSI. FIG. 2 is a cross-sectional view schematically showing a deformation of a connection portion between the substrate and the LSI. FIG. 4 is a cross-sectional view for explaining a deformation model of a connection portion, FIG. 4 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention, and FIG. FIG. 6 is an explanatory diagram of a method of manufacturing a wiring board according to one embodiment of the present invention. FIG. 6 is an explanatory diagram of steps of a method of manufacturing a wiring board according to one embodiment of the present invention. FIG. 8 is a process explanatory view of a method of manufacturing a wiring board according to one embodiment of the present invention. FIG. 8 is a process explanatory view of a method of manufacturing a wiring board according to one embodiment of the present invention. FIG. 9 is a process explanatory view of a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 10 is a view illustrating an embodiment of the present invention. FIG. 11 is a process explanatory view of a method of manufacturing a wiring board, FIG. 11 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention, and FIG. FIG. 13 is a process explanatory view of a method of manufacturing a wiring board according to the embodiment, FIG. 13 is a process explanatory view of a method of manufacturing a wiring board according to an embodiment of the present invention, FIG. FIG. 15 is a process explanatory view of a method for manufacturing a wiring board according to an embodiment of the present invention. FIG. 15 is a cross-sectional view of the wiring board that allows electrode layout change according to the present invention. FIG. 6 is a cross-sectional view of a circuit board when the wiring board according to the present invention is applied to solder connection. FIG. 17 is a cross-sectional view of a connection portion when the present invention is applied to both a wiring board and an LSI. FIG. 18 is a cross-sectional view showing an example of a connection structure according to the prior art. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings.

Assuming that the coefficient of thermal expansion of the substrate 2 is _a l, the coefficient of thermal expansion of the LSI is ct 2, the size of the LSI chip is a, the connection temperature is T l, and the room temperature is Τ2, the LSI 6 and the substrate connected by heating A distortion is generated between the two due to the difference in the coefficient of thermal expansion. As shown in Fig. 1, considering the cross section of the LSI 6 and the substrate 2, and assuming that the distortion is the largest, and assuming that the connection electrodes 1 are provided at both ends of the LSI 6, when the connection is made at a high temperature, The opposite part, after cooling, has a displacement Χ = (1 — 2 2) (Τ 1 — Τ 2) a

Is generated. Actually, the displacement is always smaller than this value because the two are connected and restrain each other's deformation. All forces constraining each other are transmitted through the joints, and the joints are exposed to large forces.

Consider the case where the connection between the substrate 2 and the LSI 6 is simplified and the connection is made with the columnar medium 7, and the maximum displacement X theoretically occurs. The occurrence of this maximum displacement means that no deformation constraint has occurred between the two substrates, and no force is applied to the connection electrode portion. In order to achieve such a state, as shown in FIG. 2, the columnar medium 7 shown by the broken line is deformed to become 7 'shown by the solid line according to the displacement 8 of the LSI. Considering this deformation, it is originally deformed as represented by a complicated curve, and the surface of the part located outside the curve is stretched with the greatest force. Therefore, if the strain in this portion exceeds the breaking strain ε f which is a material characteristic of the columnar medium 7, the breakage of the medium 7 starts from this portion. Therefore, it is possible to achieve a reliable connection by suppressing the strain in this part at least below the breaking strain, and preferably below the limit of elasticity. Become.

As shown in Fig. 3, the side surface of the columnar medium 7 is modeled and approximated by two arcs 8, 8 '. In this case, since the upper half and the lower half are equivalent to each other in a point-pair manner, the length of the lower half of the side surface before deformation is defined as hZ2, and this is the circumference of the lower half arc after deformation. If stretched to the length, the elongation strain £ is expressed by the following equation.

ε = (2 (arctan (x / h)) ((x2 + h2) / 4) (^ T (x2 + h2) / x) -h / 2) / (h / 2)

= ((x2 + h2) arctan (x / h)) / hx-1

Assuming a specific case based on this equation and assuming that f is the breaking strain of Cu, which is a material often used as an electrode, those with relatively high purity are more than 20%. Therefore, if we apply the numerical value of 0.2%, which is used as the proof stress in the field of metallurgy as the amount of strain at the elastic limit of Cu, _£ = 0.2, ε = 0.00 It becomes 2.

When the displacement X is specifically estimated, assuming that the thermal expansion coefficient of the substrate is a normal printed substrate, α 1 = 17 X l O— ⁵ , and the magnitude of the thermal expansion coefficient of the LSI is 2 = 4 X 10 — ⁶ , LSI chip size a = 20 mm, connection temperature solidification temperature T 1 = 190 °, assuming soldering of eutectic solder based on tin-lead alloy C, if the room temperature is T 2 = 20 ° C, X = 22 m. If these values are applied to the above equation, the height h of the columnar medium 7 is

h = 39 μm (for 20% strain),

h = 3 9 3 m (for a distortion of 0.2%)

Also, if the chip size is a = 10 mm,

h = 22 μm (for chip size 10 mm, distortion 20./.)

Becomes

Therefore, in the above example, if Cu having a thickness of about 40 μm or more can be formed as an electrode, it is possible to prevent the connection portion from breaking immediately after connection _c Furthermore, if it can be formed with a thickness of about 400 _m, a connection having no problem from the viewpoint of reliability can be obtained.

If the electrode material is A1, the elongation at break is about 30 to 40% even if it is not particularly pure, so based on the above calculation, if the elongation is 40%, then the size of the LSI is In the case of a 10 mm square, a thickness of about 10 μm is sufficient.

Next, an embodiment of a method of manufacturing a wiring board having a thick electrode as described above will be described with reference to FIGS. 4 to 14. FIG.

First, as shown in Fig. 4, only the electrode 1 for connection to the outside is exposed from the window formed on the protective layer 1Q on the wafer after the previous process or the wiring board 2 on which the wiring has been formed. All the other wirings are covered with the protective layer 10.

In this state, as shown in FIG. 5, a resin layer 11 is formed on the entire surface of the wafer or the substrate. The resin layer 11 may be formed by a process of applying a varnish and performing beta treatment, or may be formed by attaching a resin sheet coated with a heat-resistant adhesive. The thickness of the resin layer 11 is preferably 1 m or more, which is good. The upper limit is preferably about 50 m in consideration of the subsequent steps, but is not strictly limited to this range.

Next, as shown in FIG. 6, a hole is formed in the resin layer 11 to expose the connection electrode 1 on the surface of the wafer or the wiring board. If the thickness of the resin layer 11 exceeds 1 Q μm, dry etching or laser processing is appropriate, but if the resin layer 11 is thinner, wet etching can also be used. . At the time of processing, selectivity for the processing is required between the resin layer 11 and the base of the hole. If the protective layer 10 formed on the surface of the wafer or wiring board is inorganic, the resin layer 11 The hole can be made larger than the size of the window of the protective layer 10. Protective layer 1 ◦ is organic In this case, since selectivity cannot be expected, it is better to form the hole smaller than the window of the protective layer 10 in terms of process stability.

After the drilling process is completed, the surface of the electrode 1 is cleaned, and then, as shown in FIG. 7, Cr or Ti is formed on the entire surface of the wafer or the wiring substrate, and then Cu is formed. Is formed. Since this two-layer film is used as a plating seed film 12 in a later step, it must have excellent adhesion to the surfaces of the resin layer 11 and the electrode 1. Although the two-layer film can be formed by electroless metal plating, it is preferable to form a thin film using Cr or Ti as an adhesive layer from the viewpoint of adhesiveness. When these thin films are formed, the sputtering method is most desirable in consideration of the adhesion of the resin layer 11 into the holes, and the film thickness of Cr or Ti is about 0.1 lm. 0 11 is about 1 / ^ 111 which is good.

After the formation of the plating seed film 12 is completed, a resin layer 13 having a predetermined thickness is formed on the plating seed film 12 on the entire surface of the wafer or substrate, as shown in FIG. The thickness of the resin layer 13 determines the final thickness of the electrode described later. Considering the distribution of the film thickness, it is preferable that the resin layer 13 is formed by attaching a resin sheet coated with a heat-resistant adhesive, but a varnish-like resin is applied. · It can also be formed by beta. Thereafter, as shown in FIG. 9, a hole is formed in the resin layer 13 on the electrode 1. In this case, as the drilling process, since the thickness of the resin layer 13 is as thick as several tens to several hundreds of μm, dry etching or laser processing is considered in consideration of prevention of side etching. Good. In particular, it has been confirmed that in laser processing, an ultraviolet laser can be used to form holes with a diameter of 50 μm and a depth of 250 m or more in polyimide sheets. If so, laser processing is optimal. In these processes, the holes are stopped by the metal layer, which is the seed film 12 of the plating, and the selectivity is reduced. Is good. The diameter of this hole may be larger or smaller than the diameter of the lower hole. Further, as described above, the smaller the hole diameter, the better the flexibility of the electrode. Therefore, reducing the hole diameter within the range of the restriction of the electric resistance facilitates the effect of the present invention. In addition, the position of the hole may be such that the exposed area of the surface of the electrode 1 can be secured as long as the resistance of the connection portion can be tolerated. May be out of range.

Further, when a resin sheet with an adhesive is used as the resin layer 13, a hole is formed in advance by an appropriate means, and the hole is aligned with the electrode 1 on the wafer or the wiring board, and then bonded. It is also possible to take.

After drilling, the bottom of the hole is cleaned, and as shown in Fig. 10, the metal film already formed is used as the seed film 12 and electroplating is performed, and the resin layer 1 is removed. Fill holes 1 and 13 with membrane 14. Cu plating is optimal for electrical plating, in which case a copper sulfate plating solution is better in terms of plating speed, stability, solution management, and the like. The plated film 14 needs to completely fill the hole, and if it is about several μm, it may be raised from the hole. If the thickness variation is large, plating is performed on at least the entire surface of the wafer or wiring board until the holes in the resin layer 13 are completely filled, and then the part that has become too thick using a method such as tape polishing. Should be removed.

Thereafter, in order to prevent the interface between the plating film 14 and the resin layer 13 from being exposed to the outside, as shown in FIG. 11, a thin resin film 15 is formed, and a portion corresponding to the upper surface of the plating film is formed. Open the window. At the interface between the plating film 14 and the resin layer 13, it is possible to impart adhesion by performing chemical treatment on the side surface of the hole of the resin layer 13 before plating, but the process is long. In addition, since the electrodes on the surface of the wafer or the wiring board may be corroded, the process of covering the interface with the resin film 15 is simple. Further, as shown in FIG. 12, a protective metal film 16 for protecting the plating film 14 at the time of connection and improving the connection reliability is provided on the plated film 14 in which the holes are filled. Similarly, a film is formed by electric plating. The material of this metal film 16 differs depending on how the wafer or wiring board is connected. For example, when using solder, two layers of Ni plating film and Au plating film are used. good _c also, if connection with something like conductive adhesive can be applied alone a u film.

Next, as shown in FIG. 13, by removing the resin layer 13 around the electrodes, the electrodes are separated so that they can move easily when an external force is applied to the electrodes. The removal of the unnecessary portion is preferably performed by dry etching or laser processing, similarly to the above-described hole processing. The processing is completed when the metal film as the seed film 12 of the plating is finally exposed. The resin layer 13 left around the plating film 14 does not need to be left for the purpose of the present invention. Rather, the remaining resin film adversely affects the deformation of the thickly stacked plating film due to external force. However, in order to protect the plating film 14 from the environment, it is desirable that the thickness of 5 μm or more remains to cover the plating film side surface. Finally, the metal film of the plating seed film 12 exposed at the bottom of the portion from which the resin layer 13 was removed by the above separation step was removed by wet etching as shown in FIG. Separate the electrodes. The Cr, Cu, and Ti described above as the metal film 12 damage the protective metal film 16 because they have etching selectivity with respect to the Au film formed to protect the plating film 14. Can be removed without any problem. When the electrical separation is completed, the wiring board according to the present invention is completed.

Here, when it is necessary to convert the electrode arrangement of the LSI to match the substrate side when forming a thick electrode on the wafer, as shown in FIG. Insulation layer 17 is formed on this, and wiring 18 is formed on this Then, a predetermined wiring pattern is formed, and a thick electrode is formed by applying the above-described process to the connection electrode provided on the wiring 18. According to this structure, it is possible to convert to an electrode array of, for example, an area array so as to avoid processing difficulties associated with forming a thick electrode at a fine pitch such as the peripheral array electrodes of an LSI.

Next, an example in which a wiring board according to the present invention is actually connected by using solder will be described with reference to FIG.

For example, for a wafer formed based on the process shown in Figs. 4 to 14. After supplying the solder balls 20 to the individual electrodes, the solder is once melted, and is shown in Fig. 16. Thus, the solder balls 20 are fixed to the electrode surface. Next, the wafer is positioned and placed at a predetermined position on the wiring board. After that, the connection is completed by performing normal reflow. Basically, this part of the process is no different from a traditional connection.

When solder is used for the connection, the deformation of the solder occurs in addition to the deformation of the electrodes, so that the effect of alleviating the shearing force is greater and the reliability can be further improved.

Furthermore, if the above-mentioned underfill material is filled into the voids of the connection portion after the solder connection, the connection portion is cut off from the outside air, and the occurrence of connection failure due to oxidation and corrosion can be prevented. It becomes possible.

In the case where it is difficult to form the electrodes as thick as described above, as shown in FIG. 17, thick electrodes are formed on both the substrate side and the LSI side, and this is soldered. Connect using In this way, the thickness of the electrode can provide a stress relaxation effect that is not the individual thickness but the sum of both thicknesses. Therefore, an electrode having a thickness of about 200 m can be formed on each substrate instead of the electrode having a thickness of about 400 m as described above. In addition, since the solder has a stress relaxation effect due to the solder in between, About 0 m is enough. This effect of reducing the thickness can reduce damage to the substrate in the plating step and technical difficulty in the step of removing the thick resin layer. Industrial applicability

As described above, according to the present invention, it is possible to directly connect an LSI to a substrate having a different thermal expansion coefficient from Si, which has been difficult in the past, for example, a substrate such as a printed wiring board. However, sufficient connection reliability can be ensured. Furthermore, since the connection can be made without the use of the conventional auxiliary substrate, the effective connection distance is shortened, and it is possible to sufficiently cope with future high-speed driving of the LSI.

In addition, no special technology or equipment is required for connection, and conventional equipment can be used as it is, so there is almost no increase in additional cost, and wiring for all electronic devices that function by mounting an LSI on a board It can be applied to substrates (circuit boards).

Claims

The scope of the claims

1. The connection part of the connection electrode formed on the circuit board for connection to the external circuit should be formed at least 10 μm thicker than the upper surface of the wiring connected to it, A circuit board characterized in that connection is made on the upper surface of the thickly formed electrode.

2. The circuit board according to claim 1, wherein a side surface of the thickly formed electrode is covered with an electrical insulator.

3. The circuit board according to claim 1, wherein a side surface of the thickly formed electrode is covered with a metal different from an electrode material.

4. The circuit board according to any one of claims 1 to 3, wherein an upper surface of the thick electrode is covered with a metal film suitable for connection to an external circuit. .

5. The circuit board according to claim 1, wherein a material of the thickly formed electrode portion is any one of Cu, Al, and Au.

6. For the connection electrodes on the circuit board to be connected to the external circuit, use the electroplating method to make the connection area more than 10 μm thicker than the upper surface of the wiring connected to it. A method for manufacturing a circuit board, characterized by being formed.

7. The circuit board according to any one of claims 1 to 5, wherein the circuit board is connected to another circuit board by a solder, a conductive resin, or the like. And electronic equipment.

8. The electronic device according to claim 7, wherein a gap between the connected circuit boards is filled with an organic resin.