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WO1999031848A2 - Procede permettant de commuter des donnees entre des trains binaires transferes dans des canaux a commutation de circuits - Google Patents

Procede permettant de commuter des donnees entre des trains binaires transferes dans des canaux a commutation de circuits Download PDF

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Publication number
WO1999031848A2
WO1999031848A2 PCT/SE1998/002358 SE9802358W WO9931848A2 WO 1999031848 A2 WO1999031848 A2 WO 1999031848A2 SE 9802358 W SE9802358 W SE 9802358W WO 9931848 A2 WO9931848 A2 WO 9931848A2
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WO
WIPO (PCT)
Prior art keywords
bitstream
time slot
data
bitstreams
internal
Prior art date
Application number
PCT/SE1998/002358
Other languages
English (en)
Other versions
WO1999031848A3 (fr
Inventor
Christer Bohm
Magnus Danielsson
Lars Gauffin
Per Lindgren
Original Assignee
Net Insight Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Net Insight Ab filed Critical Net Insight Ab
Priority to EP98964623A priority Critical patent/EP1040721A2/fr
Publication of WO1999031848A2 publication Critical patent/WO1999031848A2/fr
Publication of WO1999031848A3 publication Critical patent/WO1999031848A3/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Definitions

  • the present invention refers to a method, an apparatus, and a switch for switching data transferred in circuit switched channels between at least three unidirec- 5 tional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch.
  • 10 networks are being developed for the transfer of information using synchronous or isochronous, time division multiplexed bitstreams, wherein a bitstream is divided into cycles, each cycle in turn being divided into time slots .
  • DTM Dynamic synchronous Transfer Mode
  • a bus with two unidirectional, multi-access optical fibers connecting a number of network nodes may just as well be realized by any other kind of structure, e.g. a ring structure or a hub structure.
  • the bandwidth of each wavelength on the bus, i.e. each bitstream on each fiber, is divided into fixed rate cycles that in turn are divided into fixed size time slots. The number of slots in a cycle thus depends on the network's bit-rate.
  • the time slots are divided into two
  • Control slots are used for transferring of signaling messages between said nodes for the network's internal operation.
  • the data slots are used for the transfer of data between said users connected to the different nodes.
  • Each node is arranged to dynamically allocate time slots for its respective end users to use when sending or receiving information to or from other nodes . As a result, different end users have write access to different data slots.
  • multi-rate circuit switched channels may be established on a bitstream, each being defined by a respective set of one or more time slot positions within each frame of the bitstream.
  • switches are used to switch data between channels on different bitstreams.
  • a switch in a DTM network wherein data is transferred between ports of the switch using a switch internal slotted parallel ring bus that provides one slot for each pair of adjacent ports on the bus.
  • An advantage with using this solution for transferring data between ports of the switch is that a slotted ring bus of the kind described is simple to design and operate.
  • a problem with this prior art is that over-dimension of the internal ring bus capacity in relation to the bandwidth of the external bitstreams are necessary in order to prevent congestion, especially causing a problem at high throughput.
  • Another problem is that control of the internal bus resources is very limited, increasing the risk of temporary congestion or data loss due to inability to adapt to traffic on external bitstreams.
  • An object of the invention is therefore to provide a switch that provides increased control of switching capacity as well as increased possibilities of switching data in space and time, such as efficient space multicasting of multi-rate channels.
  • Another object of the invention is to provide a simple and fast mechanism for switching between multiple incoming and outgoing bitstreams.
  • data transferred in cir- cuit switched channels is switched between at least three unidirectional multi-channel time division multiplexed bitstreams that are accessed at respective ports of a switch using circuit switched channels of a switch internal unidirectional multi-channel time division multi- plexed bitstream that is accessed by said ports.
  • the invention is thus based upon the idea of transferring data between the ports of the switch using an internal bitstream providing similar features as the bitstreams used for transferring data between the nodes of the surrounding network.
  • channels for data transfer through the switch may be established, modified, and terminated using the invention in a similar way as channels are established modified and terminated within the network, control of switching resources is advantage- ously increased as compared to prior art.
  • the allocation of channels on said switch internal bitstream is dynamically adjusted based upon changes in allocation of channels on said two or more bitstream.
  • the allocation of channels on the internal bitstream could for example also be adjusted based upon the demand for switching capacity of individual channels .
  • the invention thus provides the very advantageous possibility of changing the switching capacity of the different switch paths through the switch, i.e. the switching bandwidth allocated to the different ports of the switch, dynamically as the demand for switching capacity changes.
  • the frame, or cycle, rate of the internal bitstream is synchronized to the frame rate of the network, or to a multiple of the frame rate of the network, thus providing compatibility with the outside network and facilitating the transfer of circuit switched channels through the switch.
  • each port will operate in relation to the internal bitstream like a node in a DTM-like network, i.e. will derive bit clock, detect the start of frame and provide time slot count from the internal bitstream by itself.
  • the bit clock of the internal bitstream is distributed to the different ports of the switch by a central control unit (for example like the one designated 150 in the figures to be described below) , whereas the detection of start of frame, the counting of slots and other features in relation to the internal bitstream are still handled at each port.
  • both bit clock rate and time slot count are distributed centrally, e.g. by said control unit.
  • the time slot count may be individual for each port, i.e. at a point in time when the time slot count at a second port is one (1) the time slot count at a first port will be two (2) , or may be common for all ports, i.e. at a point in time when the time slot count at a second port is one (1) the time slot count at a first port will also be one (1) .
  • a specific time slot count will correspond to different time slots position of the actual frame at different ports.
  • a problem will arise if the number of time slots of a frame (for example a frame comprising 4000 time slots) is larger than the number of time slots corresponding to the amount of time required for a time slot to travel once through the loop (for example a loop travel time corresponding to only 3000 time slots) .
  • a port or a similar unit will find itself transmitting slot number
  • one time slot of the frame is allocated on one side of said unit and another time slot of the frame is allocated on the other side of said unit. If, according to the situation discussed above, a channel is established to comprise slot number 1 on the receiving side of said unit and slot number 3001 on the transmitting side of said unit, the time slot data of time slot number 1 may simply be transferred by said unit directly from the received slot one (1) to the transmitted slot
  • Whether or not a received time slot will be multicasted, broadcasted, or transferred point- to-point between different output ports will depend on slot mapping instructions controlling the ports of the switch. Also, switching in the time domain as well as the space domain is easily achieved by control of the slot mapping instructions of the ports.
  • space multicasting i.e. the switching of time slot data from at least one input port to at least two output ports, may involve the selection of different single output ports for different input time slots, the selection of more than one output port for an input time slot as well as the selection of all output ports for said input time slot (broadcasting) .
  • means are provided for controlling, at each input port, for each time slot of a cycle of the corresponding bitstream at the input port, whether or not the time slot data thereof is to be written into said internal bitstream, and, if so, which time slot of the internal bitstream that said time slot data is to be written into.
  • means are provided for controlling, at each output port, for each time slot of said internal bitstream, whether of not the time slot data thereof is to be written into the respective output bitstream, and, if so, which time slot of the respective output bitstream that said time slot data is to be written into.
  • each output port may act as an input port as well, and each input port may act as an output port as well, thus providing bi-directional functionality at each port .
  • the switch comprises more than one internal bitstream, for example a set of two or more parallel bitstreams, wherein the ports of the switch may be connected to all, some or just one of said bitstreams .
  • time slot alloca- tion on said internal bitstream is divided into segments, a specific time slot then being used for communication between a first set of ports on a first portion of a bitstream carrying medium and for communication between another set of ports on another portion of said bitstream carrying medium, thus providing better utilization of the bitstream bandwidth.
  • a time slot position in each cycle of said at least one bitstream, containing data to be transferred to/from said internal bitstream is unambiguously associated with a respective time slot position in each cycle of said shared bitstream, said data hence being transferred thereto/therefrom.
  • there will be a unique slot-to-slot mapping for said time slot which will require a minimum of decision-making once the mapping has been established.
  • a channel is defined by a set of time slot positions in each cycle of said at least one bitstream and a corresponding channel is defined by a corresponding set of time slot positions in each cycle of said internal bitstream
  • data from any time slot position of said set of time slot positions of said at least one bitstream is mapped to/from any time slot position of said set of time slot positions of said internal bitstream while maintaining the relative order of data among said set of time slots as received from/transmitted to said at least one bitstream.
  • the next available time slot is selected, the advantage here lying in the fact that there is no need to wait for a certain slot in the second bitstream, instead data is directly mapped to the first time slot available to the channel that has not yet been filled with switched data.
  • the writing of said data from time slots of said first set of time slots into time slots of said second set of time slots is preferably done in maintained mutual order. This is of course required by many applications, and when used in such a context, the switch must be able to meet this requirement.
  • the term internal bitstream does not necessarily mean that the internal bitstream or the corresponding bitstream carrying medium must reside physically inside a switch circuit or the like, but may be arranged peripheral to the circuit, however still being used for the transfer of data between different ports of the switch.
  • the invention is especially advantageous in a DTM network.
  • the invention is not restricted to, for example, DTM networks but can be used in any synchronous network wherein data is transferred in circuit switched channels on unidirectional, multi-channel time division multiplexed bitstreams.
  • Fig. 1 schematically shows the structure of a time multiplexed bitstream
  • Fig. 2 schematically shows a switch according to an embodiment of the invention
  • Fig. 3 schematically shows an input port of the switch shown in Fig. 2;
  • Fig. 4 schematically shows an output port of the switch shown in Fig . 2 ;
  • Figs. 5a, 5b, and 5c schematically show three further embodiments of a switch according to the invention.
  • a unidirectional, multichannel time multiplexed bitstream of a circuit switched DTM network wherein a switch according to the invention is preferably incorporated will now be described with reference to Fig. 1.
  • the bitstream is divided into fixed rate, for example 125 ⁇ s, cycles, also referred to as frames.
  • Each cycle is in turn divided into fixed size, for example 64 bits, time slots.
  • the number of time slots within a frame depends on the network's bit rate.
  • the number of time slots 1-6 shown in the cycle of the bitstream in Fig. 1 is merely illustrative.
  • the time slots are divided into two groups, control slots C and data slots D.
  • Control slots C are used for control signaling between nodes of the network.
  • the data slots D are used for the transfer of payload data between said nodes .
  • each cycle comprises one or more synchronization slots S used to synchronize the operation of each node in relation to each cycle. Also, to make sure that the number of slots in one cycle will not overlap a following cycle, a guard band G is added after the last slot at the end of each cycle. As indicated in Fig. 2, the bitstream cycle is repeated continuously.
  • Each node connected to the bitstream has access to at least one control slot and to a dynamic number of data slots .
  • Each node uses its control slot to communicate with other nodes within the network, and data channels are established by a node allocating a certain amount of its data slots, forming a set of one or more time slot positions within each cycle, to the respective channel.
  • the number of data slots allocated to each node and to each channel depends upon the transfer capacity requested for channels handled by the respective node. If a channel requires a large transfer capacity, the node will allocate more data slots for that purpose. On the other hand, if only a small transfer capacity i required within a certain channel, the node may limit the number of data slots allocated thereto.
  • the allocation of time slots and data slots to different nodes may by dynamically adjusted as the network load changes .
  • a switch 100 according to an embodiment of the invention is shown.
  • the switch 100 comprises two ports 110 and 120, having at least read access to bitstreams 112 and 122 propagating on optical fibers 111 and 121, respectively.
  • the switch also comprises two ports 130 and 140 having at least write access to output bitstreams 132 and 142 propagating on optical fibers 131 and 141, respectively.
  • ports 110 and 120 will establish circuit switched channels on an internal shared unidirectional bitstream 162 transferred on, e.g., a parallel TDM bus 161 within the switch 100.
  • the internal bitstream 162 is accessed by all four ports and thus provides multi access.
  • the internal bitstream 162 is also divided into cycles which in turn are divided into time slots.
  • 112 is to be used for transmitting information to time slot position seven in each cycle of bitstream 132 as well as to time slot position nine in each cycle of bitstream 142.
  • a channel comprising one time slot in each cycle of the internal bitstream (assuming that the internal bitstream have the same frame rate as the external bitstreams), for example time slot number ten, will then be allocated for this purpose.
  • port 110 will transfer data from the first time slot in each cycle of bitstream 112 to the tenth time slot in each cycle of the internal bitstream 162.
  • port 130 will read data from time slot position ten in each cycle of the internal bitstream 162 and transmit said data into the seventh time slot of bitstream 132.
  • port 140 will read data from time slot number ten in each cycle of the internal bitstream 162, and transmit said data into the ninth time slot of bitstream 142.
  • Management of channels and allocation/ deallocation of time slot of the internal bitstream is controlled by a controller 170.
  • the controller communicates with the ports, for providing slot mapping instructions thereto, using private communication links (as indicated by dashed lines in Fig. 2) or using control slots on the internal bitstream 162.
  • the controller 170 communicates with other nodes of the network via the internal bitstream 162. (However, in an alternative embodiment, the ports themselves may be arranged to negotiate channel and time slot allocation using control slots of the bitstream 162. )
  • the frame or cycle rate of the internal bitstream 162 is controlled by a frame synchronization unit 190 which is arranged to synchronize the frame rate of the internal bitstream 162 to the frame rate of the network, in this case using the bitstream 112 as a reference. Also, multiples of the network frame rate may be used for the internal bitstream. As is understood, in an alternative embodiment, one of the medium access units may provide the frame synchronization feature, as described with reference to Figs. 5a, 5b, and 5c.
  • Fig. 2 shows the part of the switch 100 connected to the optical fiber 111 that transfers bitstream 112.
  • the port 110 which provide read access to time slots of bitstream 112, includes a medium access unit 115, a bit clock (not shown), a slot counter 116 and a frame clock (not shown) .
  • the bit clock is synchronized to the bit-rate of bitstream 112 and is used as input to the slot counter 116.
  • the slot counter 116 counts the time slot positions transferred by the fiber 111 and is cyclically restarted by the frame clock at the start of each new cycle.
  • the controller 170 stores information in a slot mapping table 117.
  • Each time slot position in a cycle of bitstream 112 has a corresponding entry in said table 117, and each entry that represents a time slot carrying data to be switched by the switch is provided with information for identifying the time slot position on said internal bitstream 162 to which the time slot data is to be transferred.
  • the count of the slot counter 116 is used to address an entry in the slot mapping table 117.
  • the slot counter 116 When, for example, the access unit 115 reads time slot position 3 from each cycle of bitstream 112, the slot counter 116 will address the third entry of the slot mapping table 117. At this entry, position information, in this case designating position number 10, has been stored by means of the controller 170 during channel setup. Upon addressing this third entry, osition number ten will be outputted and used to control that the data read from time slot three of bitstream 112 is written into time slot ten of the internal bitstream 162. Upon addressing the next entry, i.e. corresponding to time slot number four on the bitstream 112, no time slot is specified in the slot mapping table 117 and, hence, data from time slot number four of bitstream 112 will not be transmitted to the internal bitstream 162.
  • the controller 170 stores information in a slot mapping table 137.
  • Each time slot position in a cycle of the internal bitstream 162 has a corresponding entry in said table 137, and each entry that represents a time slot position carrying data to be switched to bitstream 132 is provided with information in the table 137 for identifying the time slot position on said bitstream 132 to which the respective data is to be transferred.
  • the count of a first slot counter 136, keeping track or the time slot positions passing on the internal bitstream 162 is used to address an entry in the slot mapping table 137.
  • the first slot counter 136 When, for example, time slot position 10 is read from each cycle of the internal bitstream 162, the first slot counter 136 will address the tenth entry of the slot mapping table 137. At this entry, position information, in this case position number 22, has been stored by means of the controller 170 during channel set-up. Upon addressing the tenth entry, position number twenty-two will be outputted and used to control that data read from time slot position ten of the internal bitstream 162 is written for output into time slot position twenty-two of an output frame buffer 138. Upon addressing, for example, the fourteenth entry, i.e.
  • the port 130 further includes a medium access unit 135, a bit clock (not shown), a second slot counter (not shown) and a frame clock (not shown) .
  • the bit clock is synchronized to the bit-rate of bitstream 132 and is used as input to the second slot counter.
  • the second slot counter counts the number of slots transferred by the fiber 131 and is cyclically restarted by the frame clock at the start of each new cycle. The count of the second slot counter is used to address entries in the frame buffer 138. Data stored in said frame buffer at a specific entry is transferred to the access unit 135, which then writes the data into a time slot having a position in a cycle of the bitstream 132 corresponding to the entry of the frame buffer 138.
  • time slots of an internal bitstream of a switch 10 are allocated to different ports over different segments of the bitstream carrying medium.
  • a time slot of the internal shared bitstream lets say time slot number four in each cycle thereof, is allocated for transfer of time slot data from port 11 to optional one or more of ports 15, 16, and 17 on one segment (to the left of the dashed line) , but is allocated for transfer of time slot data from port 18 to optional one or more of ports 12, 13, and 14 on another segment (to the right of the dashed line) of the bitstream carrying medium, thus providing better utilization of the bitstream bandwidth.
  • Fig. 5a time slot of the internal shared bitstream lets say time slot number four in each cycle thereof, is allocated for transfer of time slot data from port 11 to optional one or more of ports 15, 16, and 17 on one segment (to the left of the dashed line) , but is allocated for transfer of time slot data from port 18 to optional one or more of ports 12, 13, and 14 on another segment (to the right of the dashed line) of the bitstream carrying medium, thus providing better utilization
  • a switch 20 is, according to an embodiment of the invention provided, with two internal shared bitstreams are provided in the switch 20. All eight ports 21-28 of the switch 20 have access to both bitstreams and the bitstreams are propagating in opposite directions, as indicated by the arrows in Fig. 5b. Consequently, when transferring data from one port, for example port 27, to another port, for example port 25, of the switch 20, time slots may for example be allocated on the bitstream that has the shortest propagation distance between the two ports, thereby providing both quicker switching and efficient segmented allocation of a time slot.
  • a switch 30 according to another embodiment of the invention, which is described with reference to Fig. 5c, two parallel internal bitstreams are provided, both L ⁇ 00 to to > I- 1

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  • Time-Division Multiplex Systems (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

La présente invention concerne un procédé, un appareil et un commutateur permettant de commuter des données transférées dans des canaux à commutation de circuits entre au moins trois trains binaires unidirectionnels multi-canaux multiplexés par répartition dans le temps dont l'accès s'effectue aux ports respectifs d'un commutateur. Selon l'invention, les données sont transférées entre ces ports dans les canaux à commutation de circuits du train binaire unidirectionnel multi-canaux multiplexé par répartition dans le temps interne d'un commutateur dont l'accès s'effectue aux ports précités.
PCT/SE1998/002358 1997-12-18 1998-12-17 Procede permettant de commuter des donnees entre des trains binaires transferes dans des canaux a commutation de circuits WO1999031848A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98964623A EP1040721A2 (fr) 1997-12-18 1998-12-17 Procede permettant de commuter des donnees entre des trains binaires transferes dans des canaux a commutation de circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9704738-5 1997-12-18
SE9704738A SE9704738D0 (sv) 1997-12-18 1997-12-18 Method and apparatus for switching data between bitstreams of a circuit switched time division multiplexed network

Publications (2)

Publication Number Publication Date
WO1999031848A2 true WO1999031848A2 (fr) 1999-06-24
WO1999031848A3 WO1999031848A3 (fr) 1999-08-26

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PCT/SE1998/002358 WO1999031848A2 (fr) 1997-12-18 1998-12-17 Procede permettant de commuter des donnees entre des trains binaires transferes dans des canaux a commutation de circuits

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EP (1) EP1040721A2 (fr)
CN (1) CN1284254A (fr)
SE (1) SE9704738D0 (fr)
WO (1) WO1999031848A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001001638A1 (fr) * 1999-06-28 2001-01-04 Net Insight Ab Procede et dispositif pour la commutation temporelle et spatiale de donnees entre des trains de bits entrants et sortants, appartenant chacun a un domaine d'horloge
CN1866805B (zh) * 2005-12-05 2010-08-11 华为技术有限公司 混合速率时分复用交换芯片及其数据交换方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU623953B2 (en) * 1988-12-07 1992-05-28 Telstra Corporation Limited A communications method for a shared-medium communications network
FI90173C (fi) * 1992-01-31 1993-12-27 Nokia Telecommunications Oy Foerfarande och anordning foer anslutning av en datamaskin till ett digitalt telefonnaet eller annat digitalt oeverfoeringssystem
SE508889C2 (sv) * 1996-03-25 1998-11-16 Net Insight Ab Metod och anordning för dataöverföring med parallella bitströmmar

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001001638A1 (fr) * 1999-06-28 2001-01-04 Net Insight Ab Procede et dispositif pour la commutation temporelle et spatiale de donnees entre des trains de bits entrants et sortants, appartenant chacun a un domaine d'horloge
CN1866805B (zh) * 2005-12-05 2010-08-11 华为技术有限公司 混合速率时分复用交换芯片及其数据交换方法

Also Published As

Publication number Publication date
SE9704738D0 (sv) 1997-12-18
EP1040721A2 (fr) 2000-10-04
WO1999031848A3 (fr) 1999-08-26
CN1284254A (zh) 2001-02-14

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