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WO1999031723A1 - Procede pour ameliorer la planeite de plaquettes de semi-conducteur polies - Google Patents

Procede pour ameliorer la planeite de plaquettes de semi-conducteur polies Download PDF

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Publication number
WO1999031723A1
WO1999031723A1 PCT/US1998/025429 US9825429W WO9931723A1 WO 1999031723 A1 WO1999031723 A1 WO 1999031723A1 US 9825429 W US9825429 W US 9825429W WO 9931723 A1 WO9931723 A1 WO 9931723A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
back surface
subjecting
polished
side polishing
Prior art date
Application number
PCT/US1998/025429
Other languages
English (en)
Inventor
Eugene C. Davis
Brian M. Trentman
David L. Fronterhouse
Michael D. Dangel
William L. Smith
Jerry D. Smith
Original Assignee
Memc Electronic Materials, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials, Inc. filed Critical Memc Electronic Materials, Inc.
Publication of WO1999031723A1 publication Critical patent/WO1999031723A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes

Definitions

  • This invention relates generally to a method of processing semiconductor wafers, and more specifically to a method which improves the flatness of semiconductor wafers while providing a polished side and a rough side.
  • Semiconductor wafers are generally prepared from a single crystal ingot, such as a silicon ingot, which is trimmed and ground to have one or more flats for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers which are each subjected to a number of wafer shaping or processing operations to reduce the thickness of the wafer, remove damage caused by the slicing operation, and to create a highly reflective surface.
  • each wafer is first rounded, such as by an edge grinding operation, to reduce the risk of wafer damage during further processing.
  • a substantial amount of material is removed from the front and back surface of each wafer to remove surface damage induced by the slicing operation and to make the opposing front and back surfaces flat and parallel .
  • This stock removal of material is accomplished by subjecting the front and back surfaces of the wafers to a conventional lapping operation (which uses a lapping slurry comprising abrasive particles) , or a conventional grinding operation (which uses a disc with abrasive particles embedded therein) , or even a combination of both lapping and grinding operations.
  • the wafers are then etched by fully immersing each wafer in a chemical etchant to further reduce the thickness of the wafer and remove mechanical damage produced by the lapping and/or grinding operation.
  • the front surface of each wafer is polished, using a polishing pad and a polishing slurry comprising abrasive particles and a chemical etchant, to remove a small amount of material from the front surface of each wafer, such as about 10-20 microns.
  • the polishing operation removes damage induced by the etching operation and produces a highly reflective, damage- free front surface on each wafer.
  • the flatness of the wafer is a critical parameter to customers since wafer flatness has a direct impact on the subsequent use and quality of semiconductor chips diced from the wafer.
  • the flatness may be determined by a number of measuring methods .
  • “Taper” is a measurement of the lack of parallelism between the unpolished back surface and a selected focal plane of the wafer.
  • “STIR”, or Site Total Indicated Reading is the difference between the highest point above the selected focal plane and the lowest point below the focal plane for a selected portion (e.g., 1 square cm.) of the wafer, and is always a positive number.
  • SFPD Site Focal Plane Deviation
  • TTV Total Thickness Variation
  • the conventional method of processing a semiconductor wafer described above has a number of disadvantages.
  • immersion of the entire wafer in the chemical etchant deteriorates the flatness produced by the lapping or grinding operation.
  • the single-side polishing operation tends to further deteriorate the wafer flatness, with the flatness deterioration generally increasing as the amount of silicon removal increases .
  • a typical TTV value for wafers processed according to the above described process in which the wafers are single- side polished is in the range of about 3.00 microns.
  • wafers To reduce the negative effect on flatness caused by single-side polishing, it is known to instead subject the wafers to a double-side polishing operation in which the front and back surfaces of each wafer are polished simultaneously so that removal of material occurs uniformly on both sides of the wafer.
  • equipment used for double-side polishing operations includes opposing rotating pads (one corresponding to each side of the wafer) that rotate in opposite directions while working the polishing slurry against the wafer.
  • double-side polishing operations produce wafers having equally polished front and back surfaces, which has been found to be undesirable to customers because of subsequent material handling difficulties associated with the equally polished surfaces. Rather, customers prefer wafers having a polished front surface and a rough back surface .
  • U.S. Patent No. 5,389,579 discloses a method for single-side polishing semiconductor wafers while subjecting the wafers to a double-side polishing operation.
  • a protective film is placed on the back surface of the wafer to protect the back surface against material removal during the polishing operation so that only the front surface of the wafer is polished.
  • material removal occurs only on the front surface of the wafer.
  • wafer material must be simultaneously and preferably uniformly removed from both the front and back surfaces of the wafer.
  • a method of the present invention for processing a semiconductor wafer sliced from a single- crystal ingot comprises subjecting front and back surfaces of the wafer to a lapping operation or a grinding operation. The wafer is then subjected to an etching operation in which the wafer is immersed in a chemical etchant. Next, the wafer is subjected to a double-side polishing operation in which the front and back surfaces of the wafer are polished. The wafer is then subjected to a single-side etching operation in which the back surface, but not the front surface, of the wafer is exposed to a chemical etchant to roughen the back surface of the wafer.
  • Fig. 1 is a flow diagram showing a method of manufacturing a semiconductor wafer in accordance with the present invention.
  • Fig. 1 illustrates a preferred method of processing a semiconductor wafer according to the present invention.
  • the semiconductor wafer is sliced from a single-crystal ingot, such as by using a conventional inner diameter saw or conventional wire saw, to have a predetermined initial thickness.
  • the sliced wafer is generally disk-shaped, having a peripheral edge and opposing front and back surfaces.
  • the initial thickness of each wafer is substantially greater than the desired end or final thickness to allow for the removal of wafer material from the front and back surfaces during subsequent processing operations without the risk of damaging or fracturing the wafer.
  • the wafer may be subjected to ultrasonic cleaning (not shown) to remove particulate matter deposited on the wafer from the slicing operation.
  • the peripheral edge of the wafer is then profiled (e.g., rounded) by a conventional edge grinder (not shown) to reduce the risk of damage to the wafer during further processing.
  • the wafer is placed in a conventional lapping machine for stock removal of material from the front and back surfaces of the wafer using a lapping slurry containing abrasive particles.
  • the lapping operation is used to substantially reduce the thickness of the wafer, thereby removing damage caused by the wafer slicing operation, and to flatten and parallel its front and back surfaces.
  • a conventional grinding operation in which the front and back surfaces are ground using an abrading disc having abrasive particles embedded therein, may be performed in place of or in conjunction with the lapping operation.
  • the wafer is then etched by being fully immersed in a chemical etchant, such as a conventional caustic etch solution comprising 45% (by weight) KOH, thereby removing additional material from the front and back surfaces of the wafer.
  • a chemical etchant such as a conventional caustic etch solution comprising 45% (by weight) KOH
  • the wafers are immersed in the etchant for a period of about 3.5 minutes.
  • the wafer After immersion etching, the wafer is placed in a conventional double-side polishing machine (not shown) for concurrent polishing of the front and back surfaces of the wafer.
  • a conventional double-side polishing machine (not shown) for concurrent polishing of the front and back surfaces of the wafer.
  • One such conventional machine is manufactured by Peter Wolters under the model designation
  • Double-Side Polisher AC1400 The machine has a rotating turntable having a polishing surface defined by a polishing pad, and a carrier seated on the polishing pad that is rotatable relative to the rotating turntable and polishing pad.
  • the wafers are held in the carrier with a back surface of the wafer engaging the polishing pad.
  • a second polishing pad facing opposite the front surface of the wafer is mounted on a motor driven spindle that rotates the second polishing pad relative to the carrier and the turntable.
  • the spindle is capable of being moved up and down along a vertical axis for moving the second polishing pad into polishing engagement with the front surface of the wafer whereby the wafer is sandwiched between the two polishing pads.
  • a conventional polishing slurry containing abrasive particles and a chemical etchant is injected between the polishing pads and the wafer.
  • the polishing pads work the slurry against the surfaces of the wafer to concurrently and uniformly remove material from both sides of the wafer, leaving generally polished front and back surfaces.
  • the abrasive particles in the polishing slurry are sized in the range of about 70-90 nanometers for stock removal of material from the wafer.
  • the double-side polishing operation may remove between 5-20 microns of material from each of the front and back surfaces.
  • the concurrent and uniform removal of material from each side of the wafer uniformly removes damage caused by the immersion etching operation and thus substantially improves the flatness of the wafer.
  • the wafer now having polished front and back surfaces, is subjected to a single-side etching operation in which the back surface of the wafer, but not the front surface, is etched in order to roughen the back surface.
  • the wafer is mounted on a rotatable chuck, with the front surface facing down against the chuck and the back surface facing up and being exposed.
  • a conventional acid etch solution preferably comprising HF, Nitric and Sulfuric acid, is directed onto the exposed back surface of the wafer for removing wafer material from the back surface.
  • this single-side etching operation is preferably performed only long enough to roughen the back surface of the wafer so that it is easily distinguished from the front surface of the wafer.
  • the amount of material removed from the back surface by the single-side etching operation is preferably less than about one micron.
  • the amount of material removed from the back surface of the wafer during the single-side wafer etching operation may vary, depending on the requirements of the customer, without departing from the scope of this invention.
  • the wafer Upon completion of the single- side etching operation, the wafer has a polished front surface, a rough back surface, and improved flatness characteristics compared to conventional processing methods .
  • the wafer is placed in a conventional single-side polishing machine for final polishing of its front surface to remove scratches induced by wafer handling during the prior processing operations.
  • a particularly preferred single-side polishing machine is that manufactured by Speedfam and designated as model 50 SPAW.
  • the wafer is mounted on the bottom of a ceramic block in a conventional manner by applying a wax layer to the back surface of the wafer and adhering the wafer to the block, leaving the front surface of the wafer exposed and facing downward.
  • the block is placed on the turntable, with the front surface of the wafer contacting the polishing surface of the polishing pad.
  • a polisher head is mounted on the machine above the ceramic block and is capable of vertical movement along an axis extending down through the block. While the turntable rotates, the polisher head is moved downward against the ceramic block to urge the block toward the turntable, thereby pressing the front surface of the wafer into polishing engagement with the polishing surface of the polishing pad.
  • a conventional polishing slurry containing abrasive particles and a chemical etchant is injected between the polishing pad and the wafer. As an example, the size of the particles for final polishing of the wafer is in the range of about 25-35 nanometers.
  • the polishing pad works the slurry against the surface of the wafer to remove material from the front surface of the wafer, resulting in a highly reflective, damage-free front surface.
  • the single-side polishing operation be limited to removing only enough wafer to produce the desired degree of finish of the front surface.
  • the abrasive particles in the polishing slurry used for the single- side polishing operation are substantially smaller than those used for stock removal of material during the double-side polishing operation, and the amount of material removed from the wafer during the single-side polishing operation is preferably in the range of about 5 microns or less.
  • an intermediate polishing operation (not shown) may be conducted, in which the abrasive particles are sized in the range of 70-90 microns, prior to the final polishing operation without departing from the scope of this invention.
  • the flatness of the wafers was measured at various phases of the process. More particularly, after being sliced from the ingot, the wafers were subjected first to a conventional lapping operation and then to a conventional immersion etching operation. Thereafter, the wafers were placed in a double-side polishing machine manufactured by Peter Wolters, having model designation Double-Side Polisher AC1400, for concurrent polishing of the front and back surfaces of the wafer.
  • the size of the abrasive particles was in the range of 70-90 nanometers and the rotational speed of the polishing pads was between 19 and 25 rpm.
  • the wafers were double-side polished for about 80 minutes, with the average material removal being about 34 microns (17 microns from each of the front and back surfaces) .
  • the average TTV value of the wafers was measured to be about 0.98 microns (for comparison purposes, wafers processed according to conventional processing methods that use a lapping, immersion etching and single-side polishing sequence of operations typically have an average TTV value of about 3.00 microns) .
  • the average SFPD was measured to be about 0.27 and the average STIR was about 0.47.
  • the wafers were then subjected to the single-side etching operation to roughen the back surface of each of the wafers .
  • the average TTV value of the wafers after the single-side etching operation was measured to be about 1.34 microns. Thus, the flatness of the wafer was deteriorated by the single-side etching operation.
  • the average SFPD increased to about 0.33 and the average STIR increased to about 0.54.
  • the wafers were placed in a single-side polishing machine manufactured by Speedfam under the model designation 50 SPAW for intermediate and final polishing of the front surface of each of the wafers.
  • Approximately 5 microns of material was removed from the front surface during the single-side final polishing operation, in which the size of the abrasive particles was in the range of 25-35 nanometers and the rotational speed of the turntable was about 60 rpm.
  • the average TTV value of the wafers was finally measured to be about 1.00 micron, which is substantially the same as the TTV value as measured after the double-side polishing operation and substantially improved over the 3.00 average TTV value for wafers processed according to conventional processes.
  • double-side polishing, single-side etching and subsequent polishing yielded a flatter wafer while accomplishing the objective of having a polished front surface and rough back surface.
  • the average SFPD was measured to be about 0.36 and the average STIR was about 0.50, again only slightly deteriorated from the values measured after the double-side polishing.
  • the several objects of the invention are achieved and other advantageous results attained.
  • the flatness of the wafers is substantially improved in comparison to the flatness of wafers processed according to conventional processes involving only single-side polishing.
  • Subjecting the back surface of the wafer to a single-side etching operation sufficiently roughens the back surface according to the requirements of the customer.
  • the single-side etching is conducted for only a very short time, the improved flatness achieved by the double-side polishing operation is not substantially deteriorated by the single-side etching.
  • the need for single-side polishing as a final polishing operation after the single-side etching is minimized, resulting in little or no degradation of the flatness achieved by the double-side polishing operation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Weting (AREA)

Abstract

Cette invention se rapporte à un procédé de traitement d'une plaquette de semi-conducteur découpée dans un lingot monocristallin, ce procédé consistant à soumettre les surfaces avant et arrière de la plaquette à une opération de rodage ou à une opération de meulage. La plaquette est ensuite soumise à une opération d'attaque où elle est immergée dans un agent d'attaque chimique. Puis, la plaquette est soumise à une opération de polissage double face, pendant laquelle les surfaces avant et arrière de la plaquette sont polies. La plaquette est ensuite soumise à une opération d'attaque sur une seule face, pendant laquelle la surface arrière seulement, et non la surface avant, est exposée à un agent d'attaque chimique rendant rugueuse la surface arrière de la plaquette.
PCT/US1998/025429 1997-12-12 1998-12-01 Procede pour ameliorer la planeite de plaquettes de semi-conducteur polies WO1999031723A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US99010897A 1997-12-12 1997-12-12
US08/990,108 1997-12-12

Publications (1)

Publication Number Publication Date
WO1999031723A1 true WO1999031723A1 (fr) 1999-06-24

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001054178A1 (fr) * 2000-01-20 2001-07-26 Memc Electronic Materials, Inc. Procede de fabrication de plaquettes a semi-conducteurs
WO2001070454A1 (fr) * 2000-03-17 2001-09-27 Wafer Solutions, Inc. Systemes d'outils groupes et procedes associes destines au traitement de plaquettes
US6376335B1 (en) 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
US6632012B2 (en) 2001-03-30 2003-10-14 Wafer Solutions, Inc. Mixing manifold for multiple inlet chemistry fluids

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227339A (en) * 1990-05-18 1993-07-13 Fujitsu Limited Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device composed of the substrate
US5389579A (en) * 1993-04-05 1995-02-14 Motorola, Inc. Method for single sided polishing of a semiconductor wafer
US5551907A (en) * 1994-03-14 1996-09-03 Hughes Aircraft Company System for ultrasonic lap grinding and polishing
EP0782179A2 (fr) * 1995-12-27 1997-07-02 Shin-Etsu Handotai Co., Ltd Procédé pour la fabrication de wafers de semiconducteur à surfaces miroitantes
EP0791953A2 (fr) * 1996-01-31 1997-08-27 Shin-Etsu Handotai Company Limited Procédé de fabrication de rondelles semi-conductrices

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5227339A (en) * 1990-05-18 1993-07-13 Fujitsu Limited Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device composed of the substrate
US5389579A (en) * 1993-04-05 1995-02-14 Motorola, Inc. Method for single sided polishing of a semiconductor wafer
US5551907A (en) * 1994-03-14 1996-09-03 Hughes Aircraft Company System for ultrasonic lap grinding and polishing
EP0782179A2 (fr) * 1995-12-27 1997-07-02 Shin-Etsu Handotai Co., Ltd Procédé pour la fabrication de wafers de semiconducteur à surfaces miroitantes
EP0791953A2 (fr) * 1996-01-31 1997-08-27 Shin-Etsu Handotai Company Limited Procédé de fabrication de rondelles semi-conductrices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001054178A1 (fr) * 2000-01-20 2001-07-26 Memc Electronic Materials, Inc. Procede de fabrication de plaquettes a semi-conducteurs
US6376335B1 (en) 2000-02-17 2002-04-23 Memc Electronic Materials, Inc. Semiconductor wafer manufacturing process
WO2001070454A1 (fr) * 2000-03-17 2001-09-27 Wafer Solutions, Inc. Systemes d'outils groupes et procedes associes destines au traitement de plaquettes
US6632012B2 (en) 2001-03-30 2003-10-14 Wafer Solutions, Inc. Mixing manifold for multiple inlet chemistry fluids

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