+

WO1999030336A1 - Procede et appareil de fabrication de composants electriques multicouches - Google Patents

Procede et appareil de fabrication de composants electriques multicouches Download PDF

Info

Publication number
WO1999030336A1
WO1999030336A1 PCT/IE1998/000102 IE9800102W WO9930336A1 WO 1999030336 A1 WO1999030336 A1 WO 1999030336A1 IE 9800102 W IE9800102 W IE 9800102W WO 9930336 A1 WO9930336 A1 WO 9930336A1
Authority
WO
WIPO (PCT)
Prior art keywords
mask
layer
application
chamber
deposition
Prior art date
Application number
PCT/IE1998/000102
Other languages
English (en)
Inventor
Peter Anthony Fry Herbert
Original Assignee
Peter Anthony Fry Herbert
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peter Anthony Fry Herbert filed Critical Peter Anthony Fry Herbert
Priority to AU15031/99A priority Critical patent/AU1503199A/en
Publication of WO1999030336A1 publication Critical patent/WO1999030336A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H01G4/306—Stacked capacitors made by thin film techniques

Definitions

  • the present invention relates to a method and apparatus for the production of multilayer electrical, electronic or optical components hereinafter electrical components, usually formed in layers of alternate materials or combinations of materials on a substrate layer.
  • the method used comprises applying the layers of material in a vacuum by a deposition or coating process, usually with one layer substantially covering the previous layer and the next layer being formed with a substantially sheet-like apertured mask interposed between the previous layer and a material source for application of the next material followed by subsequent fabrication into the desired component.
  • MCC multilayer ceramic capacitor
  • the quantity of charge which can be stored on a capacitor is limited by the area of conductive plates, the dielectric constant of the material between the plates, the inter-plate spacing and the dielectric strength of the material used. While these limitations may be readily overcome where cost is not an issue and where sufficient space on a printed circuit board is available, however, where this is not the case current techniques are not appropriate.
  • the present invention is directed towards providing a process and apparatus using conventional vacuum based film deposition or coating techniques to manufacture multilayer electrical components such as capacitors.
  • a method in which the mask is alternatively moved from the mask present position to the mask remote position is provided.
  • This is a particularly suitable process for manufacturing a multilayer capacitor. It will be appreciated that polymer and ferro electric ceramic dielectrics can be easily applied by this process and will offer more compact designs than can be produced with more conventional dielectric material.
  • the mask is moved to assume different positions relative to the material source in the mask present position to define at least two different patterns of material layer with the mask present.
  • a simple back and forth movement using a mask having a plurality of longitudinally arranged slits will be sufficient to provide the two end portions to form the interleaving.
  • the mask is moved laterally and substantially parallel to the uppermost layer. This is particularly suitable for the making of multilayer ceramic capacitors.
  • the mask is pivoted relative to the upper layer.
  • various different shapes can be made. Indeed, by moving the mask, all sorts of shapes can be provided and thus, for example, where the alternate layers do not have the identical pattern, it would be possible to provide different patterns on different layers which might be required for certain components.
  • the additional step is performed of choosing a mask from at least two masks stored in the vacuum chamber. Obviously, if different masks can be chosen, even more versatility can be provided.
  • the mask is stored in a remote position in the vacuum chamber.
  • the method comprises the additional steps of:-
  • the application of at least one layer involves the application of at least two separate materials from separate material sources. Again, considerable versatility can be provided.
  • the invention provides apparatus for the manufacture of a multilayer electrical component by deposition or coating of the type comprising:-
  • a mask holder assembly having an apertured mask as part thereof:
  • means are provided for moving the mask holder assembly in the mask present position to vary the pattern of material applied to the workpiece.
  • the mask By allowing the mask not just simply to be placed in one position all the time, it is possible to vary the pattern.
  • the mask holder assembly carries at least two separate masks and includes means for selectively choosing the appropriate mask for application of material. Again, this adds further versatility.
  • the invention provides an apparatus in which a mask comprises at least two separate patterns of apertures to form layers of different pattern. Detailed Description of the Invention
  • Fig. 1 is a diagrammatic view of an apparatus for use in the invention
  • Fig. 2 is a plan view of a shadow mask used in the apparatus of Fig. 1 ;
  • Figs. 3(a) to (g) are diagrammatic views of a workpiece detailing the various stages of the manufacture of a multilayer capacitor in accordance with the invention
  • Fig. 4 is a flow diagram illustrating some steps in the fabrication of the multilayer capacitor in accordance with the invention.
  • Fig. 5 is a diagrammatic view of an alternative construction of apparatus according to the present invention.
  • Fig. 6 is a plan view of an alternative construction of mask according to the invention.
  • apparatus 1 which comprises a vacuum deposition chamber 2 having an evacuation pump 3 and a workpiece carrier 4 incorporating a platen 5.
  • a workpiece 6 is illustrated mounted on the platen 5.
  • a mask holder assembly 10 is mounted within the chamber 2 and mounts a mask support 11 which in turn carries an apertured planar mask 15.
  • the mask holder assembly 10 and mask support 11 are of essentially conventional construction and can be of any suitable mechanical construction and ideally include means for moving the mask support 11 in and about any axis.
  • a material applicator 20, in this embodiment, a plasma enhanced chemical vapour deposition device, is mounted in the vacuum deposition chamber 2 remote from the workpiece carrier 4. All of the components are of conventional construction and do not require any further description.
  • the mask 15 incorporates a plurality of longitudinal apertures 16 and again is of conventional construction.
  • Figs. 3 and 4 the method according to the present invention for the production of multilayer electrical components is described with reference to a process for manufacturing a multilayer capacitor. Not all of the production of the capacitor is described but simply the deposition of the conductor and dielectric layers so as to produce a composite sheet which then has to be cut up to produce individual units, often referred to as dices, which in turn have their electrode leaves interconnected by metalisation, connectors attached and then encapsulated in some way in plastics to produce a multilayer capacitor.
  • the workpiece 6 is loaded onto the platen 5 of the workpiece carrier 4 in step 100.
  • the chamber 2 is then evacuated in step 101 by the evacuation pump 3.
  • the mask holder assembly 10 is operated in step 102 to move the shadow mask to an un-masked mode, namely, to a mask remote position relative to the workpiece. This is illustrated in Fig. 3(a) where dielectric is deposited, deposition being illustrated by arrows in Fig. 3 and by step 103 in Fig. 4.
  • step 104 the deposition of the dielectric is terminated and the dielectric layer 25 is now fully formed.
  • the mask holder assembly 10 is then activated in step 105 to place the mask 15 in the correct position as shown in Fig. 3(b).
  • step 106 the material applicator 20 is activated to deposit a conductive layer indicated by the reference numeral 26 and in step 107 the deposition of the conductive layer is terminated and the conductive layer 26 is now ready to receive, if required, another layer of dielectric.
  • the various steps 102 to 107 are then repeated until sufficient layers of dielectric 25 and conductive material 26 are added so that if the steps are carried out, for example, ten times, they will produce two interleaved five leaf electrode structure. Finally, the last layer deposited must be a dielectric layer. It will be appreciated that this is achieved in the present apparatus by successfully toggling the mask 15 by the mask holder assembly 10 into a mask present and a mask remote mode of operation.
  • the use of the mask 15 has to be so arranged to ensure that there is adequate interconnection between the conductive layers forming one of the multi-leaf electrodes, but no interconnection between leaves belonging to different electrodes.
  • Fig. 3(e) shows the deposition of a further dielectric layer 25 while Fig. 3(f) shows the deposition of a still further conductive layer 26.
  • Fig. 3(g) illustrates the deposition of dielectric material 25.
  • FIG. 5 there is illustrated an alternative construction of apparatus indicated generally by the reference numeral 30 in which parts similar to those described with reference to the previous drawings are identified by the same reference numerals.
  • a mask storage area 31 housing two additional masks 6(a) and 6(b).
  • the mask holder assembly 10 chooses the particular mask required. It is envisaged that in certain situations, different constructions of masks may be required to provide the necessary pattern.
  • FIG. 6 there is illustrated an alternative construction of apertured planar mask indicated generally by the reference numeral 40, which planar mask is effectively divided into two separate sections having apertures 41 and 42 of different sizes.
  • planar mask is effectively divided into two separate sections having apertures 41 and 42 of different sizes.
  • two different patterns can be provided by the same mask. It will be appreciated, for example, with the mask as illustrated in Fig. 2, that tilting the mask relative to the workpiece would have the same effect on the pattern as providing narrower apertures.
  • the real advantage of the present invention is the application simply of vacuum based film deposition or coating techniques to the manufacture of such components.
  • In situ patterning during the coating or film deposition process by a spatially movable mechanical shadow mask placed over the substrate upon which the multilayer structure is being deposited enables the area geometry or coverage of each individual film or layer to be controlled in turn without having to break the vacuum or remove the workpiece to carry out an alternative patterning process on each layer prior to deposition of the next layer. It enables technically powerful thin film coating technology to be applied to the manufacture of multilayer capacitors involving the usage of advanced materials not currently possible.
  • capacitors While considerable emphasis has been placed on the manufacture of capacitors, it must be appreciated that the invention is not limited to capacitors as has been mentioned throughout the specification.
  • the reason why capacitors have been chosen for illustrative purposes is that they are one of the most commonly used devices and in particular the general trends of geometry and material selection are such as to make the manufacture of multilayer capacitors having a thin dielectric layer of high dielectric constant or strength particularly advantageous with the present invention.
  • the present invention allows the use of new high dielectric constant or strength materials in thin layers which allows the increase of capacitance without corresponding component increases in thickness.
  • the manufacturing process according to the present invention is a relatively simple process using of the order of six main steps which in turn reduces costs. Further, since thin film coating technology is already well developed, any process that utilises a well known technology is of its nature going to lead to high manufacturing yield.
  • the present invention obviates the need to use weak ceramic solvents and organic binders and the need for high temperature firing. Further, the elimination of high temperature sintering reduces the cost of materials. Further, in accordance with the present invention, a much wider range of materials can be used allowing for increases in the efficiency of many devices. As has been mentioned above, this increase in efficiency and performance is particularly applicable to capacitors.
  • the present invention allows the manufacture of devices for many new applications including ignition systems, lasers, X-ray generation, power supplies, and indeed many other pieces of equipment.
  • vacuum deposition chambers may be used such as are commercially available, for example, from Balzers of Liechtenstein, Temescal of USA and Leybold Heraeus of Germany.
  • deoosition sources may be used and indeed multiple deposition sources may be used which could include, for example, electron-beam thermal evaporation, Knudsen cell, resistance heater thermal evaporation, sputtering, Chemical Vapour Deposition, Plasma enhanced Chemical Vapour Deposition and Ion Gun techniques such as Ion Beam Sputtering and Ion Assisted Deposition.
  • Multiple deposition sources in the vacuum chamber may also be used. For example, in the fabrication of a capacitor one source may be used for the dielectric and another source for the conductor.
  • the shadow masks are of a regular solid planar material but indeed any suitable shadow mask could be used. While in the embodiment described above, there has been no particular description of the mask holder assembly, it will be appreciated that the mask holder assembly would be controlled by conventional control methods such as computer control devices and by any form of coupling linking. Many different forms of mechanical actuators such as push-pull rods, rotating pivots and/or x-y-z- ⁇ stepper motors could be used. Again, many forms of locating devices can be used in the vacuum chamber to ensure that the mask is correctly located relative to the workpiece.
  • the shadow mask may be designed in any particular way to provide the necessary deposition pattern. It will also be appreciated that the shadow mask can be moved so that coating is prevented or interrupted over any chosen sequence of selected areas of a workpiece. This enables the patterning of the coating film or films being deposited by material from the material source onto the workpiece in situ within the chamber during the process.
  • the workpiece can thus be selectively coated with suitable material within the chamber to a desired pattern in real time in- situ within the chamber during the coating process.
  • a further important feature is the way in which the mask may be moved both between masked and un-masked modes of operation and between a variety of different masking positions to achieve the desired pattern and that if desired different materials from the material applicator or material source may be used to coat or etch the workpiece in accordance with the position of the mask. It will be appreciated that in addition to the deposition or coating described that selective use of an etch material or etching techniques such as sputter etching may also be used to achieve the required pattemation.
  • the present invention allows for the use of materials heretofore deemed not suitable for the manufacture of such devices. In addition to reducing costs, it allows for the use of materials whose performance characteristics enhance the operation of the final device. For example, given the limiting factors on capacitor performance imposed by the dielectric constant or strength of the material used the invention allows for the use of materials with very high dielectric constant or strength allowing an increase in device capacitance and hence in energy storage capacity. Furthermore there is a reduction in device size and an improvement in performance.
  • the invention allows for significantly increased manufacturing parameter space which allows the device parameters relating to dielectric constant, inter-plate spacing and dielectric strength to be varied over far wider ranges than currently. This allows enhanced device customisation for applications, including ignition systems, lasers, x-ray generation, scientific research, power suppliers, electric vehicles, solar-powered equipment and medical applications e.g. cardiac defibrillation.
  • the use of new, high dielectric strength material allows high capacitance to be obtained by reduction of inter plate spacing while maintaining acceptable breakdown voltage, Vm.
  • Fast capacitor discharge is also possible because of the small inter-plate spacing and use of the high purity dielectric materials now possible with the invention will give low leakage currents.
  • Improvement in manufacturing tolerances is obtained by using for process control thin film deposition parameters such as physical or optical thicknesses which can be accurately monitored during deposition by a variety of techniques, such as quartz crystal monitoring, to very high accuracy.
  • process control thin film deposition parameters such as physical or optical thicknesses which can be accurately monitored during deposition by a variety of techniques, such as quartz crystal monitoring, to very high accuracy.
  • ultrahigh purity, high quality dielectric films which are free from pinholes and other intrinsic defects is standard in the thin film coating industries such as microelectronics and optical coating.
  • the process is, thus, inherently high yield and obviates the requirement for complete component testing as is currently standard. For many requirements such as PCB manufacture and memory backups a high capacitance per unit volume is required.
  • the process is thus particularly suited to this type of application and as the devices produced in accordance with the invention are solid-state devices with excellent thermal and mechanical properties they are thus good for harsh environments.
  • the lifetimes in terms of charge-discharge cycles of capacitors produced in accordance with the invention is orders of magnitude longer than those of current multilayer capacitors.
  • the shadow mask is replicated as desired in the x-y plane (e.g. laterally across a planar workpiece) to cover the entire area of the workpiece with suitable spacing between masking elements according to designed capacitor schematic.
  • the workpiece is then cut to leave suitably exposed conductive elements for each of the capacitors produced which are then metal interconnected, bonded and finished using conventional techniques.
  • one embodiment of invention comprises an electron-beam evaporation with two materials Titanium Dioxide (TiCy and Aluminium.
  • the chamber 2 can be filled with a partial pressure of Oxygen during the dielectric evaporation to maintain the stoichiometry of the TiQ, during evaporation.
  • Deposition is carried out by alternate evaporation of the materials using the electron beam and the thickness of the evaporation is monitored using a quartz crystal monitor.
  • Five hundred layers of 1 micrometre thick TiO 2 are deposited with interleaved Aluminium layers of 0.5 micrometre thick in the process of the invention. These layers are deposited on a suitable substrate, such as for example Silicon, with a substrate thickness of 350 micrometres.
  • the substrate can be patterned, by means of the shadow mask, to produce capacitors of the required dimension. This would allow a maximum operational rating of 10 Volts. In this way, from a 1rr area of substrate, 10,000 capacitors of 76 ⁇ F can be produced with dimensions of 1 cm x 1 cm x 1.1 mm. Alternatively, 1 ,000,000 capacitors of dimension 1 mm x 1 mm x 1 J mm can be fabricated with a capacitance 0.76 ⁇ F.
  • capacitors can be stacked to give a capacitance of 690 ⁇ F per err? which is competitive in volume terms with electrolytic capacitors and at a lower cost.
  • the voltage rating of the capacitors can be improved by producing thicker dielectric layers albeit with a corresponding decrease in the capacitance values. For example one hundred layers of 5 ⁇ m thick TiQ, will give a maximum voltage rating of 50 Volts with a capacitance of 3.04 ⁇ F per enrf of fully coated substrate or 33 ⁇ F per enrf for stacked devices.
  • high dielectric constant, high dielectric strength dielectrics can be used such as Barium or Strontium Titanate. Deposition of these materials can be carried out by stoichiometric co-evaporation of Barium/Strontium and TiOa followed by a post-sintering of the stack to form crystalline dielectric material.
  • the interleaved metal would need to be a high melting point metal such as Palladium or Platinum.
  • Specially formulated ceramics such as Z5U, plasma polymerised hexamethyldisilazane (pp HMDSN) and hexamethyldisiloxane may also be used.
  • pp HMDSN plasma polymerised hexamethyldisilazane
  • pp HMDSN plasma polymerised hexamethyldisilazane
  • hexamethyldisiloxane may also be used.
  • 500 layers of 1 micrometre thick ppHMDSN deposited with interleaved Aluminium layers of 0.5 micrometre thick on a 350 micrometre thick Silicon substrate will give a capacitance per en of 2.04 microFarads with a breakdown voltage Vm of approximately 60kV.
  • These capacitors have an energy storage capacity of 25 MJ/rrf and can be stacked to give an capacitance of 18.5 microFarad per enf .
  • the process of the invention may be varied by altering the shadow mask design, layout and patterning. It will further be appreciated that a sequence of different film depositions, including but not limited to codeposition and deposition of multiple (more than two) materials may be used.
  • the relative timing of shadow mask positioning versus individual film deposition to produce film composition varying spatially in all geometrical co-ordinate directions, e.g. (x, y, z) or f ⁇ , z), etc. producing for example, laterally (x-y plane) or vertically (z direction) graded structures may also be varied.
  • the moveable, in-situ-coating shadow mask patterning process enables capacitor mass manufacturing to access the technical and commercial advantages of the powerful thin film coating technology sector.
  • the process of the invention is significantly simplified to reduce cost. Due to the well-developed, mature and robust nature of thin film coating technology, manufacturing yield is high reducing costs and testing requirements.
  • the use of weak ceramic tape, solvents and organic binders and the need for high temperature firing is eliminated. Furthermore the elimination of high temperature sintering allows the use of low cost metals and the use of a thin film process (layers down to nanometre thickness are possible) allows the design of high capacitance, high energy storage capacity devices by reduction of dielectric thickness parameter, an improvement in performance and a reduction in size and cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

La présente invention concerne un procédé et un appareil (1) utilisés pour la fabrication de composants électriques multicouches tels que des condensateurs céramiques multicouches. Les couches sont réalisées successivement dans une boîte à vide (2) selon un procédé de dépôt de revêtement ou couchage tel que la technique, couramment utilisée, du couchage de films minces à l'aide d'un pochoir mobile (15) à commande mécanique. Il est ainsi possible de changer le motif selon les couches sans casser le vide.
PCT/IE1998/000102 1997-12-08 1998-12-08 Procede et appareil de fabrication de composants electriques multicouches WO1999030336A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU15031/99A AU1503199A (en) 1997-12-08 1998-12-08 A method and apparatus for the production of multilayer electrical components

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IES970862 1997-12-08
IE970862 1997-12-08

Publications (1)

Publication Number Publication Date
WO1999030336A1 true WO1999030336A1 (fr) 1999-06-17

Family

ID=11041649

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IE1998/000102 WO1999030336A1 (fr) 1997-12-08 1998-12-08 Procede et appareil de fabrication de composants electriques multicouches

Country Status (2)

Country Link
AU (1) AU1503199A (fr)
WO (1) WO1999030336A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004073971A1 (fr) * 2003-02-20 2004-09-02 N.V. Bekaert S.A. Procede de fabrication de structures laminees
US6821348B2 (en) 2002-02-14 2004-11-23 3M Innovative Properties Company In-line deposition processes for circuit fabrication
US6897164B2 (en) 2002-02-14 2005-05-24 3M Innovative Properties Company Aperture masks for circuit fabrication
WO2006137689A1 (fr) 2005-06-21 2006-12-28 Sehyang Industrial Co., Ltd. Condensateur à puce multicouche, et ses procédé et dispositif de fabrication
KR20200124301A (ko) * 2018-03-20 2020-11-02 케이엘에이 코포레이션 심자외선(duv) 광학 이미징 시스템에 대한 임의 파면 보상기
US12094721B2 (en) 2018-01-05 2024-09-17 University Of Maryland, College Park Multi-layer solid-state devices and methods for forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2903292A1 (de) * 1979-01-29 1980-08-07 Siemens Ag Vorrichtung zur beschichtung von substraten mit abwechselnd uebereinanderliegenden metall- und kunststoffschichten
EP0147696A2 (fr) * 1983-12-19 1985-07-10 SPECTRUM CONTROL, INC. (a Pennsylvania corporation) Condensateur monolithique multicouche miniaturisé et appareil et méthode pour sa fabrication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2903292A1 (de) * 1979-01-29 1980-08-07 Siemens Ag Vorrichtung zur beschichtung von substraten mit abwechselnd uebereinanderliegenden metall- und kunststoffschichten
EP0147696A2 (fr) * 1983-12-19 1985-07-10 SPECTRUM CONTROL, INC. (a Pennsylvania corporation) Condensateur monolithique multicouche miniaturisé et appareil et méthode pour sa fabrication

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821348B2 (en) 2002-02-14 2004-11-23 3M Innovative Properties Company In-line deposition processes for circuit fabrication
US6897164B2 (en) 2002-02-14 2005-05-24 3M Innovative Properties Company Aperture masks for circuit fabrication
US7241688B2 (en) 2002-02-14 2007-07-10 3M Innovative Properties Company Aperture masks for circuit fabrication
US7297361B2 (en) 2002-02-14 2007-11-20 3M Innovative Properties Company In-line deposition processes for circuit fabrication
WO2004073971A1 (fr) * 2003-02-20 2004-09-02 N.V. Bekaert S.A. Procede de fabrication de structures laminees
WO2004075219A1 (fr) * 2003-02-20 2004-09-02 N.V. Bekaert S.A. Condensateur enroule
WO2006137689A1 (fr) 2005-06-21 2006-12-28 Sehyang Industrial Co., Ltd. Condensateur à puce multicouche, et ses procédé et dispositif de fabrication
EP1913608A4 (fr) * 2005-06-21 2012-09-05 Sehyang Ind Co Ltd Condensateur à puce multicouche, et ses procédé et dispositif de fabrication
US12094721B2 (en) 2018-01-05 2024-09-17 University Of Maryland, College Park Multi-layer solid-state devices and methods for forming the same
KR20200124301A (ko) * 2018-03-20 2020-11-02 케이엘에이 코포레이션 심자외선(duv) 광학 이미징 시스템에 대한 임의 파면 보상기
KR102802747B1 (ko) * 2018-03-20 2025-04-30 케이엘에이 코포레이션 심자외선(duv) 광학 이미징 시스템에 대한 임의 파면 보상기

Also Published As

Publication number Publication date
AU1503199A (en) 1999-06-28

Similar Documents

Publication Publication Date Title
US5486277A (en) High performance capacitors using nano-structure multilayer materials fabrication
EP0617440B1 (fr) Condensateur feuilleté à couches minces et procédé pour sa fabrication
KR20000015822A (ko) 박막 다층 콘덴서_
KR100817174B1 (ko) 다층박막 캐패시터와 그 제조방법 및 장치
US20130010400A1 (en) Sintering of high temperature conductive and resistive pastes onto temperature sensitive and atmospheric sensitive materials
EP0035536B1 (fr) Methode de fabrication de condensateurs ajustables á couches épaisses
US3426257A (en) Multiple capacitor and method of making the same
WO1999030336A1 (fr) Procede et appareil de fabrication de composants electriques multicouches
JPH09205038A (ja) 多層セラミック電子構成素子の製造方法
KR20090099275A (ko) 적층형 전자부품용 그린시트 및 이를 이용한 그린칩의제조방법
IE981022A1 (en) A method and apparatus for the production of multilayer electrical components
IES981023A2 (en) A method and apparatus for the production of multilayer electrical components
KR101004694B1 (ko) 진공증착방식 적층형 전자부품과 그 제조장치 및 방법
JP2013127992A (ja) コンデンサ内蔵基板の製造方法、及び該製造方法に使用可能な素子シートの製造方法
US7180155B2 (en) Method for manufacturing thin-film multilayer electronic component and thin-film multilayer electronic component
KR20050077687A (ko) 다층 박막 캐패시터 제조방법 및 그 제조장치
JPH02224311A (ja) 積層型セラミックス電子部品の製造方法
KR20190075385A (ko) 적층 세라믹 콘덴서 표면 처리 장치 및 방법
JP2003309037A (ja) 積層型電子部品およびその製法
KR0130868B1 (ko) 다층 칩 캐패시터(Multilayer Chip Capacitor)의 외부 전극 제조방법
EP1738431A2 (fr) Condensateurs integres utilisant des trous d'interconnexion remplis conducteurs
JPH10121233A (ja) 誘電体薄膜の作製方法
KR101010166B1 (ko) 외부전극 형성장치
JPH1126279A (ja) 積層セラミック電子部品の製造方法
JPH0878274A (ja) セラミック電子部品の製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DE DK DK EE ES FI GB GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG US UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载