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WO1999019795A8 - Procede et appareil d'optimisation de l'execution d'instructions - Google Patents

Procede et appareil d'optimisation de l'execution d'instructions

Info

Publication number
WO1999019795A8
WO1999019795A8 PCT/US1998/021465 US9821465W WO9919795A8 WO 1999019795 A8 WO1999019795 A8 WO 1999019795A8 US 9821465 W US9821465 W US 9821465W WO 9919795 A8 WO9919795 A8 WO 9919795A8
Authority
WO
WIPO (PCT)
Prior art keywords
instructions
load
store instructions
executed
execution
Prior art date
Application number
PCT/US1998/021465
Other languages
English (en)
Other versions
WO1999019795A1 (fr
Inventor
Dale C Morris
Jack D Mills
William Y Chen
Original Assignee
Inst The Dev Of Emerging Archi
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inst The Dev Of Emerging Archi filed Critical Inst The Dev Of Emerging Archi
Priority to EP98953390A priority Critical patent/EP1031076A1/fr
Priority to JP2000516280A priority patent/JP2001520415A/ja
Priority to AU10780/99A priority patent/AU1078099A/en
Publication of WO1999019795A1 publication Critical patent/WO1999019795A1/fr
Publication of WO1999019795A8 publication Critical patent/WO1999019795A8/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/3834—Maintaining memory consistency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

On diffère des problèmes rencontrés lors de l'exécution spéculative d'instructions. Si les résultats des instructions qui ont été exécutées spéculativement sont utilisés ultérieurement, on vérifie l'intégrité de l'exécution des instructions. Si elle ne l'est pas, un code de récupération est exécuté, ce code modifiant l'état du système informatique (50) pour donner l'apparence que les instructions exécutées spéculativement ont été exécutées avec succès.
PCT/US1998/021465 1997-10-13 1998-10-09 Procede et appareil d'optimisation de l'execution d'instructions WO1999019795A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP98953390A EP1031076A1 (fr) 1997-10-13 1998-10-09 Procede et appareil d'optimisation de l'execution d'instructions
JP2000516280A JP2001520415A (ja) 1997-10-13 1998-10-09 命令実行を最適化する方法および装置
AU10780/99A AU1078099A (en) 1997-10-13 1998-10-09 Method and apparatus for optimizing instruction execution

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US95383697A 1997-10-13 1997-10-13
US16804098A 1998-10-07 1998-10-07
US09/168,040 1998-10-07
US08/953,836 1998-10-07

Publications (2)

Publication Number Publication Date
WO1999019795A1 WO1999019795A1 (fr) 1999-04-22
WO1999019795A8 true WO1999019795A8 (fr) 2000-09-28

Family

ID=26863747

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/021465 WO1999019795A1 (fr) 1997-10-13 1998-10-09 Procede et appareil d'optimisation de l'execution d'instructions

Country Status (4)

Country Link
EP (1) EP1031076A1 (fr)
JP (1) JP2001520415A (fr)
AU (1) AU1078099A (fr)
WO (1) WO1999019795A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6889315B2 (en) * 1999-12-17 2005-05-03 Fujitsu Limited Processor and method of controlling the same
US6598156B1 (en) * 1999-12-23 2003-07-22 Intel Corporation Mechanism for handling failing load check instructions
US7680999B1 (en) 2000-02-08 2010-03-16 Hewlett-Packard Development Company, L.P. Privilege promotion based on check of previous privilege level
US6704862B1 (en) * 2000-03-06 2004-03-09 Sun Microsystems, Inc. Method and apparatus for facilitating exception handling using a conditional trap instruction
US6631460B1 (en) * 2000-04-27 2003-10-07 Institute For The Development Of Emerging Architectures, L.L.C. Advanced load address table entry invalidation based on register address wraparound
JP3790683B2 (ja) 2001-07-05 2006-06-28 インターナショナル・ビジネス・マシーンズ・コーポレーション コンピュータ装置、その例外処理プログラム及びコンパイル方法
JP2008293378A (ja) 2007-05-25 2008-12-04 Panasonic Corp プログラム書き換え装置
US11983535B2 (en) 2019-03-22 2024-05-14 Cambricon Technologies Corporation Limited Artificial intelligence computing device and related product
CN111723921B (zh) * 2019-03-22 2024-05-14 中科寒武纪科技股份有限公司 人工智能计算装置及相关产品
US11113065B2 (en) * 2019-04-03 2021-09-07 Advanced Micro Devices, Inc. Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5778219A (en) * 1990-12-14 1998-07-07 Hewlett-Packard Company Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
US5692169A (en) * 1990-12-14 1997-11-25 Hewlett Packard Company Method and system for deferring exceptions generated during speculative execution
JP2786574B2 (ja) * 1992-05-06 1998-08-13 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システムにおける順不同ロード動作の性能を改善する方法と装置
US5799179A (en) * 1995-01-24 1998-08-25 International Business Machines Corporation Handling of exceptions in speculative instructions
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor
US5903749A (en) * 1996-07-02 1999-05-11 Institute For The Development Of Emerging Architecture, L.L.C. Method and apparatus for implementing check instructions that allow for the reuse of memory conflict information if no memory conflict occurs

Also Published As

Publication number Publication date
WO1999019795A1 (fr) 1999-04-22
AU1078099A (en) 1999-05-03
EP1031076A1 (fr) 2000-08-30
JP2001520415A (ja) 2001-10-30

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