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WO1999013582A1 - Boucle a phase asservie numerique peu sensible aux perturbations employant un detecteur de phase-frequence - Google Patents

Boucle a phase asservie numerique peu sensible aux perturbations employant un detecteur de phase-frequence Download PDF

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Publication number
WO1999013582A1
WO1999013582A1 PCT/US1998/018511 US9818511W WO9913582A1 WO 1999013582 A1 WO1999013582 A1 WO 1999013582A1 US 9818511 W US9818511 W US 9818511W WO 9913582 A1 WO9913582 A1 WO 9913582A1
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WO
WIPO (PCT)
Prior art keywords
phase
clock pulses
output
frequency
locked loop
Prior art date
Application number
PCT/US1998/018511
Other languages
English (en)
Inventor
Martin Fornage
Paul A. Henderson
Original Assignee
Advanced Fibre Communications, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Fibre Communications, Inc. filed Critical Advanced Fibre Communications, Inc.
Publication of WO1999013582A1 publication Critical patent/WO1999013582A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Definitions

  • the invention relates to phase-locked loops and in particular to a digital phase- locked loop (PLL or DPLL) of the type employing a phase-frequency detector (PFD).
  • PLL digital phase- locked loop
  • PFD phase-frequency detector
  • Digital phase-locked loops employing phase-frequency detectors are well known in the prior art. See, for example, Digital PLL Frequency Synthesizers: Theory and Design by Ulrich L. Rohde, p.220 and Phase-Locked Loops: Theory, Design and Applications, 2d ed., by Roland E. Best, McGraw-Hill, Inc., San Francisco, 1993, particularly at pp. 93-179.
  • a typical prior art DPLL shown in Figure 1 , comprises a phase-frequency detector 10, a loop filter 12, a voltage-controlled oscillator (VCO) 14, and a divide-by-N counter 16 located in a feedback loop.
  • the loop filter 12 and VCO 14 may be implemented using analog or digital techniques.
  • the PFD 10 and counter 16 are implemented using digital techniques.
  • the input to the DPLL is the reference clock input (REFCLK) applied to PFD 10.
  • the PFD 10 also receives, via the feedback loop, a VCO derived system clock,
  • PFD 10 includes a first portion containing D-type flip-flops in block 10a and a subtract operator 10b. The details of block 10a are shown in Figure 2.
  • the output of PFD 10 a phase error signal (PHERR) is applied to the loop filter 12 which in turn provides its filtered output to the VCO 14.
  • PHERR phase error signal
  • the DPLL output, the output clock (Output CLK) is taken from the output of VCO 14.
  • the objective of the DPLL is to lock the frequency of the VCO to a multiple "N" of the reference frequency input.
  • the phase error signal PHERR indicates a frequency error and the VCO operates at its lowest frequency.
  • the PFD 10 compares the phase and frequency of the input (REFCLK) with that of the divided down VCO signal VCO/N and generates an error signal, related to the frequency and phase difference between the two signals.
  • the error signal PHERR is filtered in loop filter 12 and applied to the VCO to force it to vary in a direction which reduces the frequency difference between the divided-down VCO system clock VCO/N and the input clock REFCLK. Once the frequencies are sufficiently close, the feedback nature of the loop causes the VCO to synchronize or lock with the incoming signal. Once in lock, the VCO frequency is identical with that of the input signal, but with a finite phase difference.
  • a first D-type flip-flop 18 is controlled by the REFCLK input.
  • a second D-type flip-flop 20 is controlled by the VCO/N input.
  • a logic high is applied to the D inputs of devices 18 and 20.
  • the Q output of flip-flop 18 provides the UP output to the subtract operator 10b ( Figure 1), while the Q output of flip-flop 20 provides the DOWN output to the subtract operator 10b.
  • the Q outputs of the devices are also applied to the respective inputs of a NAND gate 22, the output of which is applied to the reset inputs of both devices. Thus, the 0, 0 outputs are inhibited (when the UP and DOWN are both 0, the NAND gate resets the devices). Since there are three other possible states of the UP/DOWN output lines (1,0; 0,1 and 1,1), the PFD output PHERR from the subtract operator has three levels (as shown in the waveforms of Figures 4-6 and 11-13, described below).
  • PFD 10 operates on the positive edges of input clock signals (it could, alternatively, operate on negative edges) such that a positive transition of REFCLK causes the PFD to go to its next higher state, unless it is already in its highest state.
  • a positive transition of VCO/N causes the PFD to go to its next lower state, unless it is already in its lowest state.
  • PHERR shows a small phase error which is necessary in practical DPLLs.
  • the phase of VCO/N is not required to be identical or even close to the phase of REFCLK as long as their difference stays constant (frequency lock).
  • it is usually sufficient to have a frequency detector instead of a phase and frequency detector.
  • the simplicity and low output ripple generated by a phase-frequency detector make it an attractive solution compared to other detectors.
  • the PFD is edge triggered and therefore very sensitive to noise. A false edge or a missing input reference edge will force the PFD to falsely adjust the VCO frequency until the PFD sees an identical number of edges on both inputs. It may take a very long time to recover from such events.
  • VCO Voltage Controlled Crystal Oscillator
  • Figures 4, 5 and 6 show in idealized fashion how a typical prior art PFD re- sponds to events such as a one-time phase jump ( Figure 4), an extra reference pulse
  • a digital phase-locked loop which is less susceptible to perturbations.
  • the loop has a phase-frequency detector receiving a reference clock and the output of a voltage controlled oscillator, a loop filter receiving the output of the phase-frequency detector, a voltage-controlled oscillator receiving the output of the loop filter for providing the phase-locked loop output, a divide-by-N counter also receiving the output of the voltage-controlled oscillator for providing an input to the phase-frequency detector, and a monitoring counter for determining whether there are N plus or minus "a" voltage-controlled oscillator clock pulses between each successive reference clock pulse, where "a" is slightly larger than the number of clock pulses which when added or subtracted from the number of clock pulses corresponding to the nominal frequency of the phase- locked loop would cause the maximum desired frequency deviation of the phase- locked loop output from the nominal frequency, the monitoring counter reloading the divide-by-N counter and resetting the phase-frequency detector when there are fewer than N-a clock
  • the invention also provides a method for phase and frequency locking signals in a digital phase-locked loop by coupling a reference clock and an output of a voltage controlled oscillator to a phase-frequency detector, coupling the output of the phase- frequency detector to a loop filter, coupling the output of the loop filter to a voltage- controlled oscillator and deriving the output of the phase-locked loop from the voltage-controlled oscillator, comparing reference clock pulses to voltage-controlled oscillator clock pulses for determining whether there are N plus or minus "a" voltage-controlled oscillator clock pulses between each successive reference clock pulse (leading or lagging edge), where "a” is slightly larger than the number of clock pulses which when added or subtracted from the number of clock pulses corresponding to the nominal frequency of the phase-locked loop would cause the maximum desired frequency deviation of the phase-locked loop output from the nominal frequency, reloading the divide-by-N counter and resetting the phase-frequency detector when there are fewer than N-a clock pulses between consecutive reference clock pulses and resetting
  • Figure 1 is a functional block diagram of a typical prior art digital phase-locked loop employing a phase-frequency detector.
  • Figure 2 is a schematic diagram of a portion of a typical prior art phase-frequency detector.
  • Figure 3 is an idealized set of waveforms showing a locked condition of a typical prior art digital phase-locked loop.
  • Figure 4 is an idealized set of waveforms showing the response of a typical prior art digital phase-locked loop in response to a phase jump in its input.
  • Figure 5 is an idealized set of waveforms showing the response of a typical prior art digital phase-locked loop in response to an extra pulse in its input.
  • Figure 6 is an idealized set of waveforms showing the response of a typical prior art digital phase-locked loop in response to a missing pulse in its input.
  • Figure 7 is a functional block diagram of preferred embodiment a digital phase- locked loop employing a phase-frequency detector in accordance with the present invention.
  • Figure 8 is a schematic diagram of a portion of the phase-frequency detector employed in the preferred embodiment of the present invention.
  • Figure 9 is a partly schematic, functional block diagram of a monitoring counter employed in the preferred embodiment of the present invention.
  • Figure 10 is a flow chart useful in understanding the monitoring counter employed in the preferred embodiment of the present invention.
  • Figure 11 is an idealized set of waveforms showing the response of the digital phase-locked loop of the present invention in response to a phase jump in its input.
  • Figure 12 is an idealized set of waveforms showing the response of the digital phase-locked loop of the present invention in response to an extra pulse in its input.
  • Figure 13 is an idealized set of waveforms showing the response of the digital phase-locked loop of the present invention in response to a missing pulse in its input.
  • FIG. 7 shows a preferred embodiment of the digital phase-locked loop according to the present invention. Elements common to the prior art DPLL of Figure 1 are shown using the same reference numerals. Elements modified from those of the Figure 1 prior art DPLL are shown with prime (') marks added to their reference numerals.
  • This preferred embodiment employs a modified PFD 10' having a modified flip-flop containing block 10a', a modified divide-by-N counter 16', and a new element, a monitoring counter 24.
  • the modified portion 10a' of the PFD 10' is shown in Figure 8.
  • An external reset input has been added.
  • the prior art NAND gate is replaced by an AND gate 22'.
  • a new NOR gate 26 receives the AND gate output and a Reset PFD input from the monitoring counter 24, as is described further below.
  • the Q,Q outputs of the flip-flops continue to be inhibited in view of the logical operation of the AND and NOR gates, but the arrangement allows the flip-flops 18 and 20 to be reset either by the Q,Q outputs or by a Reset PFD signal (a logical 0 in this case) from the monitoring counter.
  • the divide-by-N counter 16' is modified such that it is reloadable, upon receipt of a "reload” signal, to a count commensurate with the count corresponding to that when the VCO is at its nominal or free-running frequency.
  • N is the nominal count identical to the feedback divider ratio
  • a is the allowable deviation
  • a is dimensioned slightly larger than maximum frequency deviation.
  • FIG. 9 is a partly schematic functional block diagram.
  • the monitoring counter receives the REFCLK input at the main input of an edge detector 28.
  • the VCO output clock CLK is applied to the clocking input of edge detector 28 and the clocking input of a counter 30.
  • the edge detector output is applied to the reset input of counter 30 and to the clocking inputs of logic and counting functions 32 and 34, respectively.
  • Logic and counting function 32 determines if the REFCLK pulse is shorter than the time period of N-a pulses.
  • Logic and counting function 32 determines if the REFCLK pulse is longer than the time period of N+a pulses.
  • counter 30 need provide only a single output, a count "n” of the number of VCO output clock pulses CLK and that this count may be applied to a single logic and counting circuit providing two outputs in response to the functions of blocks 32 and 34.
  • the logic and counting circuit(s) may be implemented in various ways as will be readily apparent to those of ordinary skill in the art.
  • a "yes" output from block 32 causes reloading of the divide-by-N counter (the counter is “reloaded” to the count "a” corresponding to the VCO's free- running frequency) and, via OR gate 36, resetting of the PFD 10'.
  • a "yes" output from block 34 causes reloading of the counter 30 (the counter is “reloaded” to a count of N) and, via OR gate 36, resetting of the PFD 10'.
  • the monitoring counter counts a value "n" where N-a ⁇ n ⁇ N+a, the system is considered in phase and no further action is taken. If n ⁇ N-a, a spurious edge has been detected, or there was a switching between two input reference signals.
  • the feedback divider is then reloaded and the PFD is reset. That operation resynchronizes the VCO derived clock to the reference clock.
  • the PFD now measures a negligible phase error and therefore, it does not have to pull the frequency of the VCO very far to get the phase error exactly back to zero.
  • n> N+a the input signal is considered lost.
  • the PFD is then reset, and the monitoring counter is loaded to "a". This allows further PFD resets to happen every "N" clock pulses. At that point, a longer absence of pulses is not catastrophic because the system is now free running. PFD resets are recreated every N VCO pulses as if the loop would still be locked on a valid reference clock signal. This can be used as a short term holdover until the reference clock signal returns.
  • FIG. 10 The operation of the monitoring counter of Figure 9 is shown in the flow chart of Figure 10.
  • FIGs 11-13 show the idealized response of the DPLL of Figure 7 in response to perturbations such as a one-time phase jump (Figure 10), an extra reference pulse (Figure 11), and a missing pulse ( Figure 12).
  • Figure 10 a one-time phase jump
  • Figure 11 an extra reference pulse
  • Figure 12 a missing pulse
  • the present invention may be implemented using analog, digital, hybrid analog/digital and/or digital signal processing in which functions are performed in software and/or firmware.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne une boucle à phase asservie numérique moins sensible aux perturbations, qui comprend un détecteur de phase-fréquence recevant une horloge de référence et la sortie d'un oscillateur commandé en tension, un filtre à boucle recevant la sortie du détecteur de phase-fréquence, un oscillateur commandé en tension recevant la sortie du filtre à boucle pour fournir la sortie de la boucle à phase asservie, un compteur division par n recevant également la sortie de l'oscillateur commandé en tension pour fournir une entrée au détecteur de phase-fréquence, et un compteur de contrôle pour déterminer s'il y a n plus 'a' ou n moins 'a' impulsions d'horloge de l'oscillateur commandé en tension entre une impulsion d'horloge de référence et la suivante, 'a' étant légèrement plus grand que le nombre d'impulsions d'horloge qui, s'il était ajouté au ou soustrait du nombre d'impulsions d'horloge correspondant à la fréquence nominale de la boucle à phase asservie, provoquerait l'écart de fréquence maximum désiré de la sortie de la boucle à phase asservie. Le compteur de contrôle recharge le compteur division par n et réinitialise le détecteur de phase-fréquence quand le nombre d'impulsions d'horloge entre des impulsions d'horloge de référence consécutives est inférieur à n-a, et réinitialise le détecteur de phase-fréquence quand le nombre d'impulsions d'horloge de référence entre des impulsions d'horloge de référence consécutives est supérieur à n+a.
PCT/US1998/018511 1997-09-09 1998-09-04 Boucle a phase asservie numerique peu sensible aux perturbations employant un detecteur de phase-frequence WO1999013582A1 (fr)

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US92578497A 1997-09-09 1997-09-09
US08/925,784 1997-09-09

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6244871B1 (en) 1996-01-29 2001-06-12 Univ. Of Maryland Baltimore Bioactive glass compositions and methods of treatment using bioactive glass
US6365132B1 (en) 1997-09-18 2002-04-02 Univ. Of Md., Baltimore Methods and compositions for whitening teeth
US6482444B1 (en) 1999-06-14 2002-11-19 Imperial College Innovations Silver-containing, sol/gel derived bioglass compositions
US6663878B1 (en) 1999-04-29 2003-12-16 Usbiomaterials Corp. Anti-inflammatory bioactive glass particulates
EP2613442A1 (fr) * 2012-01-06 2013-07-10 u-blox AG Procédé de détermination de terme de décalage pour un signal de synthétiseur PLLS à pas fractionnaire, un synthétiseur pour réaliser le procédé, dispositif de traitement de signal et un récepteur GNSS
US11018680B1 (en) 2020-07-15 2021-05-25 Keysight Technologies, Inc. Phase lock loops (PLLS) and methods of initializing PLLS

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1452559A (en) * 1973-12-20 1976-10-13 Hasler Ag Method and device for frequency multiplication
US4843469A (en) * 1987-04-13 1989-06-27 The Grass Valley Group, Inc. Rapid signal acquisition and phase averaged horizontal timing from composite sync
US5132642A (en) * 1991-10-04 1992-07-21 Motorola, Inc. PLL using asynchronously resettable divider to reduce lock time
WO1996026604A2 (fr) * 1995-02-20 1996-08-29 Philips Electronics N.V. Dispositif servant a deriver un signal d'horloge a partir d'un signal de synchronisation et enregistreur video muni de ce dispositif

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1452559A (en) * 1973-12-20 1976-10-13 Hasler Ag Method and device for frequency multiplication
US4843469A (en) * 1987-04-13 1989-06-27 The Grass Valley Group, Inc. Rapid signal acquisition and phase averaged horizontal timing from composite sync
US5132642A (en) * 1991-10-04 1992-07-21 Motorola, Inc. PLL using asynchronously resettable divider to reduce lock time
WO1996026604A2 (fr) * 1995-02-20 1996-08-29 Philips Electronics N.V. Dispositif servant a deriver un signal d'horloge a partir d'un signal de synchronisation et enregistreur video muni de ce dispositif

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6244871B1 (en) 1996-01-29 2001-06-12 Univ. Of Maryland Baltimore Bioactive glass compositions and methods of treatment using bioactive glass
US6365132B1 (en) 1997-09-18 2002-04-02 Univ. Of Md., Baltimore Methods and compositions for whitening teeth
US6663878B1 (en) 1999-04-29 2003-12-16 Usbiomaterials Corp. Anti-inflammatory bioactive glass particulates
US6482444B1 (en) 1999-06-14 2002-11-19 Imperial College Innovations Silver-containing, sol/gel derived bioglass compositions
EP2613442A1 (fr) * 2012-01-06 2013-07-10 u-blox AG Procédé de détermination de terme de décalage pour un signal de synthétiseur PLLS à pas fractionnaire, un synthétiseur pour réaliser le procédé, dispositif de traitement de signal et un récepteur GNSS
CN103199858A (zh) * 2012-01-06 2013-07-10 瑞士优北罗股份有限公司 确定fractional-n pll合成器信号偏移项的方法，实现该方法的合成器，信号处理装置及gnss接收机
CN103199858B (zh) * 2012-01-06 2017-05-31 瑞士优北罗股份有限公司 确定fractional‑n pll合成器信号偏移项的方法，实现该方法的合成器，信号处理装置及gnss接收机
US11018680B1 (en) 2020-07-15 2021-05-25 Keysight Technologies, Inc. Phase lock loops (PLLS) and methods of initializing PLLS

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