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WO1999007067A1 - Procede de reglage de la tension de decalage de paires appariees de transistors cmos sur une tension de seuil - Google Patents

Procede de reglage de la tension de decalage de paires appariees de transistors cmos sur une tension de seuil Download PDF

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Publication number
WO1999007067A1
WO1999007067A1 PCT/US1998/015674 US9815674W WO9907067A1 WO 1999007067 A1 WO1999007067 A1 WO 1999007067A1 US 9815674 W US9815674 W US 9815674W WO 9907067 A1 WO9907067 A1 WO 9907067A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistors
voltage
substrate
offset
biasing
Prior art date
Application number
PCT/US1998/015674
Other languages
English (en)
Inventor
Donald M. Bartlett
Original Assignee
Lsi Logic Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corporation filed Critical Lsi Logic Corporation
Priority to AU90142/98A priority Critical patent/AU9014298A/en
Publication of WO1999007067A1 publication Critical patent/WO1999007067A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45766—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using balancing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45342—Indexing scheme relating to differential amplifiers the AAC comprising control means on a back gate of the AAC

Definitions

  • the present invention relates to transistors and more particularly to adjusting the threshold voltage of the transistors.
  • FIGURE 1 is an input stage differential amplifier that has matched transistors 110 and 120 coupled to an amplifier load 130.
  • amplifier load 130 includes resistors 140 and 150.
  • body or substrate connection 135 is connected to ground.
  • V offset is known as an input offset voltage
  • K is the gain value. This type of amplified signal is undesirable for many analog circuits.
  • V ⁇ is the gate-to- source voltage
  • V t is the threshold voltage.
  • Input offset voltage of matched MOS transistors is usually dominated by two factors: threshold voltage mismatch and gate area mismatch.
  • the threshold voltage V, of a MOS transistor is a function of the voltage between the source and the substrate of the MOS transistor. This is known as the "body effect.”
  • the equation for the threshold voltage V, that takes into account the body effect is:
  • V t V t0 + ⁇ (2 ⁇ + sb b* - 2 ⁇ * (1).
  • ⁇ is the constant that describes the body effect and depends upon the physical properties of the MOS transistor
  • ⁇ is the Fermi level potential
  • V offset can be described as: V offset - V gsU0 - V gsl20 (2), and
  • Vgs is the gate-to-source voltage
  • V tll0 is the threshold voltage of transistor 110
  • V tl20 is the threshold voltage of transistor 120
  • I dl is the drain current of transistor 110
  • 1 ⁇ is the drain current of transistor 120
  • ⁇ is the mobility of the channel for both transistors 110 and 120 (this parameter is determined by the silicon process)
  • C ox is the capacitance of the gate oxide per area
  • W is the physical drawn width of transistors 110 and 120
  • L is the physical drawn length of transistors 110 and 120.
  • V offset 0.
  • V offset ⁇ 0.
  • One way to trim the offset voltage V offset is by physically trimming the load devices in amplifier load 130. This can be accomplished by trimming resistors in amplifier load 130 with a laser. However, this method is intrusive, not accurate and once made, the device cannot be adjusted again when in the field. Consequently, a need exists for a device that provides a transistor pair with a reduced offset voltage, particularly over the life span of the transistor pair. The present invention meets this need.
  • the present invention includes a method for reducing an offset voltage for transistors.
  • the method independently biases a substrate of one of the transistors so that the threshold voltages of the transistors change. This change causes the gate-to-source voltage to change, which can be used to reduce the offset voltage.
  • the biasing includes providing an adjustable bias voltage, such as provided by a digital-to-analog converter.
  • the method further includes biasing a substrate of the other transistor.
  • the offset voltage is measured at the gates of the transistors and, once determined, the adjustable bias voltage is adjusted to maximally reduce the offset voltage.
  • FIGURE 1 is a diagram of an amplifier with a load
  • FIGURE 2 is a diagram of an amplifier with a load incorporating an embodiment of the present invention.
  • each of the parameters can be termed as the difference of that parameter between matched transistors.
  • the difference in drain currents I d for transistors 110 and 120 is:
  • the threshold voltages V tll0 and V tl20 can be made to vary with respect to each other. As a result, varying the threshold voltages V tll0 and V tl20 will compensate for any offset voltage V offset due to differences in the other parameters of Equation 4. As will be described below, the present invention utilizes independent control of the substrate-bias voltage V sb to compensate for the input offset voltage V offset .
  • An amplifier load 210 includes resistors 207 and 209, and is coupled to a power supply via a lead 205.
  • Amplifier load 210 is coupled to drains of n-channel transistors 220 and 230 through respective leads 223 and 233.
  • Gates of transistors 220 and 230 are coupled to receive input voltages on respective leads 225 and 235.
  • Sources of transistors 220 and 230 are coupled to a node 240 via respective leads 227 and 237.
  • Node 240 is coupled to another power supply 250 that provides a voltage or ground reference.
  • a current source 260 is provided between node 240 and ground reference 250.
  • a substrate of transistor 220 is coupled to a digital-to-analog converter (DAC)
  • DAC 270 is coupled to receive a digital signal on a lead 275.
  • a substrate of transistor 230 is coupled to a voltage supply 280 via a lead 239.
  • Voltage supply 280 is coupled to ground reference 250 via a lead 285.
  • Terminals 290 and 295 are coupled to leads 222 and 232, at nodes 292 and 297, respectively. The operation of the present invention will be explained with reference to
  • Voltage supply 280 preferably provides a positive voltage bias to the substrate of transistor 230 so that DAC 270 will only have to provide a minimal voltage bias of 0V.
  • DAC 270 outputs a voltage on lead 229 in response to the digital signal input.
  • the output voltage of DAC 270 can be adjusted, which in turn will adjust the substrate bias voltage V sb for transistor 220.
  • the difference between threshold voltages V, for transistors 210 and 220 can be adjusted, which will cause a change in the drain-source current 1 ⁇ .
  • DAC 270 can be adjusted to minimize the offset voltage V offset , preferably to OV.
  • the present invention is particularly advantageous in calibrating and recalibrating a device having matched transistors.
  • DAC 270 can be adjusted to minimize or zero the offset voltage V offset .
  • the device can also be constantly or controllingly re-calibrated while in use.
  • a comparator or an analog-to-digital converter can be coupled to the device shown in FIGURE 2 to monitor the offset voltage V offset .
  • the comparator or ADC can be coupled at either the gates of transistors 220 and 230, or at terminals 290 and 295. The comparator or ADC can then provide a result in digital format to a microprocessor.
  • the microprocessor then can provide signals to DAC 270 to vary the substrate bias voltage of transistor 220 until the offset voltage V offset is reduced to a minimum or zero.
  • the present invention therefore provides the capability of repeated re-calibration of the device over the device's life span.
  • DAC 270 can be replaced by any source that provides an adjustable or variable voltage. Such a source can be a programmable resistive device.
  • voltage supply 280 can provide any voltage, including 0V.
  • voltage supply 280 can be a DAC or other source of a voltage.
  • the substrate of transistor 230 can be coupled to ground reference 250. It shall be understood that the n-channel transistors 220 and 230 can be replaced by p-channel transistors.
  • the present invention is particularly advantageous for use with fixed common- mode amplifiers requiring good offset performance.
  • Another use of the present invention is for providing an offset adjustment for transistors having small channel width/length that has poor offset performance, but good frequency response.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un procédé servant à limiter la tension de décalage de transistors (220, 230). Ce procédé consiste à polariser de façon indépendante un substrat d'un des transistors (220), de façon à modifier les tensions de seuil des transistors. Cette modification provoque celle de la tension de la grille à la source, ce qu'on peut utiliser afin de limiter la tension de décalage. Cette polarisation consiste à produire une tension de polarisation réglable par l'intermédiaire, par exemple, d'un convertisseur numérique-analogique (270). Ce procédé consiste, de plus, à polariser un substrat de l'autre transistor (230). On mesure la tension de décalage au niveau des grilles des transistors (220, 230). Une fois qu'elle a été déterminée, on règle la tension réglable afin de limiter au maximum la tension de décalage.
PCT/US1998/015674 1997-08-01 1998-07-27 Procede de reglage de la tension de decalage de paires appariees de transistors cmos sur une tension de seuil WO1999007067A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU90142/98A AU9014298A (en) 1997-08-01 1998-07-27 Offset adjustment of cmos matched pairs with body voltage

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US90473497A 1997-08-01 1997-08-01
US08/904,734 1997-08-01

Publications (1)

Publication Number Publication Date
WO1999007067A1 true WO1999007067A1 (fr) 1999-02-11

Family

ID=25419676

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/015674 WO1999007067A1 (fr) 1997-08-01 1998-07-27 Procede de reglage de la tension de decalage de paires appariees de transistors cmos sur une tension de seuil

Country Status (2)

Country Link
AU (1) AU9014298A (fr)
WO (1) WO1999007067A1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1104092A3 (fr) * 1999-10-29 2005-07-27 Hewlett-Packard Company, A Delaware Corporation Amplificateur opérationnel à calibrage numérique d'offset
US7248104B2 (en) 2002-08-19 2007-07-24 Nxp B.V. Operational amplifier
WO2009092475A3 (fr) * 2008-01-25 2010-02-04 International Business Machines Corporation Procédé et appareil pour une amélioration de courants de fet appariés à l'aide d'un convertisseur numérique-analogique
EP2797231A1 (fr) * 2013-04-22 2014-10-29 Samsung Display Co., Ltd. Circuit différentiel désadapté
US9344305B2 (en) 2013-04-22 2016-05-17 Samsung Display Co., Ltd. PVT tolerant differential circuit
JP2018207486A (ja) * 2017-05-31 2018-12-27 株式会社半導体エネルギー研究所 比較回路、半導体装置、電子部品、および電子機器

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367707A2 (fr) * 1988-10-31 1990-05-09 International Business Machines Corporation Montage pour la correction du décalage de zéro d'un amplificateur opérationnel
JPH08125463A (ja) * 1994-10-21 1996-05-17 Hitachi Ltd 半導体集積回路装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0367707A2 (fr) * 1988-10-31 1990-05-09 International Business Machines Corporation Montage pour la correction du décalage de zéro d'un amplificateur opérationnel
JPH08125463A (ja) * 1994-10-21 1996-05-17 Hitachi Ltd 半導体集積回路装置

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
H.N. LEIGHTON: "Back Gate Control Circuits", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 27, no. 6, November 1984 (1984-11-01), NEW YORK US, pages 3607 - 3608, XP002086016 *
PATENT ABSTRACTS OF JAPAN vol. 096, no. 009 30 September 1996 (1996-09-30) *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1104092A3 (fr) * 1999-10-29 2005-07-27 Hewlett-Packard Company, A Delaware Corporation Amplificateur opérationnel à calibrage numérique d'offset
US7248104B2 (en) 2002-08-19 2007-07-24 Nxp B.V. Operational amplifier
WO2009092475A3 (fr) * 2008-01-25 2010-02-04 International Business Machines Corporation Procédé et appareil pour une amélioration de courants de fet appariés à l'aide d'un convertisseur numérique-analogique
EP2797231A1 (fr) * 2013-04-22 2014-10-29 Samsung Display Co., Ltd. Circuit différentiel désadapté
US9344305B2 (en) 2013-04-22 2016-05-17 Samsung Display Co., Ltd. PVT tolerant differential circuit
US9680430B2 (en) 2013-04-22 2017-06-13 Samsung Display Co., Ltd. Mismatched differential circuit
JP2018207486A (ja) * 2017-05-31 2018-12-27 株式会社半導体エネルギー研究所 比較回路、半導体装置、電子部品、および電子機器
US11457167B2 (en) 2017-05-31 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Comparison circuit, semiconductor device, electronic component, and electronic device
US11689829B2 (en) 2017-05-31 2023-06-27 Semiconductor Energy Laboratory Co., Ltd. Comparison circuit, semiconductor device, electronic component, and electronic device

Also Published As

Publication number Publication date
AU9014298A (en) 1999-02-22

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