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WO1999004495A1 - Boucle a phase asservie et comparateurs de frequences et de phases - Google Patents

Boucle a phase asservie et comparateurs de frequences et de phases Download PDF

Info

Publication number
WO1999004495A1
WO1999004495A1 PCT/US1998/014785 US9814785W WO9904495A1 WO 1999004495 A1 WO1999004495 A1 WO 1999004495A1 US 9814785 W US9814785 W US 9814785W WO 9904495 A1 WO9904495 A1 WO 9904495A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
control voltage
vco
pll
phase detector
Prior art date
Application number
PCT/US1998/014785
Other languages
English (en)
Inventor
Russell E. Cooper
Original Assignee
Microchip Technology Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Incorporated filed Critical Microchip Technology Incorporated
Publication of WO1999004495A1 publication Critical patent/WO1999004495A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator

Definitions

  • the present invention relates generally to phase-locked loop circuits
  • PLLs Phase-locked loops
  • IC integrated circuit
  • a PLL circuit (FIG. 1) includes a phase
  • detector 10 at the input side of the circuit to receive the reference clock signal and the
  • the phase detector compares the
  • the charge pump 13 is lagging or leading the reference clock signal, respectively.
  • low-pass loop filter 15 to remove or substantially reduce the higher frequency
  • the output of the loop filter 15 is applied as an analog control input to a
  • VCO voltage-controlled oscillator
  • the reference signal or other input signal is referred to as the "lock time" (or sometimes,
  • the correction factor provides a voltage adjustment for the VCO.
  • a PLL with a highly stable output frequency usually has a very long
  • PLL is reduced to a manageable level, on the order of microseconds ( ⁇ sec) in contrast
  • PLL usage in a system that performs a control function such as in a microcontroller
  • the PLL has a loop filter with a preset reference voltage to bias the
  • the loop filter is followed by a
  • the circuit commences from a zero voltage
  • the pump up takes place at a steep ramp toward the threshold level.
  • the reference is tantamount to a dynamic ground which assures that the PLL will move
  • Lock time is achieved on the order of microseconds versus other PLL circuit lock times which are typically greater
  • PLL to generate a control signal indicative of the need to pump up or to pump down the
  • threshold level is applied to a node within the loop filter which will produce a rapidly
  • detector provides a fine adjustment to reach the frequency match.
  • Another aim of the invention is to use a successive approximation
  • the present invention provides a very stable, single frequency PLL with
  • the PLL circuit includes a VCO and a capacitive digital-to-
  • DAC analog converter
  • a correction factor is derived from a comparison
  • That part of the PLL circuit provides a gross adjustment.
  • FIG. 1 is a block diagram of a classic implementation of a PLL system
  • FIG. 2 is a block diagram of a preferred embodiment of a PLL
  • FIG. 3 is a timing diagram for the PLL of FIG. 2.
  • FIG. 4 is a block diagram of an exemplary embodiment of a frequency
  • FIG. 2 which illustrates a phase-
  • the circuit includes
  • VCO voltage controlled oscillator
  • phase detector 32 phase detector
  • phase detector is employed for fine adjustment or fine tuning of the final (match)
  • VCO 30 The VCO-generated frequency (or simply, the generated frequency) F 0 u ⁇ is applied as F GEN to one input terminal of phase detector 32.
  • a reference frequency F ⁇ p with which F GEN is to be synchronized is applied as a
  • the phase detector develops an output in the form
  • phase detector 32 The specific output developed by phase detector 32 is a voltage level
  • circuit is fabricated (which may be integrated, for example, with a microcontroller or
  • MCU (not shown) to be used for controlling a parameter of a system of a type that
  • phase detector output voltage develops a current through and voltage drop
  • capacitor 35 is connected between VI and V ss to be charged up and to limit the voltage
  • phase detector 32 will generate an "up"
  • phase detector relies on clock pulse edges. For example, the
  • detector may observe that the reference clock edges are arriving sooner than the
  • filter resistor 33 is chosen
  • the filter resistor value should not be so large that an
  • Phase detector 32 and VCO 30 may of completely conventional
  • DAC digital -to- analog converter
  • the DAC is used to provide a rough but extremely fast correction of
  • the DAC includes frequency comparator 36 and successive
  • SAR approximation register
  • the frequency comparator then compares the
  • phase detector 32 compares the phases of the two. In this instance, however, the
  • the objective is to cause the SAR to rapidly generate
  • This objective is achieved by causing the SAR to estimate the final value
  • the exemplary 6-bit SAR 37 (which may of a greater or lesser number
  • MSB most significant bit
  • the timing diagram of FIG. 3 illustrates this operation, each part of the
  • Part B indicates the timing for
  • control unit 42 is conventional logic circuitry whose
  • VCO VCO attained a stable frequency
  • the DAC would simply vacillate and thereby unduly
  • Control unit 42 also holds the phase detector 32 in reset mode
  • SAR 37 comprises a conventional shift register (not shown), which at
  • the last stage produces a shift out as a binary 1 (part E of FIG. 3) to enable phase
  • detector 32 to commence fine adjustment of the VCO to the correct frequency and, in
  • Part F of the timing diagram of FIG. 3 illustrates the stepped excursion
  • the voltage input to the VCO — ranges between minimum and maximum values, for
  • part F shows solid line branching of the
  • frequency comparator 36 In the exemplary embodiment of FIG. 4, frequency comparator 36
  • n-bit (where n is the minimum size) racing counters 50 and 51
  • each is a 3-bit counter. The reset for each counter is released
  • RST2 control reset
  • the MSB of counter 50 will be a 0 at the time when the MSB of counter 51
  • the delay path is determined by the number of bits in each n-bit counter.
  • n should be selected as a compromise or trade-off between relatively good
  • a 3-bit counter is preferred as the minimum count to determine clock speed.
  • the frequency comparator will chase a moving frequency, with resulting
  • associated flip-flops 54 and 55 also provide the data clock to the SAR, to indicate the
  • the VCO output will include a divide-down
  • a capacitive DAC is preferred over any other type of DAC approach oi ⁇
  • the first capacitor 32C is charged up while the others are held
  • the phase detector when the SAR stepping is completed, the phase detector can effect a
  • phase detector or discharged as desired because it appears to be a capacitive load to the phase detector.
  • phase detector would be unable to make a change in

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

L'invention concerne un procédé permettant de synchroniser une fréquence produite localement avec une fréquence de référence au moyen d'une boucle à phase asservie configurée pour fonctionner de manière à réduire le temps d'asservissement nécessaire à la synchronisation. La boucle à phase asservie comprend un oscillateur commandé en tension permettant de produire la fréquence locale en réponse à une entrée tension de commande réglable dans l'oscillateur, et un détecteur de phase pour régler la tension de commande en fonction d'un manque de synchronisation entre la fréquence locale et la fréquence de référence. La tension commande appliquée à l'oscillateur est d'abord réglée rapidement par approximations successives dans une direction apte à réduire le décalage de fréquence entre la fréquence locale et la fréquence de référence et s'approcher ainsi rapidement d'une synchronisation entre les deux. Le détecteur de phase peut alors effectuer un réglage final de la tension de commande pour réaliser la synchronisation.
PCT/US1998/014785 1997-07-18 1998-07-16 Boucle a phase asservie et comparateurs de frequences et de phases WO1999004495A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US89646197A 1997-07-18 1997-07-18
US08/896,461 1997-07-18

Publications (1)

Publication Number Publication Date
WO1999004495A1 true WO1999004495A1 (fr) 1999-01-28

Family

ID=25406253

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/014785 WO1999004495A1 (fr) 1997-07-18 1998-07-16 Boucle a phase asservie et comparateurs de frequences et de phases

Country Status (2)

Country Link
TW (1) TW421922B (fr)
WO (1) WO1999004495A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545547B2 (en) * 2000-08-18 2003-04-08 Texas Instruments Incorporated Method for tuning a VCO using a phase lock loop
WO2003077422A3 (fr) * 2002-03-06 2004-09-23 Qualcomm Inc Techniques d'etalonnage pour synthetiseurs de frequences
CN116094518A (zh) * 2022-12-30 2023-05-09 成都电科星拓科技有限公司 一种高精度全数字锁相环环路的复位方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI288531B (en) 2004-02-26 2007-10-11 Mediatek Inc Phase locked loop for generating an output signal

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads
WO1994026041A2 (fr) * 1993-04-20 1994-11-10 Rca Thomson Licensing Corporation Boucle a verrouillage de phase a mode de fonctionnement de repos pendant la suppression de trame
GB2305558A (en) * 1995-09-19 1997-04-09 Fujitsu Ltd Digital frequency, phase control circuits
EP0768756A2 (fr) * 1995-10-13 1997-04-16 Pioneer Electronic Corporation Récepteur et circuit d'accord à synthétiseur de fréquence pour celui-ci

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994026041A2 (fr) * 1993-04-20 1994-11-10 Rca Thomson Licensing Corporation Boucle a verrouillage de phase a mode de fonctionnement de repos pendant la suppression de trame
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads
GB2305558A (en) * 1995-09-19 1997-04-09 Fujitsu Ltd Digital frequency, phase control circuits
EP0768756A2 (fr) * 1995-10-13 1997-04-16 Pioneer Electronic Corporation Récepteur et circuit d'accord à synthétiseur de fréquence pour celui-ci

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545547B2 (en) * 2000-08-18 2003-04-08 Texas Instruments Incorporated Method for tuning a VCO using a phase lock loop
WO2003077422A3 (fr) * 2002-03-06 2004-09-23 Qualcomm Inc Techniques d'etalonnage pour synthetiseurs de frequences
US7546097B2 (en) 2002-03-06 2009-06-09 Qualcomm Incorporated Calibration techniques for frequency synthesizers
US8019301B2 (en) 2002-03-06 2011-09-13 Qualcomm Incorporated Calibration techniques for frequency synthesizers
CN116094518A (zh) * 2022-12-30 2023-05-09 成都电科星拓科技有限公司 一种高精度全数字锁相环环路的复位方法
CN116094518B (zh) * 2022-12-30 2024-04-05 成都电科星拓科技有限公司 一种高精度全数字锁相环环路的复位方法

Also Published As

Publication number Publication date
TW421922B (en) 2001-02-11

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