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WO1999067911A2 - Procede et systeme de gestion d'une ligne d'abonne numerique - Google Patents

Procede et systeme de gestion d'une ligne d'abonne numerique Download PDF

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Publication number
WO1999067911A2
WO1999067911A2 PCT/US1999/014372 US9914372W WO9967911A2 WO 1999067911 A2 WO1999067911 A2 WO 1999067911A2 US 9914372 W US9914372 W US 9914372W WO 9967911 A2 WO9967911 A2 WO 9967911A2
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WO
WIPO (PCT)
Prior art keywords
modem
mailbox
adsl
data
usp
Prior art date
Application number
PCT/US1999/014372
Other languages
English (en)
Other versions
WO1999067911A3 (fr
Inventor
Kenny Ying Theeng Lee
Original Assignee
Ricos International, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricos International, Inc. filed Critical Ricos International, Inc.
Priority to AU47187/99A priority Critical patent/AU4718799A/en
Priority to CA002335450A priority patent/CA2335450A1/fr
Publication of WO1999067911A2 publication Critical patent/WO1999067911A2/fr
Publication of WO1999067911A3 publication Critical patent/WO1999067911A3/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5616—Terminal equipment, e.g. codecs, synch.
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5625—Operations, administration and maintenance [OAM]
    • H04L2012/5627—Fault tolerance and recovery
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling
    • H04L2012/5674—Synchronisation, timing recovery or alignment
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13003—Constructional details of switching devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13034—A/D conversion, code compression/expansion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13058—Interrupt request
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13093—Personal computer, PC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13103—Memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13106—Microprocessor, CPU
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13175—Graphical user interface [GUI], WWW interface, visual indication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13199—Modem, modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13204—Protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13216—Code signals, frame structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1329—Asynchronous transfer mode, ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13299—Bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1332—Logic circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13322—Integrated circuits

Definitions

  • the present system describes a network interface for ATM and/or ADSL communication.
  • Asynchronous transfer mode or ATM is a telecommunications protocol that allows packet based transfer of information.
  • Cells of information are sent across an information network defined by a number of nodes. The information is sent from node-to-node.
  • An ATM transport network (i.e., a communication network which transmits information using ATM cell packets) is known to include an ATM layer and a physical layer.
  • the ATM layer is based on the virtual path/virtual channel (VP/VC) concept.
  • the VC identifies a unidirectional communication capability through which ATM cells are transported.
  • One or more virtual channels (VCs) can be used in a particular virtual path (VP) , which also identifies another level of the communication capability through which the ATM cells are transported.
  • An ATM cell is the smallest information unit. It includes a header field of 5 bytes or octets, and a payload field of 48 bytes or octets.
  • the header field includes VP and VC identifiers.
  • SVC Signaling VC
  • each cell destined for many different end points is sent over a single physical communications circuit.
  • the header of each cell includes a channel identifier which is used to control the routing of the cell through the ATM system.
  • the channel identifier determines routing of the cell.
  • VPI/VCIs channel identifiers
  • DSL digital subscriber line
  • ADSL asymmetric digital subscriber line
  • XDSL digital subscriber line
  • DSL Digital subscriber line techniques or DSL techniques are used to allow communication at extremely high speed over existing copper wire.
  • ADSL provides high speed from the central office to the user, and lower speed in the reverse direction. This recognizes that a user wants to download most of the information
  • ADSL makes the best possible use of bandwidths for certain applications and hence has become extremely popular.
  • the present system uses a special combination of structure to enable controlling and interfacing with an ADSL modem in a personal computer.
  • the present system uses a modem, a processor, a PCI interface and a special purpose chip. This combination allows the software running on the personal computer to be moved through the computer, to the PCI bus, to the modem.
  • FIG. 1 shows a general network architecture of an ATM network
  • FIG. 2 shows a programming interface
  • FIG. 3 shows the application flow between the PC and modem;
  • FIG. 4 shows a block diagram of the network interface card preferably used according to the present system;
  • FIG. 5 shows a block diagram showing the clocking of the present system;
  • FIG. 6 shows a flowchart of the different power-up modes
  • FIG. 7 shows different user selectable operations
  • FIG. 8 shows the reset flowchart
  • FIG. 9 shows dying gas used during reset
  • FIG. 10 shows a power supply layout
  • FIG. 11 shows a block diagram of the application specific integrated circuit ASIC which can be used
  • FIG. 12 shows a network interface diagram with components
  • FIG. 13 shows a flowchart showing some aspects of installation
  • FIG. 14 shows a network interface diagram
  • FIG. 15 shows a screen shot of windows autodetection; PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • FIG. 16 shows a windows NP installation
  • FIG. 17 shows a flowchart of different operations of installation
  • FIG. 18 shows a screen shot of application parameters
  • FIG. 19 shows a service monitor screen shot
  • FIG. 20 shows a service connection screen shot
  • FIG. 21 shows a network connection screen shot
  • FIG. 22 shows the modified network configuration dialog
  • FIG. 23 shows connecting using asynchronous transfer mode over ATM connection dialog
  • FIG. 24 shows the setup of global ATM
  • FIG. 25 shows the setup of network performance for global ATM
  • FIG. 26 shows the optionally configuration parameters tab for ATM
  • FIG. 27 shows a download flowchart
  • FIG. 28 shows a preferred data structure used for the download flowchart
  • FIG. 29 shows a basic block diagram of the ADSL NIC firmware .
  • FIG. 30 shows a first diagram of mailboxes used to communicate the PCI bus and the controller
  • FIG. 31 shows a second block diagram using only part of the mailboxes; PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • FIG. 32 shows a flowchart of operation of the mailboxes
  • FIGs . 33-46 show ADSL open command flows
  • FIG. 47 shows a basic installation process
  • FIG. 48 shows the flow diagram for installing new services
  • FIG. 49 shows a flow of power-up
  • FIG. 50 shows the loading operations occurring on power-up
  • FIG. 51 shows a memory map of the hydrogen chip sets
  • FIG. 52 shows another flowchart of power-up
  • FIG. 53 shows mailbox operations with a hydrogen chip set
  • FIG. 54A shows connecting to the hydrogen
  • FIG. 54B shows direct memory access to the hydrogen.
  • a computer system is connected to the information network through an interface card also called a network interface card or NIC.
  • the ADSL network can be any of a number of different networks, including but not limited to an asynchronous transfer mode or ATM network.
  • One challenge is providing an orderly and useful control of the ADSL connection interface from the host computer system. Since the ADSL NIC is often installed in a personal computer, one desirable way of controlling this is via software routines on the computer.
  • the present description PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • the present application describes programmable interfaces which provide maximum flexibility to control configuration and maintenance of the complex ADSL connections to be configured and maintained.
  • FIG. 1 The overall block diagram of the general network architecture is shown in FIG. 1.
  • the embodiments described herein can operate as part of an ATM system.
  • An ADSL interface card for communicating with an ADSL network is described. More generally, however, this system can operate within any system that carries out data communication by dividing a total message into separate addressed packets, or more specifically in an asynchronous transfer mode system.
  • a PC 125 is, for example, an Internet service provider that provides Internet service to a number of users 98, 99, and others that are not shown.
  • PC 125 includes an ADSL network interface card or "NIC" 110.
  • NIC 110 connects to the telephone line 112 via a plain old telephone system (POTS) splitter 114.
  • POTS plain old telephone system
  • Other POTS equipment 117 can include conventional telephone equipment.
  • a conventional ATM subscriber access multiplexer or "ASAM" 120 connects from telephone line 112 to ATM network 115.
  • ASAM 120 multiplexes a number of communications via the ATM network 115.
  • the NIC 110 becomes a node connecting to the ATM network 115 which allows routing to other nodes, such as second node 150. While only one second node 150 is shown, the ATM network is typically connected to literally thousands of other nodes shown generally in FIG. 1. Any of the multiple nodes can send or receive a message. The connection among these nodes are based on their VCI/VPI identifiers. Node 1 receives a number of cells that will form ATM messages.
  • the ADSL NIC must communicate both with the PC and with the desired network. This can be done using a combination of hardware, software, and firmware running on different platforms, as described herein and shown in FIG. 2.
  • the programming interface is shown as modem control interface 200 lying between the PC application shown as 202 and the firmware assembly shown as 204.
  • the firmware assembly 204 can include the management application 206 on the computer and modem software 208 running in the modem.
  • a modem software ATI 210 communicates between the management application and the modem software.
  • ADSL ADSL
  • the communication pad communicates control information and/or retrieves statistics from the modem.
  • the PC itself is often physically separate from the modem.
  • the modem can be on the PCI bus of the PC. This may require that the modem be polled remotely.
  • One function of the system described herein is to allow PC software to communicate with the software modem.
  • This interface operates by agreeing on how the data will arrive and how the data will be retained.
  • the software ADI controls and receives ADSL status.
  • this data package travels from the very top of the PC application, typically running in Windows, all the way down through the Windows software stack. It arrives at the PCI bus 220, goes across the PCI bus, into the modem processor.
  • the modem processor passes the data across the processor/modem mailbox, which can be a software mailbox implemented in the modem. Data can also flow in the opposite direction by taking the opposite control route.
  • the end user sitting in front of a computer can use the graphical interface of the computer to control the complex ADSL configuration.
  • a unique data package is described herein which includes a destination address and source address.
  • the package allows multiple communications even with multiple entities in the ADSL hardware via the single channel across the PCI. This can be used when the processor is running multiple applications that use the modem.
  • the destination address defines addresses including an ATM processor or an ADSL processor. The proper destination address assures that the correct entity will receive this package, process it, and send it back.
  • the source address is the PCI application running the modem. Alternately, there could be multiple applications running in the PC. For example, multiple windows could be open in the PC, each of which has an application that requires information from the ADSL modem. Each running application can have a different source address, and can send the same information down to the ATM or ADSL modem in order to retrieve information. In return, the source address becomes the correct recipient back up in the PC.
  • the destination address and source address effectively allows PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • FIG. 3 shows the flow of the data transfer in this way
  • FIG. 4 shows a more detailed diagram of the PC-NIC.
  • FIG. 3 shows the PC 300 running two separate applications 302 and 304. Each of the applications in this example is using the ADSL modem to obtain data.
  • the PC sends two different messages shown as 306 and 308, respectively.
  • the first message indicates that it is from application one, by indicating a source address 310 of application one.
  • the messages are sent from the PC 300 to its PCI bus 320, and to the modem.
  • the PCI bus interface in the modem 325 receives the data therefrom.
  • the data is in the specified format that it can be received. This received data is passed to the processor of the modem 330, and then to the ADSL modem 340 and to the ADSL network 350. This data may be requests for status, etc.
  • the disclosed embodiment uses an internal PC printed circuit card in the PCI form factor.
  • a block diagram of the board is shown in Figure 4.
  • the board includes, inter alia, an On Board Controller 400 ("OBC") that can include a processor, an FPGA/ASIC assembly 410, an SAR "Hydrogen” chip set 420, power supply 430, PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • the assembly runs Modem initialization, Power on Self Test (POST), performance monitoring, and control interface routines among others.
  • POST Power on Self Test
  • the Hydrogen 420 includes firmware that runs download software, control information passing, and POST initiation.
  • the ADSL NIC-ATM conforms to all physical requirements for a full size PCI bus card. Throughout this document, all references to the PCI bus are as defined in the PCI Local Bus Specification, Revision 2.1.
  • the ADSL NIC-ATM has the following dimensions:
  • the ADSL NIC-ATM PCB edge connector is configured as a 32 bit, 5 volt PCI bus interface card.
  • An external interface is through an RJ-14 PCB mount connector using pins 2 and 5. This connector is accessed through a card edge mounting plate mounted on the PCB.
  • An optional RJ-45 connector can be provided as a PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • “stuffing” option i.e. an option that can be added on to the basic structure.
  • At least one red/green bi-color LED 399 is mounted on the PCB in a location to be visible through the card edge mounting plate.
  • Clock distribution on the board requires multiple domains.
  • the different clocks and their formation are illustrated in FIG.5. This includes Clock domains that exist on the Hydrogen IC, the PCI clock domain and the ARM 400 clock also have their own domains.
  • the Hydrogen chip takes the PCI 33 MHZ clock 502 from the PCI bus edge connector 440 to the Hydrogen IC 420.
  • the Hydrogen IC is placed to minimize the distance of this clock routing.
  • the Hydrogen 420 operates at 32 MHZ internally.
  • This 32 MHZ clock 505 is derived from a 8 MHZ oscillator 504 connected to an external 8 MHZ crystal 502.
  • the 8 MHZ crystal is placed to minimize the oscillator input and output trace lengths.
  • Each side of the crystal is coupled to ground through 12 pF caps 510, 512.
  • a I M ohm shunt resistor 514 across the crystal is also provided.
  • the 32 MHZ clock 505 is also output from the Hydrogen IC to the ASIC 410. This output is active whenever the 8 MHZ oscillator is operating.
  • a 16 MHZ "expansion bus" clock 515 is output from the Hydrogen IC to the ASIC.
  • the ASIC is positioned to minimize the trace length of this clock signal.
  • the bus clock is active whenever the system clock is operating.
  • the ASIC generates Utopia TXCLK 516 and RXCLK 517 signals and derived from the Expansion Bus Clock. These clock signals operate at 16 MHZ and are present whenever the Expansion Bus Clock is operating.
  • the 16 MHZ operating frequency is within specified operating parameters of both the SACHEM (25 MHZ) and Hydrogen (33 MHZ) Utopia interfaces.
  • the TXCLK is routed from the ASIC through a level shift buffer 520 to minimize skew between TXCLK and TXD[0:7] when the Txdata is received at the SACHEM Utopia interface.
  • the level shift buffer can be part of the ASIC 410.
  • the OBC clock 526 is generated using an on board 25 MHZ oscillator 525.
  • the oscillator is positioned near the OBC to minimize the length of this clock routing.
  • the oscillator operates whenever power is applied to the board.
  • This clock is also routed to the ASIC 410 for distribution/level shift to the SACHEM OBC interface.
  • the ADSL-C clock 530 is derived using an on board crystal driver/receiver 535.
  • a 35.328 MHZ/crystal 534 is placed on the board to minimize the length of these signal traces.
  • the external circuit to provide VXCO control is implemented as specified by Alcatel.
  • the Master Clock output from the ADSL-C 450 is routed to the SACHEM IC 460.
  • the Master Sachem Clock is received from the ADSL-C. Routing distance for this signal is also minimized.
  • the PCLK input is routed from the ASIC at the processor clock frequency.
  • the DUART clock is generated using an on board oscillator and an external 1.8432 MHZ Crystal 540.
  • the crystal is placed to minimize the oscillator input and output trace lengths.
  • a I M ohm shunt resistor across the crystal is provided.
  • Initialization of the modem can be carried out on power up or on reset.
  • the power up routine is shown in Figure 6. Normal and standalone modes of power up are supported. The mode is controlled by jumper selection of the state of the standalone pin 411 of the ASIC.
  • Step 600 first determines the state of the jumper 411. If the jumper is off, normal power up is started at 602. When power is applied to the board, the Hydrogen IC, ASIC, OBC, and modem components are held in a reset state at 602. PCI bus configuration is performed at 604 by loading PCI configuration parameters from the serial boot PROM 412.
  • the Hydrogen run time software is downloaded via the PCI bus 440, to the onboard PCI bus boot ROM 422 at 606.
  • a number of user-defined configuration options are allowed, and are set via the user interface.
  • One such option is the Hydrogen self test. Some of these options are shown in Figure 7.
  • the Hydrogen IC is released from reset, and PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • the Hydrogen 420 executes a series of self test functions at 608 if Hydrogen self test is selected at 702. Upon completion of these tests, the Hydrogen 420 downloads the run time software image to the OBC DRAM 402, at 610, from the Host. After completion of this download, the Hydrogen 420 sends a command to the ASIC 410 to the OBC 400 to release from reset at 612. The OBC then executes optional self test functions if selected. The OBC performs modem initialization and setup at 614.
  • standalone power up mode is selected. This mode is used, for example, for testing and development. In this mode, power is applied to the board, causing the hydrogen 420 to operate.
  • the standalone routine executes PCI configuration at 622, followed by download of code at 624. Optional self test functions and hydrogen initialization are carried out at 626. After completion, normal execution is carried out.
  • the OBC starts in standalone mode by bootstrapping from flash 404 at 628.
  • Optional self test functions are carried out at 630, and OBC initialization and modem setup at 632, followed by normal execution.
  • Two modes of reset are also supported and controlled by jumper selection of the state of the standalone jumper 411 of the ASIC 410. If a failure is detected by the host software during reset, the host software informs the user of the suspected failure via the user interface.
  • the reset flowchart is shown in FIG. 8. If the jumper is off at 800, normal reset is declared.
  • a reset can be initiated from the PCI bus by assertion of the RESET# line detected at 800.
  • the reset from PCI can only be alone after the assembly has been configured and is operational, with operating power still available to the assembly.
  • a dying gasp message is transmitted at 804 before implementing the reset function.
  • the dying gasp signal is a signal that is sent from the modem to applications and/or services that are communicating with the modem. The signal tells these services that the modem is about to be reset. Then, a power up (starting step 602) is called executing the power up instructions 602-614.
  • Soft reset can be initiated via a command from the Host detected at 810.
  • Soft reset first carries out hydrogen bootstrap at 812. This is optional depending on soft reset definition.
  • An optional hydrogen self test functions is carried out at 814.
  • Hydrogen initialization is then done at 816.
  • OBC download is optional (shown as 708) depending on soft reset definition, and is carried out at 818.
  • OBC self test functions again optional, are done at 820.
  • OBC initialization and modem setup are done at 822. Then, the normal OBC and hydrogen operation continues. If the jumper 411 is on at 800, standalone reset is declared. A reset can then be initiated from the PCI bus by assertion of the RESET# line at 829. Note that the use of # after a signal name indicates an active low signal. This signal holds the OBC in reset at 830 (by the ASIC) for 16,384 clock cycles to ensure stable clock and VCC conditions. After this a complete power up cycle is called at 806. The ASIC then releases the OBC from reset for normal initialization functions to proceed. When a "soft" reset is initiated via a command from the host at 832, the following sequence is executed by the Hydrogen IC:
  • the OBC then executes the following sequence:
  • the PC-NIC When the standalone mode is selected, the PC-NIC provides a push button reset capability.
  • ying gasp is implemented whenever commanded by the Host processor software selected at 706. This function is implemented as part of a controlled power down/shutdown sequence for the Host or a Host application occurring under the control of the Host operating system.
  • the PCI-NIC can generate a Dying Gasp message 804 responsive to a hard reset initiated by assertion of the PCI bus RESET# line while power is still applied to the PC-NIC.
  • An alternative is shown in Figure 9. This support is provided by allowing the OBC 400, under software control, to enable a SAR-RESET# signal, to generate an interrupt at 902 rather than an OBC reset signal. The OBC then produces the Dying Gasp at 904. The OBC 400 then PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • Dying Gasp requires that the time to generate the dying gasp is less than the time required to start downloading the OBC code. Since a hard reset will initiate a complete restart of the computer and the operating system (on the order of several seconds minimum) , the dying gasp message will be complete long before the download of code can begin.
  • Switched +12 Volts can also be output to provide remote power for an active caps splitter. This output is current limited to 50 ma. and is intended for application in European markets .
  • the Hydrogen IC is completely described in the CL-PS7900 data book from ATML and Cirrus Logic. Functions implemented in this IC include:
  • the NIC uses the PCI bus interface of the Hydrogen chip to implement the PCI rev. 2.1 interface.
  • the PCI bus pins on the Hydrogen chip 420 is connected to the PCI bus connector 440. Boundary scan on the PCI bus jumpers TDI to TDO.
  • the Hydrogen IC 420 requires the two Clock inputs described above.
  • Clock 502 is for the PCI bus interface, and clock 501 is for internal processing.
  • the Hydrogen 420 also generates output clocks for expansion bus operation, system clock, and reference clock.
  • the PCI Bus Clock input 502 is provided from the PCI bus. It operates at 33.33 MHZ (30 nsec period) maximum. This clock is used for all PCI bus functions and the PCI bus controller.
  • the ARM system clock input is a 64 MHZ internal system clock that is derived from the 8 MHZ crystal 506.
  • a clock input Clkln and crystal driver output (ClkOut) are provided on the Hydrogen chip to drive this crystal.
  • the 8 MHZ clock drives an internal phase locked loop that generates the on board system clock. This is used to generate all on board clock signals for the Hydrogen IC.
  • Each clock output is filtered appropriately for electromagnetic coupling considerations.
  • the Hydrogen IC can include up to 16 Mbits of DRAM. 256K X 32 bits 512K X 32 bits
  • the DRAM multiplexed address and CAS/RAS signals are provided by the Hydrogen IC.
  • DRAM resides in address space starting at 10000(h).
  • Each DRAM device is provided with a 0.1 uF decoupling capacitor, and DRAM chips share a single 10 uF decoupling capacitor.
  • Up to 8Kbits of serial EEPROM 422 is interfaced via the PC bus of the Hydrogen chip.
  • a serial PROM 412 is used to store the PCI configuration parameters and is provided and connected to the GPIO pins.
  • the UTOPIA level 1 interface of the Hydrogen IC is connected to the ADSL Modem chip 450, the ASIC 410, which includes a level shifter therein. Connections are as follows:
  • Utopia outputs from the Hydrogen IC are TTL outputs. These signals are level shifted by ASIC 410 and routed to the SACHEM IC 460. No tristate of these signals is used.
  • Output signals from the Hydrogen IC 420 are 5 Volt TTL outputs.
  • Corresponding inputs to the Sachem IC 460 are 3.3 Volt inputs that are not 5 Volt tolerant.
  • a level shift is performed to interface them.
  • Level shifting is performed using a 74LPT244 non inverting buffer or equivalent with propagation delay of less than 5.0 nsec worst case.
  • An 8 KHz clock supplied by the SACHEM modem 460 is routed to GP103.
  • This pin is an 5 volt I/O pin, and has required protection against over voltage conditions being applied to this pin by inadvertent programming of the Hydrogen I/O pin on the PC-NIC.
  • An optional, debugging, ATM25 interface 423 is used to facilitate firmware and software development.
  • the Utopia interface to the ADSL modem chip is disconnected so that only one of the UTOPIA or ATM25 interface can be used at a time on the Hydrogen chip.
  • One pin of the Hydrogen GPIO is used to drive the bi-color LED 399.
  • the LED is given to indicate more information about the modem. Red is used to indicate power on, but no ADSL line sync having been established, or that line sync has been lost. Green is used to indicate power on and ADSL line sync established.
  • the Hydrogen IC DUART I/O pins are connected to a three pin header 424 to assist in software debug and development for run time software.
  • the power supply layout is shown in Figure 10.
  • the Hydrogen Chip draws its operating power from the PCI bus supplied 5VDC PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • Decoupling associated with this device includes a 10 uF cap, and 8 0.1 uF cap.
  • +5 Volt Power is isolated from the PCB +5 Volt distribution using an inductive element 1002. This creates a +5 Volt Node specific to this IC to which the decoupling is referenced. The clock oscillator use this same unique +5V node.
  • Boundary Scan pins are connected to test points to allow a boundary scan test of the Hydrogen IC.
  • the FIG. 4 block diagram shows an ASIC 410.
  • the ASIC provides a control interface between Hydrogen, and the SACHEM modem chip 460, a control interface between the Hydrogen 420 and the OBC processor 400, a level shifter for control signals between Hydrogen 420 and SACHEM 460, a level shifter interface between OBC 400 and SACHEM 460, a DRAM refresh circuit for OBC DRAM 402, and an address Decode and control signal generation for the DUART 470.
  • the ASIC is implemented in 3.3 Volt logic with a combination of 5 Volt and 3.3 Volt I/O.
  • An FPGA, or logic gates defined using hardware definition language can alternately be used for development or final product. These are implemented using a 3.3 Volt device with 5 Volt tolerant I/O.
  • the ASIC to Hydrogen interface is implemented to allow 5 Volt TTL compatible signals.
  • the ASIC appears to the Hydrogen IC as memory mapped I/O registers, two blocks of expansion memory (OBC memory and Modem registers) on the Hydrogen Expansion bus and as a set of control/interrupt signals. These signals are defined as:
  • Registers reside in the Hydrogen expansion memory space starting at base address 20000000(h).
  • the registers and their offset addresses are:
  • Bit definitions for this register are:
  • Bit definitions for this register are:
  • Bits in this register are read only. Only IRQ sources that have been enabled are indicated in this register. Any bits set in this register are cleared upon completion of reading this register. Bit definitions for this register are:
  • register can be used for polled operation. Bit definitions for this register are:
  • This register is a 16 bit read/write register that transmits data to/from the OBC. Writes to this register generate an interrupt to the OBC 400 (when enabled by the OBC) . When this register is read, data sent by the OBC 400 is provided to the SAR PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • Read actions also generate an interrupt to the OBC (when enabled by the OBC) .
  • the resets control access to certain registers.
  • the OBC reset bit is bit 0 of the control/status register.
  • the SAR 420 When set, the SAR 420 has direct read/write access to the 256K X 32 OBC memory block for code/data download or upload. This memory block resides at address 20100000(h) of the Hydrogen expansion bus.
  • the Modem reset bit 1 of the control/status register is clear, and the Modem Bus En bit 2 of the control/status register is set, the SAR has direct read/write access to the modem registers. This register block resides at address 20900000(h) of the Hydrogen expansion bus.
  • the ASIC 410 also provides an interface to the OBC 400 to allow communication with the Hydrogen IC 420 as well as to perform level shifting between the OBC bus and the SACHEM 460 bus interface.
  • the ASIC provides DRAM support for the OBC DRAM bank.
  • An input pin 411 to select either normal or 960/modem standalone operation is provided.
  • the ASIC interface signals for the OBC are: PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • Registers reside in the OBC memory space starting at base address 01000000(h).
  • The-registers and their offset addresses are:
  • Bit definitions for the IRQ enable register are:
  • bits in the IRQ source register are set to be read only. Only IRQ sources that have been enabled are indicated in this register. Any bits set in this register are cleared upon completion of a register read.
  • Bits in the IRQ status register are also read only. These bits reflect the status of IRQ sources regardless of enabled/disabled status. This register is used for polled operation. If a change of state occurs during a read of this register, the change of state is not registered until the current read access has been completed. Bit definitions for this register are:
  • the SAR mailbox register 1110 is a 16 bit read/write register that acts as a mailbox. When written to, data 1112 is transmitted to/from the SAR 420. Writes to this register generate an interrupt 1114 to the SAR 420 (when enabled by SAR) . When this register is read, data sent by the SAR is provided to the OBC.
  • Read actions also generate an interrupt to the SAR (when enabled by SAR) .
  • the timer prescaler register is an 8 bit R/W register that controls prescaling of the OBC clock.
  • the output of this prescaler feeds both timer counters that can be used to generate interrupts.
  • the expiration of the prescale counter causes generation of a clock to both timer counters. It also restarts counting down from the programmed value 1132 in this register.
  • the timer #1 divider register is a 16 bit R/W register that controls the division of the prescaler output. When the counter controlled by this register expires, it generates an interrupt and restarts counting from the programmed value.
  • the timer #2 divider register is a 16 bit R/W register that controls the division of the prescaler output. When the counter controlled by this register expires, it generates an interrupt and restarts counting from the programmed value.
  • the refresh counter register 1160 is a 10 bit R/W register that controls the refresh rate of the DRAM refresh circuit.
  • Refresh cycles are performed at a rate determined by 1/PCLK * Count. Its default value is set to 300, which results in a PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • Modem register access is controlled by the Modem reset bit. r-bit 0 of the control/status register and the Modem Bus En bit 1 of the control/status register. When both are clear, the Modem
  • Registers reside in the OBC memory space starting at base address 02000000(h) .
  • the ASIC also provides support signals for two blocks of 256K X 32 DRAM 1170.
  • the signals include: • MA[9:0] Multiplexed Address bus
  • a refresh cycle has 8 clock cycles organized as follows
  • a refresh cycle is requested during a memory access, the refresh cycles are implemented after completion of the memory access. If an access is requested during a refresh cycle, the RDY line is used to force wait states to allow refresh completion. DRAM accesses are supported by generation of RASx and CASx signals in conjunction with the top and bottom halves of the address bus. OE# and WR# are generated to perform read or write access. Programmable wait states (0-3) for non burst and burst accesses are supported to allow use of the most cost effective
  • DRAM that meets performance requirements. All multiplexing of the DRAM address bus is performed by the ASIC. Byte accesses and burst accesses are supported.
  • the ASIC supports operations in standalone, and normal operation depending on the signal received at 401.
  • the ASIC When the standalone input pin 401 is pulled high, the ASIC allows the processor 400 to operate in a standalone mode. In this mode, the IBR is read from addresses 1FFF30 through 1FFF60 of the Flash memory 404, by decoding the external bus address and enabling read from the Flash memory.
  • the ASIC forces the processor 400 to operate in normal mode with RESET and RAM load being performed under control of the Hydrogen IC 420.
  • the IBR is read from the mailbox 1110 by decoding the external bus address and enabling reads from the 426.
  • Connections between the ASIC and the Sachem Modem 460 include:
  • All signals between the Modem and ASIC are routed to either the OBC or the SAR based on the state of the Modem Bus Control bit in the SAR status/control register.
  • the DUART 470 is supported by connection of the following signals : • CS# is connected to the ASIC to provide address decode functions
  • the ASIC draws its operating power from the 3.3 Volt onboard supply. 5 Volt I/O is drawn from the PCI-bus-supplied 5VDC.
  • +3.3 Volt Power is isolated from the PCB 3.3 Volt distribution using an inductive element 1004. This creates a +3.3 Volt Node specific to this IC to which the decoupling is referenced. Boundary Scan pins are connected to test points to allow boundary scan test of the ASIC.
  • the OBC controller 400 is implemented by a 80960JA-25 processor. This processor requires a 5 Volt supply, and a 25 MHZ clock input provided by an external oscillator 525 to provide the operating frequency for the OBC.
  • the clock input may alternately be supplied by an ASIC clock output pin.
  • ALE is connected to the ASIC to provide address latching for memory and I/O accesses.
  • AD31 through AD 1 and DO are connected to the ASIC, and the DRAM bank.
  • AD7 through AD1 and DO are connected to the DUART.
  • BE0, BE1, BE2, and BE3 are connected to the ASIC and the DRAM bank to allow byte access to memory and I/O.
  • BE0 is connected to the DUART.
  • RESET# is connected to the ASIC. It is driven low by the ASIC on RESET from the PCI bus. It is driven high or low by the Hydrogen IC via an I/O write to the ASIC.
  • the Hydrogen becomes the bus master PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • HOLD is connected to the ASIC. It is driven high by the ASIC to force the OBC AD bus into tristate during reset, and to allow the Hydrogen IC to access OBC memory during operation.
  • HOLDA is connected to the ASIC. It provides a hold- acknowledge signal to inform the ASIC that the ADBUS is in tristate.
  • INTO# is connected to the ASIC.
  • INT1# and INT2# are connected to the DUART via pullup resistors.
  • W/R#, DT/R# and DEN# are connected to the ASIC to control memory and I/O reads and writes in conjunction with other address and control signals.
  • CLKIN is connected to the ASIC for I/O timing.
  • BLAST# is connected to the ASIC for Burst access support.
  • READY# is connected to the ASIC and is driven by an ASIC provided wait state generator. This signal is used to insert wait states for memory and I/O accesses.
  • Signals connected to the DUART include:
  • DRAM 402 Up to 8 Mbits of DRAM 402 for the OBC are supplied.
  • the configuration of DRAM supported includes: • 256K X 32 bits
  • the DRAM multiplexed address, OE#, WR#, CS#, and CAS/RAS signals are provided by the ASIC.
  • Each DRAM device is provided decoupling capacitors.
  • DUART A 16552 DUART 470 is provided for debug and development.
  • the DUART resides at base address 03000000(h) on the controller bus.
  • Register addresses and programming information are included in the data sheet for the DUART. The following connections are made to the DUART:
  • AO and Al are connected to BEO and BE1 of the OBC
  • A2 is connected to A2 of the OBC
  • CHSL is connected to A3 of the OBC
  • D7 through DO are connected to AD7 through ADl and DO of the
  • RD# is connected to the ASIC
  • SIN1, SIN2, SOUT1, and S0UT2 are connected to an RS-232 transmitter receiver IC
  • XIN and XOUT are connected to a 18.432 MHZ crystal
  • 47 pF cap is connected to the junction of the 1.5K and IM res. 22pf cap is connected to XIN
  • the DUART is provided with decoupling capacitors as follows.
  • An RS-232 driver/receiver 475 such as the MAX203 is used to provide RS-232 compatible levels/thresholds for the two DUART ports. Connections will be as follows:
  • TUN T2IN connected to SOUT1 and SOUT2 of the DUART R10UT
  • R20UT connected to SIN1 and SIN2 of the DUART
  • the RS-232 driver/rec. is provided with decoupling capacitors as follows: • 1 ea 0. 1 ulF cap.
  • a block of Flash programmable Memory 404 is provided.
  • the OBC draws its operating power from the PCI bus-supplied 5VDC.
  • the current drain should be less than 400 ma.
  • Decoupling associated with this device includes a 10 uF cap and 8 of, 0.1 uF caps.
  • +5 Volt Power is isolated from the PCB +5 Volt distribution using an inductive element (s) to create a +5 Volt Node specific to this IC to which the decoupling will be referenced.
  • the ADSL Modem is implemented using the ADSL-C AFE 450 and the Sachem ADSL modem IC 460.
  • the layout and design of the ADSL modem duplicates the design used by Alcatel in their product utilizing the ADSL-C and Sachem chipset.
  • the ADSL-C connects to the line interface 452 and the Sachem I.C 460. Connection to the line interface and Sachem is as PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • ADSL-C defined by Alcatel in their current product.
  • Other connections to the ADSL-C include:
  • PDOWN is connected to the Sachem PDOWN output to implement programmable power down. Signals pulled down through 10 Kohm resistors:
  • ADSL Power supply The ADSL-C draws its operating power from the 3.3 Volt onboard supply. 3.3 Volt current used is less than 190 ma. Decoupling associated with this device includes 2 - 0.1 ⁇ F cap.
  • +3.3 Volt Power is isolated from the PCB 3.3 Volt distribution using an inductive element 1008 to create a +3.3 Volt Node specific to this IC which the decoupling is referenced.
  • the ADSL-C also uses the 3.3 Volt analog on-board supply.
  • Connection to the OBC will be through the on board ASIC to perform level shifting between the 5 Volt OBC and 3.3 Volt Sachem.
  • AD [15:0] connected to ASIC for level shift and distribution to/from OBC and SAR PCLK Output from ASIC for 1/0 timing
  • Connection to the Hydrogen SAR includes the following:
  • TXClk Connected to ASIC through level shifter to provide xfer clock (level shifter included to minimize skew between TXD[0:7] and clock)
  • PDOWN output is connected to the PDOWN input pin of the ADSL-C to implement a programmable power down of the AFE in addition to the RESET power down function implemented by reset of the board.
  • the Sachem draws its operating power from the 3.3 Volt onboard supply.
  • 3.3 Volt current used is less than 370 ma.
  • Decoupling associated with this device includes 1 ea 10 uF cap and 8 ea 0. 1 uF cap.
  • +3.3 Volt Power is isolated from the PCB 3.3 Volt distribution using an inductive element(s). This creates a +3.3 Volt Node specific to this IC which the decoupling is referenced.
  • Boundary Scan pins are connected to test points to allow boundary scan test of the Sachem IC. PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • the layout and design of the line interface duplicates the line interface used by Alcatel in their design using the ADSL-C and Sachem chipset.
  • the line interface 452 has a differential driver, a differential receiver, a hybrid coupling circuit, a line coupling transformer, and a High Pass filter.
  • the line interface is transformer-coupled to an RJ- 14 connector 454.
  • the power supply accepts +5VDC +/- 5% input from either the PCI bus or from an external input connector.
  • 3.3 VDC is derived from this 5 Volt input. Total 5 Volt current will be less than 2 Amps. External connection is supported, e.g., for development purposes .
  • the power supply 430 generates +3.3 VDC +/- 1% from the 5 Volt input using a linear regulator. Connection to the ON/OFF and FLAG pins when a 5 pin regulator is used are provided to the Hydrogen IC GPIO.
  • a 0.51 ohm pass resistor is provided to share power dissipation with the 3.3 Volt regulator.
  • An output capacitor of 22 uF is provided to ensure 1.25 Amp operation with output noise of ⁇ 200uV.
  • a 0.22uF capacitor is placed at the input of the regulator.
  • Analog 3.3 Volts for use by the AFE is derived by an LC filter between the regulated 3.3 Volts and the analog 3.3 Volts.
  • the power supply accepts +12VDC +/- 5% input from either the PCI bus or from an external input connector.
  • +12VDC current is less than 100 ma.
  • An LC filter is provided for the + 12 VDC used on the NIC.
  • the power supply accepts -12VDC +/- 10% input from either the PCI bus or from an external input connector.
  • -12VDC current s less than 100 ma.
  • An LC filter is provided for the - 12 VDC used on the NIC.
  • a DC/DC converter to generate on board +/- 12 Volts DC in place of the PCI bus provided voltages is included.
  • the converter is powered by the PCI Bus 5 VDC and will generate 100 ma output for both + and - 12 VDC.
  • the ASIC is in a 160 PQFP. It supports both 5 Volt and 3.3 Volt I/O.
  • the ADSL Network Interface Card described above operates using at least one of firmware and/or software for operation.
  • the ATM portion of the NIC is based on chips, firmware, and software developed by ATM Ltd. for their own ATM network components .
  • the Network Interface is diagrammed in Figure 12.
  • the installation routines are made up of four main components (oemsetup. inf, netvlink. inf, vlink.def, and atmncdet.dll). The combination of these four components operates as shown in Figure 13.
  • the routine installs the proper utility applications, drivers, ini files, and firmware to support the NIC card chosen by the user at 1302. It then prompts the user for the connection type (Local LAN or ADSL) for the NIC card and configures some PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • initial values for proper operation at 1306.
  • User configurative valves are set, (for example, those shown in Figure 7) at 1308.
  • the installation script format is different for Windows 95 and NT, two "inf" installation scripts are required.
  • the atmncdet.dll library is used to provide user dialogs for gathering information that the scripts could not acquire automatically. This library was written for the MSVC 1.5 development environment .
  • Vstatus and vcons are performance and status monitoring applications used for troubleshooting problems with the NIC card or with the network itself.
  • the main use for vstatus is for status monitoring of uptime, throughput, and system connections as needed.
  • the ARP server, LECS server is used as the Windows environment.
  • Vcons is a DOS console type application that is used as a terminal type connection to the NIC card. This application allows a user to send commands manually to the firmware and see the response .
  • Asock32 or the ATM Sock API is a proprietary API developed by ATML. This interface was designed to conform to Microsoft's guide to extending the Windows Socket API version 1.1. See WinSock documentation by Microsoft for further details.
  • Vsock is the ATM Sock Interface protocol. This is a proprietary protocol with a .vxd or Virtual Device Driver used by ATML which Hayes has purchased the rights to redistribute. This allows any application developed by third parties that use the ATML atmsock API to operate correctly with the Hayes NIC card.
  • This module was coded to comply with MSVC 2.0.
  • the final component to the ATMPC SDK/DDK is the vlink module.
  • This module is the network VXD that vsock and all other protocols communicate to pass data into a network. This module has been developed to work with Windows 95 and NT using NDIS 3.0.
  • the driver's function is limited to only act as a communication interface between the protocol layer and the hardware (NIC) layer.
  • ATML designed all of the encapsulation components for passing other protocols over ATM in the firmware. This driver supports NDIS 3.0 only and was coded to be compiled with MSVC 4.0.
  • Figure 14 shows the Network Interface Diagram with the present hardware components described with reference to Figures 4 to 11.
  • Installation Routines include the oemsetup. inf, hnetinst.inf & atmncdet.dll.
  • User Control and Monitoring Applications include the ServiceMonitor, AdslNicP, and NicCons.
  • Protocol Device Driver is the hAtmSock.
  • Network Device Drivers includes hNetLink and hOdiLink. Their corresponding ATML modules are Installation Routines (oemsetup. inf netvlink. inf, vlink.def atmncdet.dll), Status Applications (vstatus and vcons), Native ATM Protocol (vsock) , and Network Device Driver (vlink) respectively.
  • the OS identifies the NIC at boot-up as new hardware through the PCI plug-and-play capability at 1300. This brings up the screen of Figure 15.
  • Windows NT 3.51/4.0 the user may have to manually select to install a new network adapter and select "Have Disk" to identify the NIC as shown in Figure 4. Once the card is identified, the user is prompted to install drivers for this new hardware.
  • the present installation routines use oemsetup. inf (Used for NT) and hnetinst.inf that is required according to Microsoft's guidelines for hardware and a support library.
  • ATML' s routines including oemsetup. inf, netvlink. inf, and vlink.def are used.
  • the AdslNicP Network Control Panel Extension Library provides the NIC global properties from the Network Control Panel Applet when a user selects properties for the NIC adapter/ Figure 18 shows a screen shot of AdslNicP.exe. Changing any of these parameters changes the network. Since these settings are set at startup, they cannot be dynamically changed after the NIC card is in an operational state. This requires the PC System to be rebooted for the changes to take effect. Hence, these changes cause a "BIND" action. As shown in Figure 18, this application provides a simple graphical interface for users to change global ATM parameters.
  • This interface enables and disables the ILMI. If ILMI is disabled, then the dialog prompts for a proper ATM address.
  • the interface allows setting global signaling for SVC (Switched Virtual Circuits) connections.
  • the interface sets the connection mode for permanent connections (PVC or PVP) .
  • the system determines when the user has made changes to the global settings so a bindery action can be called for the network components. This action prompts the user to reboot before changes will take affect.
  • the routine also provides a means of saving and restoring a single working configuration in case the user makes a change that disables the network.
  • the ServiceMonitor Application has a function to allow the user of a Hayes ATM/ADSL NIC Modem PCI card to manage the network interface and obtain performance information about the network connections. This application must be executed before any network service connections can be established. Software interface provides the functions and applications.
  • the interface uses a Simple Connection Status and Problem Indication.
  • An LED style of status indication similar to the front panel of an analog modem is used. This is accomplished by providing a System Tray Icon in Windows 95 and NT 4.0 system tray as shown in Figure 19). For Windows 3.5x this is accomplished by centering the Tray Icon on the left side of the main dialog (See Figure 6) .
  • the Tray Icon is formed of three artificially simulated LED's. The left represents transmissions of data.
  • the System Tray Icon 1910 responds to various mouse actions. It allows the user to easily acquire global status information about the network interface. A Right Mouse Click brings up a
  • System Menu 1920 displaying optional actions to provide the user with some information about the connection status of some selected services.
  • the two services installed (BlockBuster 1920 and MindSpring 1921) as inactive due to the dark red LEDs 1922, 1924 to their left. If either of them were active, their associated LED turn bright green.
  • the main dialog has global performance information 1905 that can be used to track data flow, connection time, and number of installed services.
  • the connection time and flow rates can also be obtained through a ToolTip feature.
  • connection time and flow rate are displayed.
  • the Service Connection Performance and Network Configuration is shown in Figure 20.
  • the Properties dialog is displayed (as shown in Figure 20) only three main tabs — Services, ATM Interface, and Options.
  • the two modem tabs are meant to be used for troubleshooting modem problems. These are defaulted to not display from the "Options" tab.
  • the default tab to be displayed is the "Services" tab.
  • This control style is a Property Sheet with Property Page Dialogs for tabs. All of the installed service connections are be displayed from a tab control to allow ease of service selection.
  • the installed service tab names are user-configurative to allow customization. This installed service are placed on the Tray Icon system menu at the users request from the "Options" tab.
  • the user interface also provides performance data on all individual connections. To accomplish this, all service connections have the same performance data displayed upon selection of the service tab. This minimizes control creation and provides a consistent user interface to all performance data.
  • Performance data is acquired on 0.5-second intervals.
  • the performance graph is an owner-drawn control created at run time with a ten-second history.
  • User configurative parameters include changing the line colors for data representation.
  • Figure 21 shows the network Configuration Properties Dialog (Service Properties) .
  • the Service Connection Modification of Network Configuration allows the user to manually adjust the connection parameters.
  • “Modify” (See Figure 21 above) is selected from the “Service Properties” dialog. This brings up the “Modify Service” dialog and the previous dialog “Service Properties” disappears. If the service being elected to modify were being actively connected, then a warning dialog appears notifying the user that any changes to an active service could cause loss of data. This warning dialog allows the user to cancel the modify action or continue to bring up the Modify dialog. While the user is in the modification dialog, changes can be made to any of the connection parameters including alteration of the tab name.
  • Figure 22 shows the User Interface Screen to Modify Network Configuration Dialog.
  • This interface allows the user to configure the ATM parameters on a per connection basis as needed.
  • This interface also has enough intelligence to prevent incorrect parameters from being configured (ie. Invalid VPI or VCI values, Policing of Specified Cell Rates to prevent exceeding Max Upstream bandwidth, etc.).
  • the "Settings" button is enabled and brings up a configuration dialog shown in Figure 23 for that protocol if selected.
  • This configuration dialog provides a great amount of flexibility to the user.
  • the user can elect to use the gateway IP address already configured in the TCP/IP protocol stack as the destination machine to connect to the Ethernet LAN. If the connection is a machine other than the gateway, then the user needs to provide the IP address of that machine to complete the connection.
  • This configuration is simplified by the use of SVC ' s or Bridged IPoA. This interface satisfies the need for allowing multiple service configurations.
  • the "Stop" button 2100 in Figure 21 is enabled to allow the user to disable the service PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • Time delay is used instead of a set/reset type of function to avoid the user forgetting that the service has been disabled, and thinking that another problem exists.
  • auto reset functionality the state of the service connection can be returned to normal without any other user interaction.
  • FIG 26 shows the Service Installation Wizard Dialogs Status of Global ATM Connection Performance and Configuration.
  • the ATM Interface dialog displays global performance data and configuration setting to the user. This dialog is intended to be used for providing ISP's with configuration information in the event that a service installation fails or is working improperly.
  • the connection status information is static and cannot be altered by the user in this application.
  • Figure 25 shows Global ATM Network Performance and Configuration.
  • the connection configuration should not be PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • the ADSL Modem Performance and Operational Status is shown by the status monitoring application which displays ADSL modem performance.
  • the two dialogs shown in Figure 25 accomplish this task by statistically displaying modem performance. These dialogs were not designed for the novice user since the intent of these dialogs is to be used for troubleshooting problems with the ADSL modem.
  • the dialogs were designed with the assumption that the user viewing them has some advance degree of knowledge with ADSL technology. These dialogs are normally turned off for viewing through the "Options" tab dialog as shown in Figure 26 below.
  • the Figure 26 dialog includes optional configuration parameters tab dialog.
  • This dialog also provides a means of saving or restoring profile settings. This will be a method of networking for many users. It is expected that the user would need some method of restoration to a known working configuration.
  • These optional functions allow saving and restoring of profiles on a global basis.
  • the NicCons application's main function is to act as a troubleshooting tool for problems that could potentially occur outside the scope of ServiceMonitor ' s control or status monitoring. This application allows the user to work from a command line and send single commands to the NIC and obtain the NIC's response to those commands
  • the vsock protocol device driver from ATML is used as a Protocol Device Driver. This allows supporting any application developed using ATML's API without supporting the API itself.
  • the file name will change to hAtmSock.vxd to simplify recovery of the driver if a user installs an ATML product on the same PC system.
  • the protocol socket is actually a simple connection for passing data off to the driver and then to the firmware. This allows a user application to communicate to the protocol directly implemented in the firmware OS where all PDU ' s (Protocol Data Units) are actually assembled and disassembled. This model allows ATML to port the protocol socket easily to any platform and implement all ⁇ Protocol stack' s> over ATM directly on the Hydrogen chip.
  • ATML provides a plain communication module for sending and receiving data between the PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • This driver operates as follows and as shown in Figure 27: 1 .
  • the duration of the POST sequence shall be less than 5 seconds at 2700.
  • the hNetLink NDIS 3.x Network Virtual Device Driver supports Windows 95 (ver A and OSR2), Windows NT 3.51 (all Service Packs) and Windows NT 4.0 (all Service Packs).
  • the supported protocol stacks for this driver are Microsoft TCP/IP, NeBEUI, and ATML's PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • hOdiLink Netware ODI Virtual Device Driver driver supports the Novell ODI Network Interface under the following versions, Novell Netware 3.12, 4.x, and Novell IntranetWare.
  • the protocol stacks supported are Novell TCP/IP and IPX/SPX.
  • the API for hAtmSock protocol device driver is used for all Native ATM communications and for all management applications (ServiceMonitor, NicCons, etc.). This is a required driver for this product.
  • the method of communication for applications to this driver is through obtaining a handle to the driver using "CreateFile" as shown:
  • hDriver CreateFile ( "WWUkhadslid” GENERIC-READ I GENERIC-WRITE,FILE_SHARE_READ I FILE - SHARE WRITE, NULL.OPEN PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • the dwIoControlCode member is what applications will use to communicate with all devices from this protocol and below.
  • the following control codes are created by using the CTL_CODE macro defined in WINIOCTL.H (macro: CTL_CODE ( DeviceType, Function, Method, Access ) ).
  • CTL_CODE DeviceType, Function, Method, Access
  • the DeviceType, Method, and Access will always be FILE_DEVICE_NETWORK, METHOD_OUT_DIRECT, and FILE_ANY_ACCESS respectively.
  • the code of interest to the applications is the "Function" member. This member falls within the range of 0x800 to Oxfff.
  • the 0x800 to Oxbff range is used for legacy code from ATML and the OxcOO to Oxfff range is used for any new codes defined by Hayes for this project. To ensure that this range is maintained, all control codes begin with 0x00 and use the macros below to get the base address.
  • API for hNetLink was created by ATML to be a MiniPort network driver with minimal functionality for passing data, downloading firmware images and INI files, etc. At present, there are no control codes to be used by this driver.
  • This driver is PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • Communication to the ATM module uses the following control mechanism.
  • NIC_CTLCM D(Destination, Source, OpCode, DataSz) I ((Destination « 24) 1 (Source « 16) 1 (OpCode « 8) 1 (DataSz)
  • CTLCODE #define CTLCMD_OPCODE(NicCtlCmd) ((NicCtlCmd » 8) & STRIP -
  • CTLCODE #define CTLCMD_DATASZ(NicCtlCmd) (NicCtlCmd & STRIP_CTLCODE)
  • Code Generation a) Processor set to "Pentium”.. b) _cdecl Calling convention. c) Run-time Libraries linked statically using Multithreads. d) Struct member alignment should be set to 8 Bytes.
  • Class objects that will be used in multiple source files should be contained in separate source files.
  • the filename should be the name of the Class excluding the "C" header if used (ie. CmyClass - filenames are MyClass.cpp and MyClass.h).
  • the file should contain related functions that correspond to a package of features.
  • the feature should some how be related to the filename (ie. NicComm.c - Source file PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • Header Files Files that have extensions "h;hpp;hxx;hm;inl” .
  • HKEY_CLASSES_ROOT ⁇ ServiceMonitor.Application - ServiceMonitor Application HKEY_CLASSES_ROOT ⁇ ServiceMonitor.Application ⁇ CLSID ⁇ 497A0BC5-2561-11 D1 -SAF8-00805FCDE 1138) HKEY_CLASSES_ROOT ⁇ ServiceMonitor.Application ⁇ CurVer - ServiceMonitor.Application. 1.0
  • module contains an ScodeS.txt file that does describe an alternate code standard, then these standards do not apply. If any work is to be done to enhance the third party application in terms of new code then this guideline is followed. If the work -co enhance third party code is simple bug fixing or minor alteration then attempt to conform to the standard present inside the existing code.
  • MyStructData, *MyStructDataLP PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) O HMPI
  • Oemsetup Setup Information File is the Installation Setup script for the ATM/ADSL NIC product.
  • Atmncdet Setup Extension Library is used with the setup script for executing routines that the script could not support.
  • the AdslNicP Network Control Panel Application is an extension DLL is the "Properties" screen for the NIC Adapter Card launched from the Network Control Panel Applet. This DLL provides the interface for modifying the global ATM and ADSL parameters. This interface is dialog-based and signals the OS when a network bindery action takes place. It also allows the user to save the present settings as the default and restores default settings upon request.
  • Main Dialog Class (AdslNicP.h) object is designed to interface with the user through a dialog based user interface. It is responsible for displaying to the user the current global ATM interface settings and allow him/her to make changes easily. Upon any changes being made and the dialog closing, this object updates the bindery information for all network components through the Network Control Panel Applet. If a change is made that is out of scope with the capability of this NIC then this object notifies this information to the user and provides possible alternative parameters.
  • AdslNicP. h header contains the class member functions and data needed to implement the "Properties" dialog referenced PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP)WO HMPI
  • class CAdslNicP public Cdialog (DECLARE_DYNAMIC(CAdslNicP); //Construction public:
  • CadslNicP(CWnd* pParent NULL); // standard constructor virtual -CAdslNicPO; PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • the m_GlobalSettings and mb_SettingsModified member data is initialized in this function.
  • the m_GlobalSettings data are initialized with GetRegGlobalProfile ( ) and mbSettingsModified ia initialized to false. Return Type: None.
  • Function Params None.
  • Control Panel Applet This in turn notifies the user that he/she should reboot the system before these new settings can take effect.
  • CDialog : OnCancel ( ) functions prior to returning. If either SetRegGlobalProfile ( ) or SetBindaryAction ( ) functions fail, then the user is notified with a standard dialog warning message box. Some attempt is made to ascertain the nature of the failure. If the OS is NT, the user might not be the Administrator, etc.
  • the ServiceMonitor NIC Status and Management Application is the main management and Status application for the NIC Adapter Card.
  • the Main Application Class (ServiceMonitor . h) is the main application class to start the ServiceMonitor Management and control application. Its purpose is to establish all registered messages, create the main dialog for ServiceMonitor, and establish a mechanism for only allowing a single instance of this application to function.
  • OnSmHelp Description: Used for external calls to ServiceMonitor help.
  • the main ServiceMonitor dialog is created with this class.
  • SMWM SCM INSTNEWSERV SMWM SCM CONNDISCONN // Used for internal updates
  • CServiceMonitorProfile mp_SMSessionProfile CBitmap mbc - ServConnStatActive
  • CBitmap mbc_ServConnStatlnactive CBitmap mbc_ServConnStatError; Private:
  • LPVOID mvpj icManager private: char mcsJHRegKey[50]; char mcs_HISRegKey[20]; char mcs_HGblSetRegKey[IO]; char mcs_HGIbATMRegKey[l5]; boo] mb JseGlobal Profile; bool mbJsUserProfileAdmin;
  • Modify Service Class - CModifyService (ModifyService.h)
  • IDD IDD_MODIFY_SERVICE
  • IDD IDD_ATMI_IPSET ⁇ ;
  • HACCEL mhac Slobal CwinApp, *mp_ServiceMonitorApp; bool mbJsAccelHelp; bool mb ProtDataModified; bool mb_Dlglnitialized; bool mb ConnlsSvc; void *mvp_ProtData;
  • ATM Interface Settings Class - CATM Interface Page (ATMInterfacePage.h) ⁇ lnsert Description here!!!> PATENT ATTORNEY DOCKET NO. 10226/003WO1/98109402 (USP) WO HMPI
  • CATMInterfacePageO virtual -CATMinterfacePage(); //Dialog Data private:
  • IDD IDD_ADSL_MODEMPARAMPAGE ⁇
  • IDD IDD_ADSL_MODEMCOUNTERSPAGE ⁇ ;
  • Performance Graph Class - CGraphBar This class object is an owner drawn graph control that subclasses a static window passed in. This control object creates a bitmap graph and displays a ten second history of performance data for three ATM parameters (Transmit, Received, and Discarded cells) .
  • single object instance can maintain data for multiple connections and display a graph for any single connection upon request.
  • ServiceMonitorData.h Data header file for retrieving status
  • HAYES_ATMADSLPROTJMATM 0x00001
  • HAYES_ATMADSLPROTJPOA 0x00002
  • HAYES YTMADSLPROTJ POA 0x00008
  • HAYES_ATMADSLPROTJPXOA 0x00016
  • HAYES ATMADSLPROT NETBOA 0x00032
  • DualEndMR actualBitRate char carrierLoad[HAYES_MAX_CARRIERLOAD+2]; /* Carrier Load String * / JSMDOpParams, *SMDOpParamsLP;

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Communication Control (AREA)
  • Telephonic Communication Services (AREA)

Abstract

La présente invention concerne un système et une interface système pour modem ADSL. L'ensemble modem est constitué, d'une part d'un microcircuit d'interface PCI et d'un processeur, et d'autre part d'un circuit spécifique d'une application (ASIC) montés sur une carte, associé à un microcircuit modem. Le microcircuit d'interface et le processeur peuvent être commandés par du code envoyé par téléchargement. L'invention concerne également une interface utilisateur qui permet à l'ordinateur gestionnaire de produire des commandes destinées à l'ensemble modem.
PCT/US1999/014372 1998-06-24 1999-06-24 Procede et systeme de gestion d'une ligne d'abonne numerique WO1999067911A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU47187/99A AU4718799A (en) 1998-06-24 1999-06-24 Method and system for controlling a digital subscriber line
CA002335450A CA2335450A1 (fr) 1998-06-24 1999-06-24 Procede et systeme de gestion d'une ligne d'abonne numerique

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US9055198P 1998-06-24 1998-06-24
US60/090,551 1998-06-24

Publications (2)

Publication Number Publication Date
WO1999067911A2 true WO1999067911A2 (fr) 1999-12-29
WO1999067911A3 WO1999067911A3 (fr) 2000-07-20

Family

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Application Number Title Priority Date Filing Date
PCT/US1999/014372 WO1999067911A2 (fr) 1998-06-24 1999-06-24 Procede et systeme de gestion d'une ligne d'abonne numerique

Country Status (3)

Country Link
AU (1) AU4718799A (fr)
CA (1) CA2335450A1 (fr)
WO (1) WO1999067911A2 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002035882A1 (fr) * 2000-10-25 2002-05-02 Siemens Aktiengesellschaft Dispositif et procede permettant de couper une liaison de transmission de donnees a debit binaire eleve
EP2497024A2 (fr) * 2009-11-04 2012-09-12 Aware, Inc. Capacité de diagnostic argumenté comprenant g.inp

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61855A (ja) * 1984-03-06 1986-01-06 コ−デツクス・コ−ポレ−シヨン プロセサ・インタフエ−ス回路
US4742482A (en) * 1985-10-29 1988-05-03 Hayes Microcomputer Products, Inc. Modem controller
US5333256A (en) * 1989-05-15 1994-07-26 International Business Machines Corporation Methods of monitoring the status of an application program
US5249218A (en) * 1992-04-06 1993-09-28 Spectrum Information Technologies, Inc. Programmable universal interface system
US5345367A (en) * 1992-09-22 1994-09-06 Intel Corporation Thin form factor computer card
US5617526A (en) * 1994-12-13 1997-04-01 Microsoft Corporation Operating system provided notification area for displaying visual notifications from application programs
US5619250A (en) * 1995-02-19 1997-04-08 Microware Systems Corporation Operating system for interactive television system set top box utilizing dynamic system upgrades
US5742602A (en) * 1995-07-12 1998-04-21 Compaq Computer Corporation Adaptive repeater system
EP0767544A3 (fr) * 1995-10-04 2002-02-27 Interuniversitair Micro-Elektronica Centrum Vzw Modem programmable utilisant la communication à spectre étalé
WO1998006018A2 (fr) * 1996-08-01 1998-02-12 Roxan Telecom. Co., Ltd. Ordinateur apte a reinitialiser un modem en cas de panne due a un danger associe a un reseau externe de communications
US6112015A (en) * 1996-12-06 2000-08-29 Northern Telecom Limited Network management graphical user interface

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002035882A1 (fr) * 2000-10-25 2002-05-02 Siemens Aktiengesellschaft Dispositif et procede permettant de couper une liaison de transmission de donnees a debit binaire eleve
EP2497024A2 (fr) * 2009-11-04 2012-09-12 Aware, Inc. Capacité de diagnostic argumenté comprenant g.inp
EP2497024B1 (fr) * 2009-11-04 2023-05-31 Avago Technologies International Sales Pte. Limited Capacité de diagnostic argumenté comprenant g.inp

Also Published As

Publication number Publication date
CA2335450A1 (fr) 1999-12-29
WO1999067911A3 (fr) 2000-07-20
AU4718799A (en) 2000-01-10

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