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WO1999063667A1 - Tampon de sortie numerique en technologie cmos, a portes separees pour les listes directes et les listes refoulees - Google Patents

Tampon de sortie numerique en technologie cmos, a portes separees pour les listes directes et les listes refoulees Download PDF

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Publication number
WO1999063667A1
WO1999063667A1 PCT/US1999/011485 US9911485W WO9963667A1 WO 1999063667 A1 WO1999063667 A1 WO 1999063667A1 US 9911485 W US9911485 W US 9911485W WO 9963667 A1 WO9963667 A1 WO 9963667A1
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WO
WIPO (PCT)
Prior art keywords
inverter
pull
fall
rise
slow
Prior art date
Application number
PCT/US1999/011485
Other languages
English (en)
Inventor
Charles James Persico
Original Assignee
Qualcomm Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Incorporated filed Critical Qualcomm Incorporated
Priority to AU42021/99A priority Critical patent/AU4202199A/en
Publication of WO1999063667A1 publication Critical patent/WO1999063667A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits

Definitions

  • a CMOS buffer interconnecting a signal input line and a signal output line, said CMOS buffer comprising: fast-rise /slow-fall inverter means for inverting a signal received from the signal input line; slow-rise /fast-fall inverter means for inverting the signal received from the signal input line; pull-up means, responsive to receipt of a high voltage signal from the fast-rise /slow-fall inverter means, for pulling up a voltage on the signal output line; and pull-down means, responsive to receipt of a low voltage signal from the slow-rise /fast-fall inverter means, for pulling down a voltage on the signal output line; and wherein said fast-rise /slow-fall inverter means switches a signal from a low voltage level to a high voltage level faster than said slow-rise /fast-fall inverter means switches a signal from the low voltage level to the high voltage level and wherein said slow-rise /fast-fall inverter means switches a signal from a high voltage level to
  • CMOS buffer of claim 1 wherein said pull-up means is a PMOS device having a source connected to a voltage source, a drain connected to the output signal line, and a gate connected to an output of the fast-rise /slow-fall inverter means; and wherein said pull-down means is an NMOS device having a source connected to a ground, a drain connected to the output signal line, and a gate connected to an output of the slow-rise /fast-fall inverter means.
  • CMOS buffer of claim 1 wherein said fast-rise /slow- fall inverter means is configured to pull up a voltage at its output at a first rate in response to a transition of a first type in a signal asserted at its input and to pull down the voltage at its output at a second rate in response to a transition of a second type in the signal asserted at its input; wherein said slow-rise /fast-fall inverter is configured to pull up a voltage at its output at a third rate in response to the transition of the first type in the signal asserted at its input and to pull down the voltage at its output inverter at a fourth rate in response to the transition of the second type in the signal asserted at its input; and wherein the first rate is faster than the third rate and wherein the fourth rate is faster than the second rate.
  • CMOS buffer of claim 3 wherein the transition of the first type is a signal transition from a low voltage level to a high voltage level and the transition of the second type is a signal transition from the low voltage level to the high voltage level.
  • CMOS buffer of claim 3 wherein the first rate is substantially the same as the fourth rate and wherein the second rate is substantially the same as the third rate.
  • CMOS buffer of claim 3 wherein said fast-rise /slow-fall inverter means includes a pull-up device and a pull-down device and said slow-rise /fast- fall inverter means includes a pull-up device and a pull-down device; wherein said pull-up device of said fast-rise /slow-fall inverter means has a larger width than a width of the pull-up device of slow-rise /fast-fall inverter means; and wherein said pull-down device of said fast-rise /slow-fall inverter means has a smaller width than a width of the pull-down device of slow-rise /fast- fall inverter means.
  • CMOS buffer of claim 1 further comprising first additional means for inverting connected between the signal input line and inputs of said fast-rise /slow-fall inverter means and said slow-rise /fast-fall inverter means.
  • CMOS buffer of claim 7 further comprising: second additional means for inverting having an input connected to a tri- state control line; NAND means for performing a NAND operation on a pair of input signals, said NAND means connected between said first additional means for inverting and said slow-rise /fast-fall inverter means, said NAND means having a first input connected to an output of said first additional means for inverting, a second input connected to an output of said second additional means for inverting, and an output connected to an input of said slow-rise /fast-fall inverter means; and
  • NOR means for performing a NOR operation on a pair of input signals, said NOR means connected between said first additional means for inverting and said fast-rise /slow-fall inverter means, said NOR means having a first input connected to an output of said first additional means for inverting, a second input connected to said tri-state control line, and an output connected to an input of said fast-rise /slow-fall inverter means.
  • a CMOS buffer interconnecting a signal input line and a signal output line, said CMOS buffer comprising: a fast-rise /slow-fall inverter and a slow-rise /fast-fall inverter both having inputs connected the signal input line; and a pull-up device and a pull-down device both connected in series between a voltage source and a ground, said pull-up device having a gate connected to an output of said fast-rise /slow-fall inverter and a drain connected to the signal output line, said pull-down device having a gate connected to an output of said slow-rise /fast-fall inverter and a drain connected to the signal output line.
  • CMOS buffer of claim 9 wherein said fast-rise /slow-fall inverter is configured to pull up a voltage at the output of the fast-rise /slow-fall inverter at a first rate in response to a transition of a first type in a signal input to the fast-rise /slow-fall inverter and to pull down the voltage at the output of the fast-rise /slow-fall inverter at a second rate in response to a transition of a second type in the signal input to the fast-rise /slow-fall inverter; wherein said slow-rise /fast-fall inverter is configured to pull up a voltage at the output of the slow-rise /fast-fall inverter at a third rate in response to the transition of the first type in the signal input to the slow- rise /fast-fall inverter and to pull down the voltage at the output of the slow- rise /fast-fall inverter at a fourth rate in response to the transition of the second type in the input signal; and wherein
  • CMOS buffer of claim 10 wherein the transition of the first type is a signal transition from a low voltage level to a high voltage level and the transition of the second type is a signal transition from the low voltage level to the high voltage level.
  • CMOS buffer of claim 10 wherein the first rate is substantially the same as the fourth rate and wherein the second rate is substantially the same as the third rate.
  • CMOS buffer of claim 10 wherein said fast-rise /slow-fall inverter includes a pull-up device and a pull-down device and said slow-rise /fast-fall inverter includes a pull-up device and a pull-down device; wherein said pull-up device of said fast-rise /slow-fall inverter has a larger width than a width of the pull-up device of said slow-rise /fast-fall inverter; and wherein said pull-down device of said fast-rise /slow-fall inverter has a smaller width than a width of the pull-down device of said slow-rise /fast-fall inverter.
  • CMOS buffer of claim 10 further comprising a first inverter connected between the signal input line and said inputs of said fast-rise /slow- fall inverter and said slow-rise /fast-fall inverter.
  • CMOS buffer of claim 14 further comprising: a second inverter having an input connected to a tri-state control line; a NAND-gate connected between said first inverter and said slow- rise /fast-fall inverter, said NAND-gate having a first input connected to an output of said first inverter, a second input connected to an output of said second inverter, and an output connected to an input of said slow-rise /fast-fall inverter; and a NOR-gate connected between said first inverter and said fast- rise /slow-fall inverter, said NOR-gate having a first input connected to an output of said first inverter, a second input connected to the tri-state control line, and an output connected to an input of said fast-rise /slow-fall inverter.
  • a method for buffering a signal between a signal input line and a signal output line comprising the steps of: applying an input signal to a fast-rise /slow-fall inverter; applying the input signal to a slow-rise /fast-fall inverter; and applying an output of the fast-rise /slow- fall inverter to a gate of a pull- up device and applying an output of the slow-rise /fast-fall inverter to a gate of a pull-down device, said pull-up device having a source connected to a voltage source and having a drain connected to the signal output line, said pull-down device having a source connected to a ground and having a drain connected to the signal output line; wherein said fast-rise /slow-fall inverter switches a signal from a low voltage level to a high voltage level faster than said slow-rise /fast-fall inverter switches a signal from the low voltage level to the high voltage level and wherein said slow-rise /fast-fall inverter switches
  • CMOS buffer of claim 16 wherein said fast-rise /slow- fall inverter pulls up a voltage at the output of the fast-rise /slow-fall inverter at a first rate in response to a transition of a first type in a signal input to the fast-rise /slow-fall inverter and pulls down the voltage at the output of the fast-rise /slow-fall inverter at a second rate in response to a transition of a second type in the signal input to the fast- rise /slow-fall inverter; wherein said slow-rise /fast-fall inverter pulls up a voltage at the output of the slow-rise /fast-fall inverter at a third rate in response to the transition of the first type in the signal input to the slow-rise /fast-fall inverter and pulls down the voltage at the output of the slow-rise /fast-fall inverter at a fourth rate in response to the transition of the second type in the input signal; and wherein the first rate is
  • CMOS buffer of claim 17 wherein the transition of the first type is a signal transition from a low voltage level to a high voltage level and the transition of the second type is a signal transition from the low voltage level to the high voltage level.
  • the CMOS buffer of claim 17 wherein the first rate is substantially the same as the fourth rate and wherein the second rate is substantially the same as the third rate. 20. The CMOS buffer of claim 17 further comprising the initial step of routing the input signal from the signal input line through a first inverter connected between the signal input line and said inputs of said fast-rise /slow- fall inverter and said slow-rise /fast-fall inverter.
  • CMOS buffer of claim 20 further comprising the steps of: routing a tri-state control signal through a second inverter; routing an output of the first inverter and the second inverter through a NAND-gate then into the input of said slow-rise /fast-fall inverter; and routing an output of the first inverter and the tri-state control signal through a NOR-gate then into the fast-rise /slow-fall inverter.
  • a tri-stateable CMOS buffer interconnecting a signal input line, a tri-state control line and a signal output line, said tri-stateable CMOS buffer comprising: input stage means for receiving signals from the signal input line and the tri-state control line and for generating first and second intermediate signals; pull-up means for receiving the first intermediate signal and for pulling up a voltage on the signal output line in response to a transition to a high voltage within the first intermediate signal; and pull-down means for receiving the second intermediate signal and for pulling down a voltage on the signal output line in response to a transition to a low voltage within the second intermediate signal; and wherein said input stage means outputs the signal received on the input line as both the first and second intermediate signals if the tri-state control line is in a first state and wherein said input stage means outputs a constant signal as both the first and second intermediate signals if the tri-state control line is in a second state regardless of signals received on the input line.
  • the tri-stateable CMOS buffer of claim 22 wherein said input stage means comprises a first means for inverting a signal received from the signal input line; a second means for inverting a signal received from the tri-state control line; NAND means for performing a NAND operation on a pair of input signals, said NAND means having a first input connected to an output of said first means for inverting, a second input connected to an output of said second means for inverting; NOR means for performing a NOR operation on a pair of input signals, said NOR means having a first input connected to an output of said second means for inverting, a second input connected to an output of said first means for inverting a third means for inverting having an input connected to an output of said NOR-gate; and a fourth means for inverting having an input connected to an output of said NAND-gate; with said third means for inverting outputs the first intermediate signal and the fourth means for inverting outputs the second intermediate signal.
  • CMOS buffer of claim 24 wherein said fast-rise /slow-fall inverter is configured to pull up a voltage at the output of the fast-rise /slow- fall inverter at a first rate in response to a transition of a first type in a signal input to the fast-rise /slow-fall inverter and to pull down the voltage at the output of the fast-rise /slow-fall inverter at a second rate in response to a transition of a second type in the signal input to the fast-rise /slow-fall inverter; wherein said slow-rise /fast-fall inverter is configured to pull up a voltage at the output of the slow-rise /fast- fall inverter at a third rate in response to the transition of the first type in the signal input to the slow- rise /fast-fall inverter and to pull down the voltage at the output of the slow- rise /fast-fall inverter at a fourth rate in response to the transition of the second type in the input signal; and where
  • CMOS buffer of claim 25 wherein the transition of the first type is a signal transition from a low voltage level to a high voltage level and the transition of the second type is a signal transition from the low voltage level to the high voltage level.
  • CMOS buffer of claim 25 wherein the first rate is substantially the same as the fourth rate and wherein the second rate is substantially the same as the third rate.
  • the tri-stateable CMOS buffer of claim 23 wherein said fast-rise /slow- fall inverter includes a pull-up device and a pull-down device and said slow-rise /fast-fall inverter includes a pull-up device and a pull-down device; wherein said pull-up device of said fast-rise /slow-fall inverter has a larger width than a width of the pull-up device of slow-rise /fast-fall inverter; and wherein said pull-down device of said fast- rise/ slow-fall inverter has a smaller width than a width of the pull-down device of slow-rise /fast-fall inverter.
  • a tri-stateable CMOS buffer interconnecting a signal input line and a signal output line, said tri-stateable CMOS buffer comprising: a first inverter having an input connected to a signal input line; a second inverter having an input connected to a tri-state control line; a NAND-gate having a first input connected to an output of said first inverter and having a second input connected to an output of said second inverter; a NOR-gate having a first input connected to an output of said first inverter and having a second input connected to the tri-state control line; a third inverter having an input connected to an output of said NOR- gate; a fourth inverter having an input connected to an output of said NAND- gate; and a pull-up device and a pull-down device connected in series between a voltage source and a ground, said pull-up device having a gate connected to an output of said third inverter and a drain connected to the signal output line, said pull-down device having a gate connected
  • CMOS buffer of claim 30 wherein said fast-rise /slow-fall inverter is configured to pull up a voltage at the output of the fast-rise /slow-fall inverter at a first rate in response to a transition of a first type in a signal input to the fast-rise /slow-fall inverter and to pull down the voltage at the output of the fast-rise /slow-fall inverter at a second rate in response to a transition of a second type in the signal input to the fast-rise /slow-fall inverter; wherein said slow-rise /fast-fall inverter is configured to pull up a voltage at the output of the slow-rise /fast-fall inverter at a third rate in response to the transition of the first type in the signal input to the slow- rise /fast-fall inverter and to pull down the voltage at the output of the slow- rise /fast-fall inverter at a fourth rate in response to the transition of the second type in the input signal; and where
  • CMOS buffer of claim 31 wherein the transition of the first type is a signal transition from a low voltage level to a high voltage level and the transition of the second type is a signal transition from the low voltage level to the high voltage level.
  • CMOS buffer of claim 31 wherein the first rate is substantially the same as the fourth rate and wherein the second rate is substantially the same as the third rate.
  • CMOS buffer of claim 29 wherein said fast-rise /slow-fall inverter includes a pull-up device and a pull-down device and said slow-rise /fast-fall inverter includes a pull-up device and a pull-down device; wherein said pull-up device of said fast-rise /slow-fall inverter has a larger width than a width of the pull-up device of slow-rise /fast-fall inverter; and wherein said pull-down device of said fast-rise /slow-fall inverter has a smaller width than a width of the pull-down device of slow-rise /fast-fall inverter.
  • the invention generally relates to integrated circuits and in particular to complimentary metal-oxide-semiconductor (CMOS) output buffers for use therein.
  • CMOS complimentary metal-oxide-semiconductor
  • FIG. 1 illustrates a simple CMOS output buffer 10.
  • Output buffer 10 includes a pull-up or PMOS transistor 12 and a pull-down or NMOS transistor 14 connected in series between a voltage source and a ground. Gates of devices 12 and 14 are both connected to an input line. Drains of devices 12 and 14 are both connected to an output line.
  • pull-up device 12 turns on and pulldown device 14 turns off resulting in the output line being pulled up to the high voltage level.
  • pull-up device 12 turns off and pull-down device 14 turns on thereby pulling the voltage on the output line down to the ground voltage.
  • logic signals asserted on the input line are output to the output line.
  • the pull-up device and the pull-down device are both on resulting in a "shoot through” current or “cross bar” current flowing between the voltage source and the ground.
  • the shoot through current causes the integrated circuit incorporating the output buffer to consume more current than would otherwise be desirable and such can be a significant problem, particularly for integrated circuits employing numerous output buffers used in portable devices such as cellular telephones and the like. Accordingly, it would be desirable to provide an output buffer which substantially reduces shoot through current and certain aspects of the present invention are directed to that end.
  • FIG. 2 illustrates a CMOS tri-stateable output buffer 16 having a pair of pull-up devices 18 and 20 and a pair of pull-down devices 22 and 24 all connected series between a voltage source and a ground. Gates of devices 20 and 22 are connected to an input line and drains of devices 20 and 22 are connected to an output line.
  • Pull- up device 18 is connected between a source of device 20 and the voltage source.
  • Pull-down device 24 is connected between a source of pull-down device 22 and the ground.
  • a gate of device 18 is connected to a tri-state control input line.
  • a gate of device 24 is connected through an inverter 26 to the tri-state control input line.
  • Pull-up device 20 is sized to be significantly larger than pull-down device 22.
  • devices 18 and 20 may both have a width/length ratio (W) of X/l and devices 22 and 24 may both have a width /length ratio (W) of Y/l.
  • the values of X and Y are four times greater than those values associated with a non-tri-stateable inverter with the same output drive capability.
  • the tri-stage enabling line is set to logic low, devices 18 and 24 are switched on and, particularly as a result of the relatively large size of devices 18 and 24, thereby causing devices 20 and 22 to operate in the same manner as the output buffer of FIG. 1 for outputting signals to the output line.
  • the tri-state control line is set to logic high, devices 18 and 24 are both switched off.
  • changes in the logic level of the input line do not affect the logic level of the output line.
  • signals asserted on the input line are not output to the output line. Instead the output line floats with respect to the input line.
  • the tri-state buffer of FIG. 2 may be used in connection with a shared output line, such as a bus line. Problems, however, also arise when using the tri-stateable buffer of FIG.
  • the tri-stateable output buffer of FIG. 2 requires a substantially larger amount of circuit area than the output buffer of FIG. 1.
  • the larger amount of area is required particularly because device 18 and 24 must be physically large to ensure that, when the tri-state control line is set to a logic low level, device 18 and 24 allows the output to reach the proper logic level for logic state 1 and logic state 0 at the output of devices 20 and 22. Accordingly, it would be desirable to provide a tri-stateable output buffer which both reduces shoot- through current and which consumes relatively little circuit area and it is to these ends that aspects of the invention are also drawn.
  • a CMOS buffer which interconnects a signal input line and a signal output line.
  • the CMOS buffer comprises fast-rise /slow-fall inverter means for inverting a signal received from the signal input line; slow-rise /fast-fall inverter means also for inverting the signal received from the signal input line; pull-up means, responsive to receipt of a high voltage signal from the fast-rise /slow-fall means, for pulling up a voltage on the signal output line; and pull-down means, responsive to receipt of a low voltage signal from the slow-rise /fast-fall inverter means, for pulling down a voltage on the signal output line.
  • the fast-rise /slow- fall inverter means switches a signal from a low voltage level to a high voltage level faster than the slow-rise /fast-fall inverter means switches a signal from the low voltage level to the high voltage level.
  • the slow-rise /fast- fall inverter means switches a signal from a high voltage level to a low voltage level faster than the fast-rise /slow-fall inverter means switches a signal from the high voltage level to the low voltage level.
  • the pull-up and pull-down devices are separately gated and are turned on or off at slightly different times. Hence, shoot though current conducted from the voltage source to the ground through the pull-up and pull-down devices is reduced over buffers wherein the pull-up and pull-down devices are turned on or off at the same time.
  • the pull- up means is a PMOS device having a source connected to a voltage source, a drain connected to the output signal line, and a gate connected to an output of fast-rise /slow-fall inverter means.
  • the pull-down means is an NMOS device having a source connected to a ground, a drain connected to the output signal line, and a gate connected to an output of slow-rise /fast- fall inverter means.
  • the fast-rise /slow-fall inverter means is configured to pull up a voltage at its output at a first rate in response to a transition of a first type in a signal asserted at its input and to pull down the voltage at its output at a second rate in response to a transition of a second type in the signal asserted at its input.
  • the slow-rise /fast-fall inverter is configured to pull up a voltage at its output at a third rate in response to the transition of the first type in the signal asserted at its input and to pull down the voltage at its output at a fourth rate in response to the transition of the second type in the signal asserted at its input.
  • the first rate is faster than the third rate and the fourth rate is faster than the second rate.
  • the fast-rise /slow-fall inverter means includes a pull-up device and a pull-down device and the slow-rise /fast- fall inverter means includes a pull-up device and a pull-down device.
  • the pull- up device of the fast-rise /slow- fall inverter means has a larger width than that of the pull-up device of slow-rise /fast-fall inverter means.
  • the pull-down device of the fast-rise /slow-fall inverter means has a smaller width than that of the pull-down device of slow-rise /fast-fall inverter means.
  • a tri-stateable CMOS buffer which interconnects a signal input line and a tri-state control line to a signal output line.
  • the tri-stateable CMOS buffer comprises input stage means for receiving signals from the signal input line and the tri- state control line and for generating first and second intermediate signals.
  • the tri-stateable CMOS buffer also comprises pull-up means for receiving the first intermediate signal and for pulling up a voltage on the signal output line in response to a transition to a high voltage within the first intermediate signal and pull-down means for receiving the second intermediate signal and for pulling down a voltage on the signal output line in response to a transition to a low voltage within the second intermediate signal.
  • the input stage means is configured to output the signal received on the input line as both the first and second intermediate signals if the tri-state control line is in a first state and wherein the input stage means outputs a constant signal as both the first and second intermediate signals if the tri-state control line is in a second state regardless of signals received on the input line.
  • the pull-up and pull-down devices are also separately gated and are turned on or off in response to signals received on the input signal line only if an appropriate signal is received on the tri-state line.
  • the input stage permits the output buffer to be tri-stateable though using relatively small pull-up and pull-down devices thereby reducing overall circuit area.
  • the input stage means includes a first means for inverting a signal received from a signal input line; a second means for inverting a signal received from a tri-state control line; NAND means for performing a NAND operation on a pair of input signals, and NOR means for performing a NOR operation on a pair of input signals.
  • the NAND means has a first input connected to an output of the first means for inverting, a second input connected to an output of the second means for inverting.
  • the NOR means has a first input connected to an output of the second means for inverting, a second input connected to an output of the first means for inverting.
  • the input stage means also comprises third means for inverting having an input connected to an output of the NOR-gate and fourth means for inverting having an input connected to an output of the NAND-gate.
  • the first intermediate signal is output by the third means for inverting and the second intermediate signal is output by the fourth means for inverting.
  • the third means for inverting is a fast- rise /slow-fall inverter and the fourth means for inverting is a slow-rise /fast-fall inverter. Hence, shoot though current is also reduced.
  • FIG. 1 illustrates a conventional output buffer.
  • FIG. 2 illustrates a conventional tri-stateable output buffer.
  • FIG. 3 illustrates an output buffer configured in accordance with a first exemplary embodiment of the invention wherein a fast-rise /slow-fall inverter and a slow-rise /fast-fall inverter are employed to reduce shoot through current.
  • FIG. 4 is a timing diagram illustrating signals generated by the inverters of FIG. 3.
  • FIG. 5 illustrates a tri-stateable output buffer configured in accordance with a second exemplary embodiment of the invention wherein a combinatorial logic input stage is provided to allow the use of relatively small devices within an output stage of the output buffer to thereby reduce the overall size of the output buffer.
  • FIG. 6 illustrates a tri-stateable output buffer configured in accordance with a third exemplary embodiment of the invention which employs both the fast-rise /slow-fall and slow-rise /fast-fall inverters of FIG. 3 and the combinatorial logic input stage of FIG. 5 to achieve both reduced shoot through current and reduced size.
  • FIG. 7 illustrates a particular implementation of the tri-stateable output buffer of FIG. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIG. 3 illustrates an output buffer 110 having pull-up PMOS device 112 and a pull-down NMOS device 114 connected in series between a voltage source and a ground. Drains of devices 112 and 114 are connected to a common output line 115. A gate of a device 112 is connected through a fast-rise /slow- fall inverter 116 to an input line 118. A gate of pull-down device 114 is connected through a slow-rise /fast-fall inverter 120 to input line 118. An inverter 122, which may be conventional, is provided along input line 118 for initially inverting an input signal. Hence, a pair of inverters are provided on the signal paths leading to the gates of both of devices 112 and 114.
  • the output buffer of FIG. 3 operates logically in the same manner as the output buffer of FIG. 1. Namely, in response to a transition from a low logic level to a high logic level in a signal asserted on input line 118, device 112 pulls up output line 115 to a high logic level. Likewise, in response to a transition from a high logic level to a low logic level in the signal asserted on input line 118, device 114 pulls down output line 115 to a low logic level.
  • Fast-rise /slow-fall inverter 116 is configured to generate an output signal which transitions from a low voltage level to a high voltage level very rapidly in response to a sharp falling edge in a signal asserted at its input. Inverter 116 is also configured to generate an output signal which transitions relatively slowly from a high logic level to a low logic level in response to a sharp rising edge in the signal asserted at its input.
  • slow-rise /fast-fall inverter 120 is configured to generate an output signal which transitions relatively slowly from a low logic level to a high logic level in response to a sharp falling edge. Also, inverter 120 is configured to generate an output signal which transitions relatively quickly from a high logic level to a low logic level in response to a sharp rising edge.
  • FIG. 4 provides timing diagrams illustrating the operation of inverters 116 and 120.
  • a first timing diagram 124 illustrates a signal input to both inverter 116 and inverter 120.
  • Timing diagram 126 illustrates the response of inverter 116 to input signal 124 and timing diagram 128 illustrates the response of inverter 120 to input signal 124.
  • inverter 116 responds very quickly to a sharp falling edge in input signal 124 and responds relatively slowly to a sharp rising edge in the input signal 124.
  • inverter 120 responds relatively slowly to the sharp falling edge of input signal 124 but responds relatively quickly to the sharp rising edge in input signal 124.
  • devices 112 and 114 are turned on or off at slightly different times. More specifically, pull-up device 112 is turned OFF slightly before pull-down device 114 is turned ON. Conversely, pull-up device 112 is turned ON slightly after pull-down device 114 is turned OFF. Because the turn on and turn off times of the pull-up and pull-down devices are slightly offset from one another, there is very little time during which both device 112 and device 114 are on. Hence, there is very little time during which current shoots through devices 112 and 114 from the voltage source to the ground. Hence, shoot through current is substantially reduced as compared to that of the conventional input buffer of FIG. 1.
  • Inverter 116 is configured to provide a faster-rise than that of inverter 120 by incorporating an internal pull-up device (not shown in FIG. 3) which has a substantially larger width than that of an internal pull-up device (also not shown in FIG. 3) incorporated within inverter 120.
  • inverter 116 is configured to provide a slower-fall than that of inverter 120 by incorporating an internal pull-down device (not shown in FIG. 3) which has a substantially smaller width than that of an internal pull-down device (also not shown in FIG. 3) incorporated within inverter 120.
  • the pull-up device of inverter 116 has a size of 24/0.
  • the pull-up device of inverter 120 has a size of only 3.6/0.6.
  • the pull- down device of inverter 116 has a size of 3.6/0.6 whereas the pull-down device of inverter 120 has a size of a 24/0.6.
  • CMOS output buffer configured, in part, to reduce shoot through current over conventional implementations.
  • FIG. 5 a tri-stateable CMOS output buffer is described which reduces circuit area over conventional implementations.
  • FIG. 5 illustrates a tri-stateable output buffer 210 having pull-up PMOS device 212 and a pull-down NMOS device 214 connected in series between a voltage source and a ground. Drains of devices 212 and 214 are connected to a common output line 215. A gate of a device 212 is connected through an inverter 216 and through a combinatorial logic input stage 217 to an input line 218 and to a tri-state control line 219. A gate of pull-down device 214 is connected through an inverter 220 and through combinatorial logic input stage 217 to input line 218 and to tri-state control line 219. Inverters 216 and 220 may be entirely conventional.
  • Input stage 217 includes a NOR-gate 222, a NAND-gate 224 and a pair of inverters 226 and 228.
  • Input stage 217 is configured, as shown, with a first input of NOR-gate 222 connected through inverter 226 to input line 218, a second input of NOR-gate 222 connected directly to tri-state input line 219, a first input of an NAND-gate 224 connected through inverter 226 to input line 218, and a second input of NAND-gate 224 connected through inverter 228 to tri-state input line 219.
  • the tri-stateable input buffer of FIG. 5 operates logically in the same manner as the tri-stateable output buffer of FIG. 2.
  • Inverters 216 and 220 act to invert the input signals as applied to inverters 216 and 220. Inverters 216 and 220 re-invert the logic values to be the same as those asserted on input line 218. Hence, devices 212 and 214 effectively see only the input signal of line 218 when the tri-state control signal is low and thereby operate as an otherwise conventional output buffer.
  • the tri-stateable output buffer of FIG. 5 logically operates in the same manner as the tri-stateable output buffer of FIG. 2.
  • additional pull-up and pull-down devices (such as devices 18 and 24 of FIG. 2) are no longer required for connecting in series with devices 212 and 214.
  • device 18 and 24 must be fairly large thereby requiring a relatively large amount of circuit area to implement the output buffer of FIG. 2.
  • the implementation of FIG. 5 because additional pull-up and pull-down devices are not required in series with devices 212 and 214, the overall amount of circuit area is reduced.
  • FIG. 6 illustrates a tri-stateable output buffer similar to that of FIG. 5 but which additionally employs a fast-rise /slow-fall inverter and a slow-rise /fast- fall inverter between the input stage and the pull-up and pull-down devices.
  • shoot through current is also reduced as compared to the tri-stateable input buffer of FIG. 2.
  • the implementation of FIG. 6 is similar to that of FIG. 5 and only pertinent differences will be described.
  • Like reference numerals are employed to represent like elements, incremented by one hundred.
  • FIG. 6 illustrates a tri-stateable output buffer 310 having a pull- up PMOS device 312 and a pull-down NMOS device 314 connected in series between a voltage source and a ground. Drains of devices 312 and 314 are connected to a common output line 315. A gate of a device 312 is connected through a fast-rise /slow-fall inverter 330, another inverter 316 and a combinatorial logic input stage 317 to both an input line 318 and a tri-state control line 319.
  • a gate of pull-down device 314 is connected through a slow- rise /fast-fall inverter 332, another inverter 320 and combinatorial logic input stage 317 to both input line 318 and tri-state control line 319.
  • Inverters 316 and 320 may be entirely conventional. However, fast-rise /slow-fall inverter 330 and slow-rise /fast-fall inverter 332 are configured as described above in connection with FIGS. 3 and 4 to reduce shoot through current through devices 312 and 314. Similar to the embodiment of FIG. 5, input stage 317 of FIG. 6 includes a
  • NOR-gate 322 a NAND-gate 324 and a pair of inverters 326 and 328.
  • inverter 320 is connected to NOR-gate 322 rather than to NAND-gate 324.
  • inverter 316 is connected to NAND-gate 324 rather than to NOR-gate 322. Additional inverters may be provided between the input stage and the fast- rise/ slow-fall and slow-rise /fast-fall inverters as needed to provide a cascade effect.
  • the tri-stateable output buffer operates logically in the same manner as the tri-stateable output buffer of FIG. 5.
  • shoot through current is reduced and, although the overall circuit area is increased somewhat as compared to that of FIG. 5, circuit size is still reduced as compared to the tri-stateable output buffer of FIG. 2.
  • FIG. 7 illustrates a particular configuration of the output buffer of FIG. 6 specifically showing internal devices which may be employed to form the various inverters, the NAND-gate and the NOR-gate.
  • devices 401 and 402 form inverter 328 and devices 403 and 404 form inverter 326.
  • Devices 405, 406, 407 and 408 form NAND-gate 324.
  • Devices 409, 410, 411 and 412 form NOR-gate 322.
  • Devices 413 and 414 form inverter 316 and devices 415 and 416 form inverter 320.
  • Devices 417 and 418 form fast-rise /slow- fall inverter 330 and devices 419 and 420 form slow-RISE/fast-FALL inverter 332.
  • Devices 421 and 422 correspond to pull-up and pull-down devices 312 and 314, respectively.
  • Table I provides exemplary device sizes for each of the devices of FIG. 7.
  • pull-up device 415 of the fast-rise /slow- fall inverter is substantially larger than pull-down device 418 of the slow-fall /fast-rise inverter thereby ensuring that the fast-rise /slow-fall inverter turns on pull-up device 421 faster than the slow-fall /fast-fall inverter turns off pull-down device 422 to reduce shoot through current on rising edges of an input signal.
  • pulldown device 416 of the fast-rise /slow-fall inverter is substantially smaller than pull-up device 419 of the slow-fall /fast-rise inverter thereby ensuring that the slow-fall /fast-fall inverter turns on pull-down device 422 faster than the fast- rise /slow-fall inverter turns off pull-up device 421 to reduce shoot through current on falling edges of an input signal.

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Abstract

Ce tampon de sortie (10) en technologie CMOS comporte un dispositif de liste directe (112) et un dispositif de liste refoulée (114) qui sont montés en série entre une source de tension et une masse. Un inverseur à montée rapide et chute lente (116) est monté entre une ligne d'entrée (118) et une porte du dispositif de liste directe (112). Par contre, un inverseur à montée lente et chute rapide (120) est monté entre la ligne d'entrée et une porte du dispositif de liste refoulée (114). L'inverseur à montée rapide et chute lente (116) commute de bas à haut le niveau de tension d'un signal plus rapidement que l'inverseur à montée lente et chute rapide (120) ne commute de haut à bas le niveau de tension du signal.
PCT/US1999/011485 1998-05-29 1999-05-24 Tampon de sortie numerique en technologie cmos, a portes separees pour les listes directes et les listes refoulees WO1999063667A1 (fr)

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Publication number Priority date Publication date Assignee Title
EP1280276A3 (fr) * 2001-07-26 2003-07-09 Infineon Technologies AG Dispositif et méthode pour la commutation de transistors
DE10224987A1 (de) * 2002-06-05 2004-01-08 Infineon Technologies Ag Ausgangstreiber und Ansteuerung für Drain-gekoppelte komplementäre Ausgangstransistoren eines Ausgangstreibers
JP2015119481A (ja) * 2013-12-16 2015-06-25 スンシル ユニバーシティー リサーチ コンソルティウム テクノーパークＳｏｏｎｇｓｉｌ Ｕｎｉｖｅｒｓｉｔｙ Ｒｅｓｅａｒｃｈ Ｃｏｎｓｏｒｔｉｕｍ Ｔｅｃｈｎｏ−Ｐａｒｋ 貫通電流制御のためのインバータチェーン回路
JP2017028370A (ja) * 2015-07-16 2017-02-02 ローム株式会社 ドライバ回路及びそれを備えたデジタルアンプ

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JPH03258115A (ja) * 1990-03-08 1991-11-18 Matsushita Electric Ind Co Ltd インバータ回路装置
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EP0251910A2 (fr) * 1986-06-25 1988-01-07 Fujitsu Limited Circuit tampon de sortie CMOS
JPS63301622A (ja) * 1987-06-01 1988-12-08 Fuji Electric Co Ltd 三状態回路
JPH03258115A (ja) * 1990-03-08 1991-11-18 Matsushita Electric Ind Co Ltd インバータ回路装置
US5315173A (en) * 1991-07-19 1994-05-24 Samsung Electronics Co., Ltd. Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1280276A3 (fr) * 2001-07-26 2003-07-09 Infineon Technologies AG Dispositif et méthode pour la commutation de transistors
US6750697B2 (en) 2001-07-26 2004-06-15 Infineon Technologies Ag Configuration and method for switching transistors
DE10224987A1 (de) * 2002-06-05 2004-01-08 Infineon Technologies Ag Ausgangstreiber und Ansteuerung für Drain-gekoppelte komplementäre Ausgangstransistoren eines Ausgangstreibers
DE10224987B4 (de) * 2002-06-05 2004-05-13 Infineon Technologies Ag Ausgangstreiber und Ansteuerschaltung für Drain-gekoppelte komplementäre Ausgangstransistoren einer Ausgangstreiberschaltung
JP2015119481A (ja) * 2013-12-16 2015-06-25 スンシル ユニバーシティー リサーチ コンソルティウム テクノーパークＳｏｏｎｇｓｉｌ Ｕｎｉｖｅｒｓｉｔｙ Ｒｅｓｅａｒｃｈ Ｃｏｎｓｏｒｔｉｕｍ Ｔｅｃｈｎｏ−Ｐａｒｋ 貫通電流制御のためのインバータチェーン回路
JP2017028370A (ja) * 2015-07-16 2017-02-02 ローム株式会社 ドライバ回路及びそれを備えたデジタルアンプ

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