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WO1998039847A1 - Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large - Google Patents

Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large Download PDF

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Publication number
WO1998039847A1
WO1998039847A1 PCT/US1998/004178 US9804178W WO9839847A1 WO 1998039847 A1 WO1998039847 A1 WO 1998039847A1 US 9804178 W US9804178 W US 9804178W WO 9839847 A1 WO9839847 A1 WO 9839847A1
Authority
WO
WIPO (PCT)
Prior art keywords
frequency
phase
signal
error signal
locked loop
Prior art date
Application number
PCT/US1998/004178
Other languages
English (en)
Inventor
James Everitt
James Parker
Original Assignee
Level One Communications, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Level One Communications, Inc. filed Critical Level One Communications, Inc.
Priority to CA002283316A priority Critical patent/CA2283316C/fr
Priority to IL13170598A priority patent/IL131705A0/xx
Priority to AU65408/98A priority patent/AU6540898A/en
Priority to EP98911466A priority patent/EP0968568B1/fr
Priority to DE69830713T priority patent/DE69830713T2/de
Publication of WO1998039847A1 publication Critical patent/WO1998039847A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator

Definitions

  • the present invention relates generally to phase-locked loop circuits, and more particularly to a phase-locked loop circuit which exhibits a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within a wider, predetermined frequency range.
  • Fig. 1 illustrates a prior art phase-locked loop (PLL) 10 feedback circuit.
  • the PLL 10 is a feedback circuit that is often used to reduce an error term toward zero.
  • the error term is the phase difference between an input signal and a reference signal.
  • the basic component building blocks of a PLL are a phase comparator 12 and a voltage-controlled oscillator (VCO) 14.
  • the PLL incorporates the VCO 14 in the feedback loop.
  • a VCO is an oscillator whose output frequency is a function of its input voltage.
  • the phase comparator 12 compares the phase of the input signal on line 16 to the phase of the signal at the output of the VCO on line 18.
  • phase difference between these two signals is non-zero, the output frequency of the VCO 14 is adjusted in a manner which forces this difference down to zero.
  • the output signal on line 20 is fed back to the VCO 14 to provide a signal proportional to the phase difference between the signals on lines 16 and 18.
  • Phase-locked loops are also widely used in communication systems for coherent carrier tracking, and threshold extension, bit synchronization and symbol synchronization.
  • the PLLs as used in the data communications system of the present invention are used to lock to a receive signal and to subsequently provide the receive clock for that signal.
  • the PLL lock information generated from a data signal is poor, and is therefore not capable of pulling the PLL very far in frequency.
  • the frequency range of the PLL is wider than this narrow "capture" range.
  • the oscillation frequency of the PLL must somehow be brought close enough to the data signal frequency for the PLL to lock to the data signal. This can be done, as shown in Fig. 1, by first locking the PLL 10 to the frequency of a reference signal on line 22, which is close in frequency to the data signal on line 24. When the PLL 10 is locked to the reference signal on line 22, the input of the PLL 10 is switched over to the data signal on line 24.
  • phase-locked loop which has a wide frequency capture range for pulling the PLL within a predetermined frequency range, yet has a well-controlled and narrow frequency capture range for locking to the actual data signal, without the use of switching control circuitry such as control circuitry 26.
  • the present invention discloses a phase-locked loop that exhibits a tightly controlled capture range for locking an output signal to a data signal, while also providing a wide frequency capture range for initially pulling the output signal within a wider, predetermined frequency range.
  • the apparatus detects a frequency difference between at least one reference signal and a phase-locked loop (PLL) output signal, and generates a frequency error signal in response to the frequency difference.
  • a phase difference is detected between a received input signal and the PLL output signal, and a phase error signal is generated in response to this phase difference.
  • the frequency error signal and the phase error signal are combined, and this combined signal controls the frequency of the output signal.
  • the frequency error signal dominates the concurrently generated phase error signal when the frequency difference is outside of a predetermined frequency range. This dominating signal overdrives the phase error signal by increasing the amplitude of the frequency error signal.
  • a multiple-stage phase-locked loop has an inherently wide actual signal capture range and a narrow effective signal capture range.
  • the PLL includes a first detection mechanism for detecting first phase differences between reference signals and an output signal, and for generating a first phase error signal when the first phase differences fall outside of a predetermined frequency range.
  • the PLL further includes a second detection mechanism for detecting second phase differences between a received input signal and the output signal, and for generating a second phase error signal in response thereto.
  • a signal summing mechanism combines the first phase error signal and the second phase error signal, and allows the first phase error signal to overdrive the second phase error signal when both the first and second phase error signals are active.
  • the PLL also includes a voltage-controlled oscillator to control the frequency of the output signal in response to the first and second phase error signals.
  • a method for phase- locking an output signal to a data signal.
  • a frequency error signal is generated where a first frequency difference, measured by the frequency difference between a reference signal and the output signal, is outside of a predetermined frequency range.
  • a phase error signal is generated for a second frequency difference measured by the frequency difference between the data signal and the output signal. Where the first frequency difference is outside of the predetermined frequency range, the frequency error signal overdrives the phase error signal.
  • the frequency of the output signal is controlled with the phase error signal and the frequency error signal.
  • Fig. 1 illustrates a prior art phase-locked loop feedback circuit
  • Fig. 2 is a general block diagram of one embodiment of the phase-locked loop of the present invention.
  • Fig. 3 is a block diagram of a second order phase-locked loop of the present invention.
  • Fig. 4 is a block diagram of one embodiment of the frequency comparator
  • Fig. 5 is a general diagram of the transfer function of the frequency comparator; and Fig. 6 is a diagram of the transfer function of the frequency comparator with respect to the preferred reference signals.
  • Fig. 2 is a general block diagram of one embodiment of the invention.
  • the PLL 100 of Fig. 2 includes a frequency comparator 102 and a phase error detector 104 at the inputs of the PLL 100.
  • the frequency comparator 102 compares the frequency of one or more reference signals to the frequency of a signal to be controlled.
  • the signal to be controlled in Fig. 2 is the output signal, labeled F(CK) on line 106.
  • the F(CK) signal is fed back to the frequency comparator 102 via line 108 to be compared to one or more reference signals.
  • F(CENT) on line 110
  • F(REF) on line 112.
  • PLL 100 compares the frequency of the F(CK) signal on feedback line 108 to a combination of the reference signals on lines 110 and 112. The reference signal combination will be described in more detail in the ensuing description.
  • the purpose of the frequency comparator 102 is to provide a mechanism for pulling the output of the PLL 100 within a first frequency range from which the phase error detector 104 can then tightly lock to the input signal on line 114.
  • the frequency comparator 102 outputs a frequency error on line 116 that is proportional to the frequency difference between the combination of the reference signals on lines 110, 112, and the F(CK) signal on feedback line 108. Where the frequency of the F(CK) signal on feedback line 108 is greater than a combination of the reference signals F(CENT) and F(REF), a negative frequency error signal will be generated on line 116 to ultimately cause the VCO 118 to decrease the frequency of the F(CK) signal.
  • a positive frequency error signal will be generated on line 116 to ultimately cause the VCO 118 to increase the frequency of the F(CK) signal.
  • the frequency comparator 102 and the phase error detector 104 operate concurrently, however the frequency comparator 102 overrides the phase error detector 104 while the frequency error on line 116 is active.
  • the frequency error is active when the frequency difference, between the F(CK) signal on feedback line 108 and the combination of the reference signals F(CENT) and F(REF) on lines 110 and 112 respectively, is outside of a predetermined frequency range.
  • This predetermined frequency range is bounded by a cutoff frequency, F(cutoff), above or below the combined reference signal frequency.
  • F(cutoff) a cutoff frequency
  • the phase error on line 120 is recognized by the VCO 118, which then adjusts the output signal F(CK) on line 106 according to the frequency difference between the F(CK) signal on feedback line 108 and the input signal on line 114.
  • the frequency comparator 102 first pulls the PLL 100 output signal F(CK) on line 106 to a frequency range defined by the reference signals F(CENT) and F(REF) on lines 110 and 112 respectively. Then, when the F(CK) signal is within the predetermined frequency range, the phase error detector locks the PLL 100 output signal F(CK) to the input signal on line 114.
  • the frequency comparator 102 overrides the phase error detector 104 when the frequency comparator 102 is generating a frequency error signal on line 116.
  • the amplitude of the frequency comparator 102 output on line 116 is selected to be large enough to overdrive the phase error signal on line 120. Therefore, when the frequency difference between the F(CK) signal and the combination of the reference signals F(CENT) and F(REF) is outside of the predetermined frequency range, the frequency comparator 102 provides an amplified error signal which is recognized at the input of the VCO 118. When this frequency difference is within the predetermined frequency range, the amplified frequency error signal on line 116 is reduced to a near zero value, and the phase error detector 104 then provides the error signal to the input of the VCO 118.
  • the PLL 200 includes a circuit 202 for changing the order of the phase-locked loop.
  • the PLL 200 is similar to PLL 100 of Fig. 2, as it includes the frequency comparator 102, the phase error detector 104, the summing circuit 122 and the VCO 118.
  • PLL 200 is a second order phase-locked loop, as the circuit 202 includes an integrator 204 and a summing circuit 206. As will be appreciated by those skilled in the art, the inclusion of circuit 202 results in a transfer function having two poles, thereby providing a second-order PLL. Regardless of the order of the PLL, the resulting signal is inputted into the VCO 118 to control the frequency of the output signal F(CK) on line 106. The output signal F(CK) is also fed back into both the frequency comparator 102 and the phase error detector 104. This feedback provides the control signal necessary for the frequency comparator 102 and the phased error detector 104 to lock in on the frequency of the input signal on line 114. Any order PLL can be constructed using the teachings as herein disclosed without departing from the scope and spirit of the invention.
  • Fig. 4 is a general block diagram of one embodiment of the frequency comparator 102.
  • the preferred frequency comparator 102 is an up/down counter 300 with input signals F(CENT), F(REF) and F(CK) on lines 110, 112 and 114.
  • One possible implementation is a 16-bit counter having four outputs on lines 302, 304, 306 and 308.
  • the counter executes one count towards its center (i.e., it decrements the count if the count is greater than eight, and increments the count if the count is less than eight).
  • the positive edge of an F(CENT) pulse the counter executes one count towards its center (i.e., it decrements the count if the count is greater than eight, and increments the count if the count is less than eight).
  • F(REF) pulse the counter increments, and on the positive edge of an F(CK) pulse the counter decrements.
  • the frequency comparator 102 When the count is greater than 12, the frequency comparator 102 outputs a positive error signal proportional to the amount by which the count is greater than or equal to twelve (hexadecimal C). When the count is less than 4, the frequency comparator 102 outputs a negative error signal proportional to the amount by which the count is less than four.
  • the boundary logic 310 receives the count value on lines 302 through 308, and determines whether the count is less than four, between four and eleven, or greater than or equal to twelve. If the count is between four and eleven, the boundary logic 310 outputs a binary null value to ultimately generate a near zero frequency error signal on line 116. If the count is less than four, or greater than eleven, the boundary logic passes the value to a digital-to-analog (D/A) converter 312 that generates a proportional frequency error signal on line 116.
  • D/A digital-to-analog
  • the up/down counter 300 counts down and therefore produces a negative frequency error signal when F(CK)-F(REF) > F(CENT), which would indicate that the F(CK) signal is oscillating at a faster rate than the F(REF) and F(CENT) reference signal combination.
  • the up/down counter 300 counts up and therefore produces a positive frequency error signal when F(CK)-F(REF) ⁇
  • the up/down counter 300 counts toward the center and therefore produces zero output when
  • the frequency comparator 102 output i.e., the frequency error signal on line 116
  • a negative frequency error signal labeled -ERR
  • the -ERR signal is proportional to the amount by which the count is less than four.
  • the +ERR signal is proportional to the amount by which the count is greater than or equal to twelve. Where the count is between four and eleven, the frequency error signal, shown as ERR, is approximately equal to zero.
  • Fig. 5 is a diagram of the transfer function of the frequency comparator 102 of Fig. 4.
  • Fig. 5 illustrates the frequency error signal on line 116 as plotted against the frequency mismatch of the reference signals and the VCO 118 output.
  • no error signal is generated by the frequency comparator 102 within the predetermined frequency range 400. It is within this frequency range 400 that the frequency error on line 116 does not dominate the phase error signal on line 120, and the phase error signal allows the input signal on line 114 to be locked as the F(CK) signal on line 106.
  • the lower range of the frequency mismatch is shown in Fig.
  • the up/down counter 300 will decrement the count when the F(CK) signal is greater than the sum of the reference signals as shown in Equation 1 below.
  • the up/down counter 300 will increment the count when the F(CK) signal is less than the difference of the F(REF) and F(CENT) signals as shown in Equation 2 below.
  • a diagram of the transfer function of the frequency comparator 102 is shown having the frequency cutoff values as determined by
  • the -F(CUTOFF) frequency, shown at point 500 can be represented by F(REF)-F(CENT), as shown in Equation 2.
  • the +F(CUTOFF) frequency, shown at point 502 can be represented by F(REF)+F(CENT), as shown in Equation 1. Therefore, the capture range is set by controlling the frequencies of the F(REF) and F(CENT) signals. By using crystal controlled signals, this range can be tightly controlled.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

On décrit un circuit de boucle asservie en phase s'utilisant pour fournir une gamme d'accrochage strictement contrôlée pour asservir un signal de sortie sur un signal de données et pour fournir également une gamme d'accrochage étendue de fréquences pour déplacer au départ le signal de sortie dans une plage de fréquences prédéterminée plus vaste. L'appareil détecte une différence de fréquence entre au moins un signal de référence et un signal de sortie puis génère un signal d'erreur de fréquence en réponse à la différence de fréquence. Une différence de phase est détectée entre un signal d'entrée reçu et le signal de sortie puis un signal d'erreur de phase est généré en réponse à la différence de phase. Le signal d'erreur de fréquence et le signal d'erreur de phase sont combinés pour commander la fréquence du signal de sortie par la commande d'un oscillateur commandé en tension.
PCT/US1998/004178 1997-03-04 1998-03-04 Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large WO1998039847A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002283316A CA2283316C (fr) 1997-03-04 1998-03-04 Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large
IL13170598A IL131705A0 (en) 1997-03-04 1998-03-04 Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop
AU65408/98A AU6540898A (en) 1997-03-04 1998-03-04 Emulating narrow band phase-locked loop behavior on a wide band phase-locked loop
EP98911466A EP0968568B1 (fr) 1997-03-04 1998-03-04 Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large
DE69830713T DE69830713T2 (de) 1997-03-04 1998-03-04 Emulation des verhaltens eines schmalbandigen phasenregelkreises auf einem breitbandigen phasenregelkreis

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80773997A 1997-03-04 1997-03-04
US08/807,739 1997-03-04

Publications (1)

Publication Number Publication Date
WO1998039847A1 true WO1998039847A1 (fr) 1998-09-11

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PCT/US1998/004178 WO1998039847A1 (fr) 1997-03-04 1998-03-04 Comportement d'une boucle asservie en phase a bande etroite a effet d'emulation sur une boucle asservie en phase a bande large

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AU (1) AU6540898A (fr)
CA (1) CA2283316C (fr)
IL (1) IL131705A0 (fr)
WO (1) WO1998039847A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402113A2 (fr) * 1989-06-07 1990-12-12 International Business Machines Corporation Circuit de commande de fréquence pour VCO
WO1996017435A1 (fr) * 1994-11-28 1996-06-06 Curtin University Of Technology Boucle a phase asservie a frequence pilotee
US5525935A (en) * 1994-12-02 1996-06-11 Electronics And Telecommunications Research Institute High-speed bit synchronizer with multi-stage control structure
US5546433A (en) * 1995-03-21 1996-08-13 National Semiconductor Corporation Digital phase lock loop having frequency offset cancellation circuitry

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0402113A2 (fr) * 1989-06-07 1990-12-12 International Business Machines Corporation Circuit de commande de fréquence pour VCO
WO1996017435A1 (fr) * 1994-11-28 1996-06-06 Curtin University Of Technology Boucle a phase asservie a frequence pilotee
US5525935A (en) * 1994-12-02 1996-06-11 Electronics And Telecommunications Research Institute High-speed bit synchronizer with multi-stage control structure
US5546433A (en) * 1995-03-21 1996-08-13 National Semiconductor Corporation Digital phase lock loop having frequency offset cancellation circuitry

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AU6540898A (en) 1998-09-22
CA2283316C (fr) 2008-06-03
CA2283316A1 (fr) 1998-09-11
IL131705A0 (en) 2001-03-19

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