WO1998038680A1

WO1998038680A1 - Memory module

Info

Publication number: WO1998038680A1
Application number: PCT/JP1998/000717
Authority: WO
Inventors: Kouichi Ikeda
Original assignee: T.I.F. Co., Ltd.
Priority date: 1997-02-28
Filing date: 1998-02-23
Publication date: 1998-09-03

Abstract

A memory module wherein the wiring in a module board can be simplified. The memory module has a module board (2) mounted with four bare chips (1) for memory which have the same structure. On each of the bare chips (1) for memory, pads (3) are formed in a line in the longitudinal direction. At the center of the module board (2), pads (4) are formed in a line in the longitudinal direction. The bare chips (1) for memory are located on both sides of the line of the pads (4) of the module board (2), with two chips located on each side and disposed in the same direction. By this arrangement of the bare chips, the pads (3) on both sides of the module board (2) are arranged in the same order and the pads of the same order are arranged adjacently to each other. Therefore, when electrically connecting the pads (3) of the same kind, all that should be done is to connect the pads (3) to the common pad (4) on the module board (2) with bonding wires (5).

Description

Description Memory module Technical field

The present invention relates to a memory module that can be mounted on a memory board, a motherboard, or the like. Background art

Generally, a memory bare chip or a processor bare chip cut out of a semiconductor wafer is mounted on a printed circuit board or the like in a packaged state. However, the external dimensions of the package are considerably larger than the size of the various bare chips themselves, so there are certain limitations on the number of memory packages and cages that can be mounted on a printed circuit board or the like.

—On the other hand, recently, a multi-chip module (MCM) in which a plurality of bare chips are mounted on a substrate having almost the same size as a packaging substrate is becoming popular. The use of this multi-chip module makes it possible to (1) reduce the size and weight of the mounting area, (2) improve the performance and speed of high-density wiring and bare chip mounting, and (3) ensure high reliability.

By the way, in the module substrate used in the above-mentioned multi-chip module, since a plurality of bare chips are arranged in close contact with each other, wiring becomes complicated, and it is usually necessary to form a wiring pattern over a plurality of layers. For this reason, it is necessary to take measures such as using an expensive multi-layer substrate having a large number of layers and making the wiring pattern thinner, which increases costs. In addition, as the amount of wiring on the module substrate increases, failures such as disconnection or short circuit of the wiring pattern are more likely to occur, and noise such as crosstalk is more likely to occur. Disclosure of the invention

The present invention has been made in view of the above points, and its purpose is to It is an object of the present invention to provide a memory module that can simplify wiring in a rule substrate.

When a memory module is configured as a multi-chip module, the memory modules of the present invention are arranged adjacent to each other in units of two even-numbered memory chips having the same structure. In the case of a memory chip, for example, a part of control signals such as a chip select signal and a write enable signal and a part or all of data or an address are often connected in common. However, if the same type of signal is input and output when the adjacent memory chips are oriented in the same direction, wiring routing and the like can be reduced, and wiring in the module substrate can be simplified.

The above-described arrangement of the memory chips is suitable for a DRAM memory chip in which a plurality of chip pads are arranged in a row. That is, in this case, the pads of the same type and in the same order are arranged in parallel, so that the pads of the same type can be easily connected, and the wiring in the module substrate is reduced. It doesn't get complicated. In particular, when connecting the same type of chip pads of these two memory chips to the substrate pads formed between two memory chips arranged in the same direction, the chip pads are connected to each other. Since only the wiring and the common board pad between them are required to be connected, the connection by the wiring pattern in the module board can be reduced. When this connection is performed using a bonding wire, the bonding wire between the chip pad and the substrate pad does not intersect with another bonding wire. be able to. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a plan view schematically showing a memory module of the present embodiment,

FIG. 2 is a sectional view taken along the line A—A ′ in FIG. 1,

FIG. 3 is a diagram showing the arrangement direction of each memory bay chip on the module substrate, FIG. 4 is a perspective view showing a part of the memory module,

Figure 5 is a circuit diagram of the memory module, FIG. 6 is a diagram showing the pattern layout of the module board,

FIG. 7 is a view showing a state in which the memory module is mounted on an SODIMMM board. FIG. 8 is a view showing a module board in the case where a bare chip for memory is mounted on a flip chip.

FIG. 9 is a plan view of a memory module showing an example in which bonding wires are alternately drawn. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a memory module as a multi-chip module to which the present invention is applied will be specifically described with reference to the drawings.

FIG. 1 is a plan view schematically showing a memory module of the present embodiment, and FIG. 2 is a sectional view taken along line AA ′ of FIG. As shown in the figure, a memory module 10 has four memory base chips 1 of the same structure, which are individually cut out from a semiconductor wafer, placed on a rectangular module substrate 2 by a C 0 B (chip). On Board) This is implemented. Each memory base chip 1 is a DRAM having a memory capacity of, for example, 4 M × 4 bits.Each of the memory bare chips 1 has a rectangular shape, and a plurality of packages are arranged in a line in the center along the long side. C3 is formed.

On the other hand, the module board 2 has an external dimension that can be mounted on a SO—DIMM (Single Outline Dual Inline Memory Module) board, which will be described later. A plurality of pads 4 are formed substantially in a row. Two memory bay chips 1 are mounted on both sides of the pad 4, and the direction in which the pads 4 of the module board 2 are arranged is almost parallel to the direction in which the pads 3 of each memory bay chip 1 are arranged. It has become. In other words, a plurality of pads 4 are formed on the module substrate 2 between two memory bare chips 1 arranged such that their long sides are adjacent to each other and in parallel with their respective pads 3. ing. The pad 3 described above corresponds to a chip pad, and the pad 4 corresponds to a board pad.

The pad 4 of the module board 2 and the pad 3 of the memory bare chip 1 are connected by bonding wires 5. The nodes 4 include one in which two bonding wires 5 are connected and one in which one bonding wire 5 is connected. Bare chips for memory 1 For terminals commonly connected to a plurality of memory bare chips 1 such as address terminals of the memory, by connecting a plurality of bonding wires 5 to a pad 4 on the module board 2, the pad is connected. 4 is being shared.

As described above, since a plurality of bonding wires 5 are connected to some of the pads 4, the total number of the pads 4 can be smaller than the total number of the pads 3 of the entire memory bare chip 1. In addition, by connecting two bonding wires 5 to some of the pads 4, the two bonding wires 5 can be connected to each other at the same time through the common pad 4. The amount of wiring can be reduced. For example, when the module substrate 2 is configured using a multilayer substrate, the number of layers of the substrate can be reduced, and the cost of the memory module 10 can be reduced.

Also, the memory bare chips 1 are arranged such that the pads 3 of the memory bare chips 1 are arranged in two rows in parallel with the longitudinal direction of the module substrate 2, and furthermore, the pads 4 of the module substrate 2 are sandwiched therebetween. When the two memory bases 1 arranged adjacent to each other are oriented in the same direction, the bonding wire 5 from each memory bare chip 1 is connected to the common pad 4 of the module board 2. Then, a plurality of bonding wires 5 are connected to the common pad 4 at the shortest distance.

Further, when the corresponding pads 3 of the two memory bare chips 1 are connected to each other, it is only necessary to connect the common pads 4 of the module substrate 2 with the bonding wires 5. There is no need to perform wiring using different wiring layers within the module, and wiring within the module substrate 2 can be simplified. On the other hand, considering the case where the direction of the memory bay chip 1 is reversed or the case where the memory bay chips having different structures are combined, the corresponding identical pads 3 are shared by the common package of the module substrate 2.も Even if you try to connect to the board 4, you cannot connect directly because the wire bonding 5 crosses each other. For example, it will once pass through another wiring layer in the module board 2, Wiring becomes complicated.

In addition, since the pads 4 on the module substrate 2 are concentrated between the two bare memory chips 1 arranged so that the long sides are adjacent to each other, each pad 4 is located outside the corresponding bare memory chip 1. Pad 4 occupies compared to forming pad 4 separately The area can be reduced, and the memory module 10 can be reduced in size and mounted with high density.

FIG. 3 is a diagram showing the arrangement direction of each memory bare chip 1 on the module substrate 2. As shown in FIG. 3 (a), four memory bare chips 1 arranged with a plurality of pads 4 on a module substrate 2 interposed therebetween are arranged in such a manner that all of them are oriented in the same direction. In addition, as shown in FIG. 3 (b), at least two memory bare chips 1 adjacent to each other with the pad 4 interposed therebetween may be arranged in the same direction. As shown in FIG. 2, the resin 10 covers the upper surface of the wire-bonded memory bare chip 1 with a resin 6 to prevent disconnection or the like. If the resin 6 is formed thick, the height of the memory module 10 becomes too high. Therefore, a sealing frame 7 having a predetermined height is attached near the outer periphery of the module substrate 2, and the resin 6 is poured into the sealing frame 7. The thickness of the resin is set to match the height of the sealing frame 7. As a result, variations in the height of the memory module 10 can be reliably suppressed.

Further, the memory module 10 of the present embodiment is mounted on a main board such as a S0-DIMM board by a so-called LCC (Leadless Chip Carrier) method. FIG. 4 is a perspective view showing a part of the memory module 10 shown in FIG. As shown in the figure, external connection terminals 8 formed in a concave shape are provided on the outer surface of the module substrate 2, and these external connection terminals 8 are wirings formed on the surface or inside the module substrate 2. It is electrically connected to the pads 4 on the surface of the module substrate 2 via the pattern 9. In addition, by pouring solder into the recesses of these external connection terminals 8, electrical connection with the main board and the like, as well as mechanical fixing, are performed.

In addition, the memory module 10 of the present embodiment is obtained by cutting out the memory bare chip 1 formed on the semiconductor wafer and mounting it on the module substrate 2 without packaging. (For example, 4) memory bare chips 1 can be mounted without difficulty.

FIG. 5 shows a memory device constructed using four memory chips 1 having the same structure. FIG. 3 is a circuit diagram of the memory module 10. In this figure, some terminals such as a power supply terminal and a ground terminal are omitted for simplification. As shown in the figure, some of the terminals of each memory chip 1 are connected in common to all the memory bare chips 1. More specifically, the address terminals A0 to A11 of each memory bare chip are commonly connected to the external connection terminals ADRO to ADR11, respectively, the control terminal RAS is connected to the external connection terminal RE, and the control terminal WE is connected to the external connection terminal WE. In addition, the control terminal OE is commonly connected to the external connection terminal OE. On the other hand, the data terminals I / O0 to 1/03 are separately connected to the external connection terminals DO to D15, respectively. The control terminal CAS is connected to the external connection terminals CE 0 and CE 1 as a set of two memory bare chips 1.

FIG. 6 is a diagram showing a pattern layout of the module substrate 2, wherein the hatched portions in the drawing show the wiring patterns, and the dotted lines in the drawing show the mounting positions of the memory bare chips 1. The module board 2 is composed of, for example, a four-layer printed wiring board. Pads 4 are formed substantially in a line in the longitudinal direction at the center of the uppermost layer, and solid pads for grounding are provided on both sides of the pads 4. Pattern 21 is formed. The ground solid pattern 21 is also formed on the lowermost layer. Further, a wiring pattern 22 is connected to each pad 4, and the other ends of these wiring patterns 22 are connected to through holes 23 except for a part. The through-hole 23 is connected to an inner layer pattern or a lowermost layer pattern, and the patterns of these layers are respectively connected to the external connection terminals 8. In addition, for terminals commonly connected to a plurality of memory bare chips 1 such as address terminals and control terminals, a plurality of corresponding pads are connected to each other by a wiring pattern 22.

In the memory module 10 of the present embodiment, the number of the external connection terminals 8 can be reduced because one external connection terminal 8 is shared in correspondence with the pads 3 of the plurality of memory base chips 1. Is not much different from the total number of pads 3 for one bare chip for memory.

Also, the memory module 10 of the present embodiment has a plurality of memory bare chips 1 mounted on the module substrate 2 by COB, and wiring between the memory bare chips 1 is performed by an SO-DIMM substrate or the like instead of the module. The module base The amount of wiring of the S0—DIMM board or the like can be much smaller than that of mounting the memory bare chip 1 mounted on the board 2 individually on the main board.

In addition, the memory module 10 as a multi-chip module can have a smaller mounting area than mounting the packaged memory chips individually, reducing the wiring length and reducing the effects of wiring delay and noise. You can do it.

FIG. 7 is a plan view showing an example in which the memory module 10 of the present embodiment is mounted on the SO-DIMM board 11, and FIG. 7 (a) shows one of the SO-DIMM boards 11. Figure 7 (b) shows the other side. In the SO-DIMM substrate 11 shown in the figure, two memory modules 10 are mounted on each side, and two memory modules 10 are provided for each memory module 10 to prevent noise. Hereinafter, it will be referred to as a bus control) 12. A controller 13 for checking the bare chip 1 for each memory is mounted on one surface. Each memory module 10 is mounted by the above-described LCC method, and the bypass capacitor 12 and the controller 13 are mounted by the SMT (Surface Mount Technology) method.

The SO-DIMM board shown in Fig. 7 has the same result as mounting a total of 16 memory ICs with 8 on each side. For example, the memory bare chip 1 that constitutes the memory module 10 has 4 MX each. In the case of a 4-bit DRAM, the memory capacity of each memory module 10 is 8 Mbytes, and the total memory capacity of the SO-DIMM is 32 Mbytes.

In the above-described embodiment, an example in which a plurality of memory bare chips are mounted on the module substrate 2 by C0B has been described. Instead of COB mounting, a so-called COG (Chip On Glass) Alternatively, COF (Chip On Film) mounting, in which a chip is mounted on a film, may be performed, and the material of the module substrate 2 can be changed as needed.

Also, instead of mounting the bare memory chip 1 on the module substrate 2 using the bonding wires 5, it is also possible to mount the memory substrate 1 on the module substrate 2 using bumps such as solder balls or gold balls. Good. Figure 8 shows the FIG. 4 is a diagram showing a module substrate when a bare chip for memory is mounted on a flip chip. In this figure, pads 4 'are formed on the module substrate 2 at the same intervals as the pads 3 of the bare chip for memory 1 shown in FIG. 1, and as shown in FIG. Place bare chip 1 for memory in the same direction. The dotted line part shown in FIG. 8 indicates the mounting position of the memory base chip 1.

Since the same pads 3 are adjacent to each other by aligning the orientation of the two flip-chip mounted memory bare chips 1, for example, address terminals and data terminals are placed on the module substrate 2 or in the module substrate 2. Even in the case where the connection is made by the connection, the adjacent wiring patterns do not cross each other to make the connection, the number of layers forming the wiring pattern can be reduced, and the wiring pattern can be shortened. Therefore, it is not necessary to route a large number of wiring patterns on the module substrate 2, and it is possible to reduce the influence of wiring delay and noise.

Further, in the above-described embodiment, an example in which the completed memory module 10 is mounted on a main substrate such as S0-DIMM by the LCC method has been described. However, a BGA (Ball Grid) using bumps such as solder balls is used. Array) method may be used.

In FIG. 1, the bonding wire 5 is drawn almost symmetrically from the two memory bare chips 1 arranged on both sides of the pad on the module board 2 as shown in FIG. As for the pad 4 to which one bonding wire 5 is connected, the bonding wire 5 may be alternately drawn out from the memory bare chips 1 on both sides.

Also, in FIGS. 1 and 9, an example in which the memory module 10 is configured to include the four memory bare chips 1 has been described, but the number of the memory bare chips 1 mounted on the memory module 10 is as follows. The number is not limited to four and is not particularly limited as long as it is two or more. However, if too many memory bare chips 1 are mounted, the failure rate of the memory module 10 may increase. Therefore, the type of memory chip 1 to be implemented (for example, the number of bits and the memory capacity) is taken into consideration, and the number of memory modules 10 to be implemented is determined based on the number of memory modules 10 to be manufactured. It is desirable to determine the number of tips 1. Since ordinary computer equipment often manages the memory capacity in multiples of four, it is desirable that the number of memory base chips 1 mounted on the module substrate be even.

In the above-described embodiment, the example in which the DRAM is mounted on the module substrate 2 has been described. However, it is also possible to mount another type of memory bare chip 1 such as an SRAM or a flash ROM. Industrial applicability

As described above, according to the present invention, when a memory module is configured as a multi-chip module, by arranging adjacent memory chips having the same structure in units of two even-numbered memory chips, When inputting and outputting the same type of signals and data to and from each memory module, the number of wirings in the module substrate is reduced, and the wirings can be simplified.

In particular, when wiring is performed by wire bonding using a DRAM memory chip in which chip pads are arranged in a line, the same type of chip pads of each memory chip are connected to each other. When connecting them, it is only necessary to connect them and the common board pad with bonding wires, so that the wiring in the module board can be further simplified.

Claims

The scope of the claims

1. A memory module characterized by mounting an even number of memory chips of the same structure cut out from a semiconductor wafer on a module board by arranging and aligning them in units of two.

2. The memory chip is for DRAM, and a plurality of chip pads are formed in a row at a center along a long side of a rectangular shape, and the pads of two memory chips arranged in the same direction. 2. The memory module according to claim 1, wherein said pads of the same type are arranged in the same order.

3. The module substrate has a plurality of substrate pads formed substantially in parallel with the chip pads between two memory chips arranged adjacent to each other in the same direction. 3. The memory module according to claim 2, wherein said memory chips are arranged on both sides of a substrate pad.

4. A part of the plurality of chip pads formed on each of the two memory chips arranged in the same direction and of the same type are connected to the substrate on the module substrate. 4. The memory module according to claim 3, wherein the memory module is connected via a pad.

5. The chip pad commonly connected to the substrate pad includes at least a part of a control terminal and one of an address terminal and a data terminal. The memory module according to the item.