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WO1998038652A9 - Pave resistif en couche epaisse et sa fabrication - Google Patents

Pave resistif en couche epaisse et sa fabrication

Info

Publication number
WO1998038652A9
WO1998038652A9 PCT/IB1998/000133 IB9800133W WO9838652A9 WO 1998038652 A9 WO1998038652 A9 WO 1998038652A9 IB 9800133 W IB9800133 W IB 9800133W WO 9838652 A9 WO9838652 A9 WO 9838652A9
Authority
WO
WIPO (PCT)
Prior art keywords
thick film
layers
sub
contact
tcr
Prior art date
Application number
PCT/IB1998/000133
Other languages
English (en)
Other versions
WO1998038652A3 (fr
WO1998038652A2 (fr
Inventor
Hong Jyh Li
Ruey Tzong Chang
Original Assignee
Koninkl Philips Electronics Nv
Philips Svenska Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Svenska Ab filed Critical Koninkl Philips Electronics Nv
Priority to JP10529230A priority Critical patent/JP2000509907A/ja
Priority to EP98900968A priority patent/EP0919061A2/fr
Publication of WO1998038652A2 publication Critical patent/WO1998038652A2/fr
Publication of WO1998038652A3 publication Critical patent/WO1998038652A3/fr
Publication of WO1998038652A9 publication Critical patent/WO1998038652A9/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H01C1/142—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors the terminals or tapping points being coated on the resistive element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C13/00—Resistors not provided for elsewhere
    • H01C13/02—Structural combinations of resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/003—Thick film resistors

Definitions

  • the invention relates to a method of manufacturing thick film chip resistors, said method comprising the following steps: a. providing a number of contact layers on an electrically insulating substrate plate, b. applying a number of thick film resistance layers on the substrate plate, each of said thick film resistance layers being in contact with two neighbouring contact layers, c. fracturing the substrate plate into substrate rods, d. applying end contacts to the contact layers, and e. fracturing the rods into individual thick film resistors.
  • the invention also relates to a thick film chip resistor comprising an insulating substrate a main surface of which is provided with two contact layers between which a thick film resistance layer is provided, each of said contact layers being contacted with an end contact.
  • the inventive resistor is characterized in that the thick film resistance layer comprises at least two separate sub layers, which are at a distance of at least 0.05 mm.
  • Figure 2 shows in a perspective view a detail of the substrate plate depicted in Figure 1
  • Figure 3 schematically shows a number of thick film chip resistors according to the present invention
  • Figure 4 shows in a histogram the results of the variance in resistance value which is measured in mass produced thick film chip resistors which are either manufactured in accordance with the present invention (a) or manufactured not in accordance with the present invention (b).
  • longitudinal contact layers (4) are provided on one of the main surfaces of substrate plate (1) as shown in Fig 1-A.
  • These layers (4) can be provided by means of vacuum deposition techniques, such as f.i. sputtering and metal evaporation, but they are preferably provided by means of screen printing.
  • Said screen printed contact layers which contain for example Ag or Pd/Ag, are fired at 850° C for 1 hour. For clarity, only three contact layers are shown in Fig 2. It is noted, that the contact layers can also be constructed as small, discrete area's as shown in US 5.258.738.
  • these resistance layers comprise at least two separate sub layers (5,8) per individual chip resistor unit.
  • these resistance layers comprise at least two separate sub layers (5,8) per individual chip resistor unit.
  • two thick film resistance layers each comprising two sub layers (5) and (8) per individual chip resistor unit are shown in Fig 2.
  • steps a providing contact layers
  • step b applying thick film resistance layers
  • the method in which the contact layers are provided on the substrate before the thick film resistance layer are applied is preferred.
  • the same procedure of applying contact layers and resistance layers comprising at least two sub layers is also executed on the other main surface of the substrate plate.
  • a thicker layer of Ni is provided on said first layer by means of electroplating and a solder layer is applied onto the Ni-layers.
  • a dipping process for this purpose by dipping the fracture surfaces into a conductive paste which contains f.i. Ag or Ag/Pd, so that the fracture surfaces become covered by such paste.
  • the substrate rods need to be fired for one hour at about 580°C in order to consolidate the conductive paste as a layer on the fracture surfaces.
  • the thus formed end contacts are electrically conductively connected to the contact layers (4).
  • the rods (6) are broken along the fracture grooves (3) (chip grooves) into individual thick film chip resistors. In Fig. 1-C, only a few of these resistors are schematically shown. In total, approximately 1800 thick film chip resistors having dimensions of 1.6 x 3.2 x 0.54 mm 3 can be manufactured from said Al 2 O 3 substrate.
  • Figure 4 shows a histogram in which the frequency (F) of the individual resistors having a certain resistance value (k ⁇ ) is depicted.
  • F frequency
  • k ⁇ resistance value

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Non-Adjustable Resistors (AREA)

Abstract

L'invention concerne un procédé amélioré permettant de fabriquer des pavés résistifs en couches épaisses pour la production de masse. En appliquant au moins deux couches de résistance par pavé résistif, on obtient moins de variance dans la valeur de la résistance finale si on fabrique les résistances, en production de masse, en utilisant des plaques de substrat. Moins de variance dans la valeur de la résistance implique moins d'activité d'ajustement, ce qui aboutit à une réduction considérable des coûts. De plus, quand on applique au moins deux sous-couches, on peut compenser le coefficient de température de la résistance (CTR) en utilisant un matériau résistant ayant un CTR positif pour une sous-couche et un matériau résistant ayant un CTR négatif pour l'autre sous-couche.
PCT/IB1998/000133 1997-02-26 1998-02-02 Pave resistif en couche epaisse et sa fabrication WO1998038652A2 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10529230A JP2000509907A (ja) 1997-02-26 1998-02-02 厚膜チップ抵抗器及びその製造
EP98900968A EP0919061A2 (fr) 1997-02-26 1998-02-02 Pave resistif en couche epaisse et sa fabrication

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP97200545.8 1997-02-26
EP97200545 1997-02-26

Publications (3)

Publication Number Publication Date
WO1998038652A2 WO1998038652A2 (fr) 1998-09-03
WO1998038652A3 WO1998038652A3 (fr) 1998-12-10
WO1998038652A9 true WO1998038652A9 (fr) 2001-07-05

Family

ID=8228051

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1998/000133 WO1998038652A2 (fr) 1997-02-26 1998-02-02 Pave resistif en couche epaisse et sa fabrication

Country Status (4)

Country Link
EP (1) EP0919061A2 (fr)
JP (1) JP2000509907A (fr)
TW (1) TW340976B (fr)
WO (1) WO1998038652A2 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7038572B2 (en) * 2001-03-19 2006-05-02 Vishay Dale Electronics, Inc. Power chip resistor

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4803457A (en) * 1987-02-27 1989-02-07 Chapel Jr Roy W Compound resistor and manufacturing method therefore
EP0509582B1 (fr) * 1991-04-16 1996-09-04 Koninklijke Philips Electronics N.V. Résistance SMD
JP3309010B2 (ja) * 1993-09-02 2002-07-29 コーア株式会社 電子部品の製造方法
JPH07153601A (ja) * 1993-12-01 1995-06-16 Hokuriku Toryo Kk チップ抵抗器の製造方法
BE1007868A3 (nl) * 1993-12-10 1995-11-07 Koninkl Philips Electronics Nv Elektrische weerstand.
JPH08172004A (ja) * 1994-10-18 1996-07-02 Taiyo Yuden Co Ltd チップ抵抗器の製造方法
JP3637124B2 (ja) * 1996-01-10 2005-04-13 ローム株式会社 チップ型抵抗器の構造及びその製造方法

Also Published As

Publication number Publication date
WO1998038652A3 (fr) 1998-12-10
TW340976B (en) 1998-09-21
EP0919061A2 (fr) 1999-06-02
WO1998038652A2 (fr) 1998-09-03
JP2000509907A (ja) 2000-08-02

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