WO1998037583A1 - Method for manufacturing semiconductor device - Google Patents

Abstract

At the time of machining a laminated gate electrode containing a metallic material, thin insulating side-wall coatings are provided on the side wall sections of an upper conductive laminated film, while part of a polycrystalline silicon layer which is the gate electrode of the lowermost layer is left. Later, the left polysilicon layer is etched off, cleaned with a chemical, and heat-treated for restoring the layer from dry-etching damages. Therefore, the resistance of the gate electrode can be reduced remarkably without causing the increase of junction leakage currents nor the reliability deterioration of a gate oxide film due to metallic contaminants.

Description

 Description Method of manufacturing semiconductor device

 The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a MISFET using a semiconductor or a metal material as a gate electrode. Background art

 With the miniaturization of LSI, there is a strong demand for lowering the resistance of the MOSFET gate electrode. This is for the following reasons. (1) The gate electrode width is reduced due to the miniaturization of elements, and as a result, the resistance of the gate electrode wiring tends to increase. (2) As the integration degree of LSI increases, In addition, as the gate electrode wiring length increases, the resistance of the gate electrode wiring tends to increase. For this reason, there has been proposed a proposal in which polycrystalline silicon or metal silicide, which has been conventionally used, is used as a gate electrode material, and a lower resistance metal such as tungsten or titanium is used as the gate electrode material. Have been. For example, in Japanese Patent Application Laid-Open No. 61-152,076, a conventional polycrystalline structure was formed by forming a gate electrode into a laminated structure composed of polycrystalline silicon, a metal nitride film, and a metal film. Proposals have been made to reduce the resistance of the gate electrode while maintaining the reliability of the gate oxide film in the case of silicon gate.

However, in the above-mentioned conventional technology, since the gate electrode including the metal film is processed, the gate electrode portion, the source / drain of the MOSFET, It has been clarified by the present inventors that there is a problem that metal contamination occurs in the diffusion layer region to be formed.

 That is, when a polycrystalline silicon is used as the gate electrode, titanium nitride is used as the barrier layer, and a metal film for lowering resistance, for example, a laminated film made of tungsten is used. It is difficult to select a chemical solution for cleaning the source / drain formation surface after electrode pattern application. In addition, when thermal oxidation treatment is performed to recover the dry etch damage received by the gate oxide film in the gate etch portion, titanium nitride becomes abnormally oxidized, and the gate electrode becomes phthalate, or the titanium nitride and the tungsten are removed. There is a problem that is peeled off. Therefore, if ion implantation for forming the source / drain is performed without performing the thermal oxidation treatment, contamination of the oxide film surface is implanted into the substrate by impurity ions, and the problem of PN junction leakage is reduced. Newly arise.

 Therefore, when a semiconductor layer of polycrystalline silicon and a conductive laminated film in which a conductor made of titanium nitride and tungsten are laminated on the semiconductor layer are used as the gate electrode, the gate under the gate electrode is used. The issue is how to recover the dry etch damage of the oxide film (measure against insulation failure).

 That is, an object of the present invention is to provide a method of manufacturing a semiconductor device having a low-resistance gate electrode and capable of improving reliability.

 Another object of the present invention is to provide a method for manufacturing a semiconductor device which has a gate electrode of low resistance, is fine and can improve reliability.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device suitable for high speed and high integration. Disclosure of the invention

 (Solution)

 According to the present invention, a gate electrode formed of a conductive laminate in which the lowermost layer is a semiconductor layer and another conductive film containing a metal material (metal film) for reducing resistance is laminated on the semiconductor layer In the processing (pattern etch) of the lower layer, the etching of the lowermost semiconductor layer is stopped halfway and left thinly, and the side wall of the upper conductive laminated film is covered with an insulating first side wall film. The thinned lowermost semiconductor layer is etched, cleaned, and thermally oxidized to improve the reliability by recovering the dry etching damage of the gate oxide film in the gate edge portion.

 Etching of the semiconductor film that will become the gate electrode is performed so that the semiconductor film remains, and an insulating film is provided on the sidewall of the etched semiconductor film to protect the gate edge from cleaning, wet etching, and the like. It is possible to do.

 Further, in a gate electrode structure in which a gate electrode is formed by laminating a semiconductor film and a metal film, it becomes possible to prevent abnormal oxidation of the metal film and separation of the metal films during thermal oxidation treatment.

 Note that in order to protect the substrate from etching damage, the semiconductor film of the gate electrode is preferably etched so that the thickness of the semiconductor film remains at least 5 nm.

Further, in a gate electrode in which a semiconductor film and a metal film are stacked, it is not always necessary to stop the etching of the semiconductor film in the middle, and the gate electrode is formed on the side wall of the gate electrode, for example, at the interface between the semiconductor film and the metal film. The etching of the gate electrode may be stopped, and an insulating film may be formed on the side wall of the etched film. Further, according to the present invention, after forming a gate oxide film in the gate etching portion, a first impurity layer is formed in the semiconductor substrate in a self-aligned manner with respect to the first side wall film. Forming a second side wall film on the surface of the first side wall film, forming a second impurity layer in the semiconductor substrate in a self-aligning manner with the surface of the second side wall film, By forming an interlayer insulating film on the substrate and forming an opening for contact that is aligned with the interlayer insulating film by the second sidewall film and exposes the surface of the second impurity layer, It has a gate electrode of resistance and is fine and improves reliability.

 Further, according to the present invention, in particular, a groove having a desired depth is formed in a selected area of the main surface of the semiconductor substrate, and an insulating film is formed on the main surface of the semiconductor substrate including the groove. By depositing and then polishing the insulating film to form a group isolation in which the insulating film is embedded in the groove, a semiconductor device suitable for higher integration is obtained. Is obtained.

(Effect)

 According to the present invention, it is possible to easily perform a process of recovering damage to a gate oxide film in a metal-contaminated {gate-etched portion) after processing the gate electrode, which is a problem when forming a gate electrode having a laminated structure including a metal. As a result, the gate electrode resistance can be drastically reduced without increasing the junction leakage current due to metal contamination and without deteriorating the reliability of the gate oxide film.

In addition, according to the present invention, the use of the SAC and the group isolation enables a miniaturized MOSFET structure to be achieved and a highly integrated semiconductor device to be obtained. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 1; FIG. 3 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 2; FIG. 4 is a fragmentary cross-sectional view following FIG. 3 showing the semiconductor device manufacturing process. FIG. 5 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 4; FIG. 6 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 5; FIG. 7 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 8 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 9 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 10 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 9; FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 1.0. FIG. 12 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 11; FIG. 13 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 12; FIG. 14 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 13; FIG. 15 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 14; FIG. 16 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 15; FIG. 17 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 16; FIG. 18 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 17; FIG. 19 is a fragmentary cross-sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention. Figure 20 is a semi-continuation of Figure 19 It is principal part sectional drawing which shows the manufacturing process of a body device. FIG. 21 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 20; FIG. 22 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 21; FIG. 23 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 24 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device, following FIG. FIG. 25 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 24. FIG. 26 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 25; FIG. 27 is a cross-sectional view of a principal part showing a manufacturing step of a semiconductor device, following FIG. 26. FIG. 28 is a cross-sectional view of a principal part showing a manufacturing step of the semiconductor device, following FIG. 27. FIG. 29 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. FIG. 30 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 29. FIG. 31 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 30; FIG. 32 is a cross-sectional view of a principal part showing a manufacturing step of a semiconductor device, following FIG. FIG. 33 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 32. FIG. 34 is a cross-sectional view of main parts showing the manufacturing steps of the semiconductor device, following FIG. 33. FIG. 35 is a cross-sectional view of the principal part showing the manufacturing process of the semiconductor device, following FIG. FIG. 36 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor device, following FIG. 35; BEST MODE FOR CARRYING OUT THE INVENTION

 (Example 1)

 A first embodiment of the present invention will be described with reference to FIGS. 1 to 18.

 First, as shown in Fig. 1, a selective oxide film 102 for isolation is formed on a P-type single crystal Si substrate 101 by a normal selective oxidation method (LOCOS technology). I do. This selective oxide film is formed to a thickness of, for example, 30 Onm.

 Subsequently, as shown in FIG. 2, a gate oxide film 103 having a thickness of about 5 nm was formed on the surface of the Si substrate 101 partitioned by the selective oxide film by a thermal oxidation method. Form. A 5 nm thick Si (polycrystalline silicon) film 104 is formed on the gate oxide film 103 by low pressure chemical vapor deposition. A 20 nm-thick titanium nitride film 105 as a Si film 104 barrier layer is deposited by sputtering. Then, a low-resistance metal material having a high melting point that can withstand heat treatment, for example, a tungsten film 106 is deposited on the titanium nitride film 105 to a thickness of 100 nm by sputtering. . Further, in order to prevent oxidation of the titanium nitride film 105 and the tungsten film 106, a silicon nitride film 107 having a thickness of 150 nm is formed on the surface of the tungsten film 106. It is formed by low pressure chemical vapor deposition.

 Subsequently, as shown in FIG. 3, the resist 108 is patterned by a lithography technique.

Subsequently, the silicon nitride film 107, the tungsten film 106, and the titanium nitride film 105 were sequentially processed by dry etching using the resist 108 as a mask. At this time, the lowermost Si film 104 On the other hand, etching of about 20 nm was performed, and after removing the resist mask, the shape shown in FIG. 4 was obtained. Subsequently, cleaning with an organic cleaning solution is performed for the purpose of removing contaminants such as dry etching residues.

 Subsequently, as shown in FIG. 5, a silicon nitride film 109 having a thickness of 10 to 20 nm is deposited by low pressure chemical vapor deposition. In this embodiment, the silicon nitride film is formed on the polycrystalline silicon film 104 and on the side walls of the gate, but the polycrystalline silicon film is oxidized to form an oxide film to protect the gate edge portion. You may.

 Thereafter, as shown in FIG. 6, the cap layer patterned by performing anisotropic etching by dry etching technology.

The first insulating side wall coating 11 made of, for example, oxidation-resistant silicon nitride is formed on the side walls of (107) and the gate electrodes (106, 105, and a part of 104). 0, a so-called side wall film is formed.

 Then, as shown in FIG. 7, a gate electrode is formed by completely patterning the Si film 104 using the cap layer and the insulating side wall film 110 of the side wall as a mask.

 Then, as shown in FIG. 8, the oxide film 103 is removed by cleaning with a mixed solution of ammonia and hydrogen peroxide and wet etching with a dilute hydrofluoric acid aqueous solution. At this time, the oxide film 103 is slightly etched. Here, since the material exposed on the surface is a silicon oxide film, a silicon nitride film, or a silicon film, the cleaning means usually used in an LSI process including a hydrofluoric acid aqueous solution treatment is made of metal. It can be used while avoiding problems such as elution of water.

Next, as shown in Fig. 9, protection by an oxide film at the gate edge The purpose was 8 5 0 ° C, the thermal oxide film 1 1 1 is Ri by the thermal oxidation in a dry 〇 ₂ atmosphere was 5 nm grown on the substrate. In the thermal oxidation at this time, since the titanium nitride 105 and the tungsten film 106 are covered with the first insulating sidewall film 110 and the cap layer 107 which are oxidation-resistant, Since the material exposed to the silicon nitride film and silicon is limited to silicon nitride film and silicon, it can be easily performed without the problem of blistering and peeling as in the conventional case described above.

Thereafter, as shown in FIG. 10, arsenic ions are implanted by ion implantation to match the first insulating side wall film 110 to form a first N-type impurity layer 112. I do. At this time, the ion implantation energy is 15 KeV, and the implantation concentration is 2 × 10 ¹³ atoms / cm ² .

 Subsequently, as shown in FIG. 11, a silicon nitride film 113 having a thickness of 50 to 100 nm is deposited by low pressure chemical vapor deposition.

 Subsequently, as shown in FIG. 12, a second insulating sidewall film 114 is obtained by performing anisotropic dry etching.

Then, as shown in FIG. 13, a second N-type impurity layer 115 is formed by implanting phosphorus ions by ion implantation in alignment with the second insulating side wall film 114. . At this time, the ion implantation energy is 25 to 30 KeV, and the implantation concentration is 5 × 10 ¹⁴ atomscm ² . Therefore, the second N-type impurity layer 115 is formed as a contact region deeper than the first N-type impurity layer 114.

Subsequently, after the ion damage was recovered by annealing, as shown in FIG. 14, the SiO ₂ insulating film 1 serving as an interlayer insulating film between wirings was formed. 16 is formed by the plasma CVD technique. This SiO ₂ -based insulating film 116 has a thickness of about 300 nm.

Subsequently, as shown in FIG. 15, a resist 117 is patterned on the SiO ₂ -based insulating film 116 by using a lithography technique. The urchin by that shown in the first 6 figure registry 1 1 7 a second N-type impurity layer Ri especially good for Etsuchingu the S i 〇 ₂ based insulating film 1 1 6 Ri by the gong Ietsuchingu technology mask 1 1 the opening of the contactor preparative hole the opening _c this contactor preparative hole to 5, the second side wall film 1 1 4 almost Etsu Chisarezu, also selective oxide film 1 0 2 end extent which is etched slightly The so-called self-aligned contact (SAC: Se1fA1ign Contact) can be realized, and miniaturization that does not require high-precision mask alignment can be achieved.

Subsequently, as shown in FIG. 17, a conductor layer of aluminum and silicon was used as a conductor layer on the opening and on the top of the Si ₂ -based insulating film 116 by a Snotter method. Is deposited to a thickness of 200 to 250 nm. For this conductive layer, a refractory metal such as tungsten or a refractory metal silicide can be applied.

 Then, as shown in FIG. 18, the conductive layer 118 is processed according to a desired wiring pattern by using lithography and dry etching techniques to form a wiring layer 119.

 Note that the conductive layer 118 can be formed as a plug electrode (electrode structure embedded in the opening) to be a structure optimal for a multilayer wiring structure having flattening.

Thereafter, the final passivation film is covered, and selective etching is performed on the passivation film so that the bonding pad is exposed. After the wafer is processed (scribed) into chips from the wafer state, bonding is performed on the exposed bonding pad to connect to an external lead, and finally, the semiconductor device is obtained by resin sealing. . In this embodiment, the gate electrode structure is a polycrystalline silicon / titanium nitride (barrier layer of polycrystalline silicon and tungsten) Z tungsten from the lower layer. For the purpose of reducing the contact resistance, other gate electrode structures such as polycrystalline silicon non-crystalline silicon silicide (metal silicide film) and polycrystalline silicon Z nitride titanium nitride (metal nitride film) are used. Even if it is selected, it is possible to recover the gate oxide film damage at the contamination {gate edge} portion of the diffusion layer due to the processing of the metal electrode by the same procedure as in the present embodiment. Therefore, a combination of the stacked electrode having the silicon film as the lowermost layer and the sidewall protection method described in this embodiment is within the scope of the present invention.

 When forming polycrystalline silicon Z tungsten silicide (metal silicide film), after forming the polycrystalline silicon film, a metal film made of tungsten is deposited on the polycrystalline silicon film. Then, by performing the heat treatment, a tungsten silicide (metal silicide film) can be easily formed.

 (Example 2)

 In Example 1 described above, a selective oxidation method (LOCOS technology) was employed as an isolation region for separation between a plurality of MOS FETs (elements). However, in the case of this selective oxidation method, a bird's beak is generated at the end of the selective oxide film, and it is a problem to miniaturize the element, particularly to obtain a MOSFET having a uniform gate oxide film of 5 nm or less.

The second embodiment shown in FIGS. 19 to 34 has a thickness of 10 nm or less, In particular, it is easy to obtain a MOS FET having a gate oxide film with a thickness of 3 to 5 nm, and it solves the conventional problems.

 That is, the present embodiment is a method of manufacturing a semiconductor device in the case where the groove isolation technology is used as the isolation.

 As shown in Fig. 19, a thermal oxide film 202 with a thickness of 1 O nm is formed on the silicon substrate 201, and a silicon oxide with a thickness of 150 nm is formed on the thermal oxide film 202. A nitride film 203 is formed.

 Subsequently, as shown in FIG. 20, a resist 204 for forming an isolation is buttered by a lithographic technique.

 Subsequently, as shown in FIG. 21, the silicon nitride film 203, the thermal oxide film 202, and the silicon substrate 201 are etched by dry-etching technology using the resist as a mask. A groove (depth about 0.3111) is formed in the portion where the solution is to be formed.

Subsequently, urchin by that shown in the second 2 FIG, Ri by the chemical vapor deposition, S i O ₂ based insulating (C VD- S i 0 ₂₎ film 2 0 6 a thickness of 5 0 0 nm deposition. Although not shown, the CVD-S i 0 ₂ film 2 0 6 Sakiritsu connexion to deposition, the surface of the groove is thermally oxidized to form a thin S i 0 ₂ film, crystal distortion on the surface of the groove Should be removed.

 Next, as shown in FIG. 23, the silicon nitride film 203 is flattened as a polishing stopper using a so-called CMP (Chemical Mechanical Polishing) technique. Groove isolation is obtained by chemical modification. In this case, a parse beak unlike the above embodiment is not formed.

Then, as shown in Fig. 24, the group isolation (G (Roove Isolation) A gate oxide film 207 having a thickness of about 3 to 5 nm is formed on the surface of the Si substrate 201 partitioned by the GI by a thermal oxidation method.

 Further, as shown in FIG. 25, a 50 nm thick Si (polycrystalline silicon) film 20 was formed on the good oxide film 207 by a low pressure chemical vapor deposition method. Form 8. Further, a titanium nitride film 209 having a thickness of 200 nm and a tungsten film 210 having a thickness of 100 nm are deposited by a sputtering method. Then, a silicon nitride film 211 having a thickness of 150 ηm is formed on the surface of the tungsten film 210 by a low pressure chemical vapor deposition method. Then, the resist 2 12 is patterned by lithography technology.

 Subsequently, the silicon nitride film 211, the tungsten nitride film 210, and the titanium nitride film 209 were processed by dry etching using the resist 212 as a mask. At this time, the underlying Si film 208 was also etched by about 20 ηm to obtain the shape shown in FIG. 26 after removing the resist mask. Subsequently, cleaning with an organic cleaning solution was performed to remove contaminants such as dry etching residues.

 Subsequently, as shown in FIG. 27, for example, a silicon nitride film is formed on the side walls of the cap layer (211) and the gate electrodes (parts of 210, 209 and 208). A first insulating sidewall film 2 13 was formed. The first insulating side wall film 2 13 is formed by first depositing a silicon nitride film having a thickness of 10 to 20 nm by low pressure chemical vapor deposition as in Example 1, and then performing dry etching. It is formed by performing anisotropic etching by technology.

Then, as shown in FIG. 28, the cap layer (211) and The gate electrode was formed by completely patterning the Si film 208 using the first insulating sidewall film 213 as a mask. Further, the oxide film 207 was removed by washing with a mixed solution of ammonia and hydrogen peroxide and dilute hydrofluoric acid aqueous solution. Here, since the material exposed on the surface is a silicon oxide film, a silicon nitride film, or a silicon film, the cleaning means usually used in an LSI process such as a hydrofluoric acid aqueous solution treatment is used to elute metal. Can be used while avoiding such problems.

Next, as shown in Fig. 29, a thermal oxide film 2 14 was placed on the substrate at 850 ° C and a dry O ₂ atmosphere for the purpose of modifying the gate oxide film in the gate portion. 5 nm was grown. The modification treatment by the thermal oxidation method can be easily performed because the material exposed on the surface is limited to the silicon nitride film and silicon.

Thereafter, as shown in FIG. 30, arsenic ions are implanted by ion implantation technology to form a first N-type impurity layer 216 in alignment with the first insulating side wall film 213. did. At this time, the ion implantation energy is 15 KeV, and the implantation concentration is 2 × 10 ¹³ atoms / cm ² .

Next, as shown in Fig. 31, a 50 to 100 nm thick silicon nitride film 113 is deposited by low pressure chemical vapor deposition, followed by anisotropic dry etching. As a result, a second side wall coating 2 15 was obtained. Then, as shown in FIG. 32, a second N-type impurity layer 217 was formed by implanting phosphorus ions by ion implantation in alignment with the second insulating side wall film 215. . At this time, the ion implantation energy is 25 to 30 KeV, and the implantation concentration is 5 × 10 ¹ atomscm ² . Therefore, the second N-type impurity layer 2 15 It is formed as a contact region deeper than the N-type impurity layer 2 13 of FIG.

Subsequently, after the ion damage is recovered by annealing, as shown in FIG. 33, an SiO ₂ -based insulating film 218 serving as an interlayer insulating film between wirings is formed by a plasma CVD technique. did. The Si ₂ -based insulating film 2 18 has a thickness of about 3101111. Then, a resist 219 was patterned on the SiO ₂ -based insulating film 218 by using a lithography technique.

Thereafter, the third 4 by FIG urchin, registry 2 1 9 Ri by the de dry etching technique to mask S i O ₂ based insulating film 2 1 8 etched to Rukoto by the Ri diffusion layer 2 1 7 A contact hole was opened. As is clear from the figure, the opening of the contact hole is such that the second side wall coating 2 15 is not etched, and the end of the group isolation GI is slightly etched. A self-aligned contact (SAC) can be achieved.

Subsequently, urchin by that shown in 35 figure as a conductor layer in the opening and S i 0 ₂ based insulating film 2 1 8 upper, Ri by the alloy 2 2 0 of aluminum and silicon in the sputtering Deposit 200-250 nm thick. This conductor layer can be made of a high-melting-point metal such as tungsten or a high-melting-point metal silicide, as in the above embodiment.

 Then, as shown in FIG. 36, the conductor layer 220 is processed using a lithography and dry etching technique according to a desired wiring pattern to form a wiring layer 221.

Thereafter, the final Passhibeshiyo down film coated, perform by Uni selection Etsuchingu that this passivation emission film bonding pad exposed _c Then, after processing (scribe) from the wafer state to chips, bonding is performed on the exposed bonding pad to connect to an external lead, and finally, the semiconductor device is sealed with resin. Obtained. According to the second embodiment described above, it is possible to obtain a semiconductor device manufacturing method suitable for high speed and high integration by lowering the resistance of the gate electrode as well as improving the reliability.

 In this embodiment also, the gate electrode structure is polycrystalline silicon / titanium nitride tungsten from the lower layer, but other gate electrode structures and gate contact structures due to factors such as gate resistance and wiring contact. For example, even if a structure such as polycrystalline silicon tungsten silicide or polycrystalline silicon non-nitride tungsten is selected, the contamination layer of the diffusion layer related to the processing of the metal electrode can be formed by the same procedure as in the present embodiment. It is possible to recover gate oxide film damage in the Toetu area. Therefore, a combination of the stacked electrode having the silicon film as the lowermost layer and the sidewall protection method described in the present embodiment is within the scope of the present invention.

 In the first and second embodiments described above, one MOS FET was used as an example. However, as is apparent from the embodiment, the formation of an isolation region in a semiconductor substrate is disclosed. Therefore, it is apparent that the present invention can be applied to the case of obtaining a semiconductor device having a plurality of MOS FETs as constituent elements, in general, a highly integrated semiconductor device called a semiconductor integrated circuit device. Specifically, it is useful when applied to the formation of MOS FET which constitutes a DRAM memory cell. Industrial applicability

The present invention relates to a dynamic cylinder having a MOSFET as a constituent element. It is used for manufacturing semiconductor devices such as memory access memories.

Claims

The scope of the claims 1. a step of sequentially forming a semiconductor layer and another conductive layer including a metal material on the main surface of the semiconductor substrate via an oxide film, selectively removing the other conductive layer, and further forming the semiconductor layer to a predetermined thickness. Removing the gate electrode to form a desired pattern of the gate electrode, and selectively forming a sidewall film on the sidewalls of the other conductive film and the semiconductor layer on which the gate electrode has been processed. A method for manufacturing a semiconductor device, comprising: a step of removing the remaining semiconductor layer and the oxide film in conformity with a side wall film; and a step of performing a heat treatment in an oxidizing atmosphere.  2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductive layer is made of polycrystalline silicon, and the other conductive layer is tungsten formed through titanium nitride.  3. a step of sequentially forming a semiconductor layer and another conductive layer containing a metal material on the main surface of the semiconductor substrate via an oxide film;  Depositing a first insulating film on the other conductive layer;  Selectively removing the first insulating film and the other conductive layer, and further removing the semiconductor layer with a predetermined thickness, thereby performing a desired pattern processing;  Selectively forming a first sidewall film on the sidewalls of the first insulating film, the other conductive layer, and the semiconductor layer on which the desired pattern has been processed;  Removing the remaining semiconductor layer and the oxide film in conformity with the sidewall film; By performing a heat treatment in an oxidizing atmosphere, the side portions of the semiconductor layer and Forming an oxide film on a part of the exposed main surface of the semiconductor substrate, and forming a first impurity layer by introducing a first conductivity type impurity into the semiconductor substrate in conformity with the first side wall film. Process and  Forming a second sidewall coating on the surface of the first sidewall coating; and introducing a first conductivity type impurity into the semiconductor substrate in conformity with the second sidewall coating to form a second impurity layer. Forming,  Thereafter, a step of depositing an interlayer insulating film on the main surface of the semiconductor substrate, and a step of aligning the interlayer insulating film with the interlayer insulating film by the second side wall film, (2) forming an opening exposing the surface of the impurity layer; and  Forming a conductive layer that contacts the surface of the second impurity layer through the opening; A method for manufacturing a semiconductor device, comprising:  4. The method of manufacturing a semiconductor device according to claim 3, wherein the semiconductor layer is made of polycrystalline silicon, and the other conductive layer is tungsten formed with titanium nitride.  5. The step of forming the first impurity layer is performed by introducing impurities by arsenic ion implantation, and the step of forming the second impurity layer is performed by introducing impurities by phosphorus ion implantation. 5. The method for manufacturing a semiconductor device according to item 3 or 4. 6. forming an isolation region in a selected area of the semiconductor substrate principal surface;  Forming a gate oxide film on a main surface of the semiconductor substrate partitioned by the isolation region; Sequentially stacking and forming a semiconductor layer and another conductive layer including a metal material; Depositing a first insulating film on the other conductive layer;  A step of selectively removing the first insulating film and the other conductive layer, and further processing the desired pattern by removing the semiconductor layer while keeping a predetermined thickness.  Selectively forming a first sidewall film on the sidewalls of the first insulating film, the other conductive layer, and the semiconductor layer on which the desired pattern has been processed;  Removing the remaining semiconductor layer and the oxide film in conformity with the sidewall film;  Forming an oxide film on a side portion of the semiconductor layer and a part of the exposed main surface of the semiconductor substrate by performing a heat treatment in an oxidizing atmosphere;  Forming a first impurity layer by introducing an impurity of a first conductivity type into the semiconductor substrate in conformity with the first side wall film;  Forming a second sidewall coating on the surface of the first sidewall coating; and introducing a first conductivity type impurity into the semiconductor substrate in conformity with the second sidewall coating to form a second impurity layer. Forming,  Then, a step of depositing an interlayer insulating film on the main surface of the semiconductor substrate, and forming an opening that is aligned with the interlayer insulating film by the second sidewall film and exposes a surface of the second impurity layer. Process, and  Forming a conductive layer contacting the surface of the second impurity layer through the opening; A method for manufacturing a semiconductor device, comprising: 7. In the step of forming the isolation region, a groove having a desired depth is provided in a selected area of the semiconductor substrate main surface, and an insulating film is deposited on the semiconductor substrate main surface including the groove. Thereafter, the insulating film is polished. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the isolation region is formed by burying the insulating film in the trench.  8. The manufacturing method of the semiconductor device according to item 6 or 7, wherein the semiconductor layer is made of polycrystalline silicon, and the other conductive layer is tungsten formed through titanium nitride. Method. 9. A method for manufacturing a semiconductor device including a MOSFET as a constituent element, the method comprising: forming a gate insulating film of the MOSFET on a main surface of a semiconductor substrate; A first patterning step of patterning the insulating film and the conductive laminated film while leaving at least a part of the lowermost polycrystalline silicon; and Forming a first insulating sidewall film on the film and a part of the lowermost polycrystalline silicon; and forming a part of the lowermost polycrystalline silicon which is not patterned by the above-mentioned patterned polycrystalline silicon. (1) A method for manufacturing a semiconductor device, comprising: a second buttering step of patterning using an insulating sidewall film as a mask.  10. The method according to item 9, wherein after the second patterning step, a step of forming a film made of a silicon oxide film on the exposed surface of the polycrystalline silicon by a thermal oxidation method is included. The manufacturing method of the semiconductor device described in the above. 11. The method according to claim 9, wherein after the second patterning, a second insulating sidewall film is formed to cover the first insulating sidewall film and the lowermost polycrystalline silicon. A method for manufacturing a semiconductor device. 12. After forming a film made of a silicon oxide film on the exposed polycrystalline silicon surface by a thermal oxidation method, the first insulating side wall film and the first insulating sidewall film are formed. 10. The method for manufacturing a semiconductor device according to claim 9, wherein a second insulating sidewall film is formed so as to cover the silicon oxide film formed on the surface of the lowermost polycrystalline silicon.  13. The step of forming a plurality of conductor laminated films in which the polycrystalline silicon layer is the lowermost layer comprises, after forming the polycrystalline silicon film, forming a metal film, a metal nitride film or a metal silicide film. 10. The method for manufacturing a semiconductor device according to claim 9, wherein at least one of them is formed.  1. The step of forming a plurality of conductive laminated films having a polycrystalline silicon layer as a lowermost layer includes, after forming the polycrystalline silicon film, depositing a metal film on the polycrystalline silicon film and performing a heat treatment. 10. The method of manufacturing a semiconductor device according to claim 9, wherein the method includes forming a metal silicide film.  15. The method of manufacturing a semiconductor device according to item 9, wherein the first insulating side wall film is an insulating film containing silicon nitride in its composition.  16. The method for manufacturing a semiconductor device according to item 12, wherein the second insulating sidewall film is an insulating film containing silicon nitride in its composition.  17. A step of forming a semiconductor film on the base;  Patterning the semiconductor film by etching away the first region of the semiconductor film so that a predetermined film thickness remains;  Forming an insulating film on the pattern side wall of the semiconductor film in the first region. 18. The method of manufacturing a semiconductor device according to claim 17, wherein the predetermined film thickness is 5 nm or more. 1 9. A step of forming an insulating film on the base,  Forming an electrode film on the insulating film;  Processing the electrode film by etching and removing the second region so as to leave a predetermined thickness while leaving the first region of the electrode film; and an insulating film on a side wall of the electrode in the first region. Forming an electrode in the second region by etching, and exposing the oxide film in the second region.  Removing the oxide film in the second region by wet etching. 20. The method for manufacturing a semiconductor device according to item 19, wherein the electrode film is formed of a laminated film of a semiconductor film and another conductive film.