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WO1998036497A1 - Circuit d'attaque de bus equipe d'un circuit temoin de vitesse de balayage pourvu d'une serie d'elements retard - Google Patents

Circuit d'attaque de bus equipe d'un circuit temoin de vitesse de balayage pourvu d'une serie d'elements retard Download PDF

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Publication number
WO1998036497A1
WO1998036497A1 PCT/US1998/003364 US9803364W WO9836497A1 WO 1998036497 A1 WO1998036497 A1 WO 1998036497A1 US 9803364 W US9803364 W US 9803364W WO 9836497 A1 WO9836497 A1 WO 9836497A1
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WO
WIPO (PCT)
Prior art keywords
pvt
slew rate
code
signal
delay elements
Prior art date
Application number
PCT/US1998/003364
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English (en)
Inventor
Bruno Garlepp
Original Assignee
Rambus, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus, Inc. filed Critical Rambus, Inc.
Publication of WO1998036497A1 publication Critical patent/WO1998036497A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Definitions

  • the present invention relates generally to the field of communication buses and more particularly to a bus driver circuit having slew rate control.
  • a parallel data bus typically comprises a number of bus lines to which the components of a computer system may be connected for communicating information between one another.
  • Each component coupled to the data bus typically includes a set of bus driver circuits for transmitting data via the bus lines by switching the voltages of the bus lines between voltages that correspond to logic states, however defined.
  • the speed at which a bus driver circuit switches the voltages of the bus line between logic states is called the "slew rate,” and the slew rate of the bus driver circuit is an extremely important characteristic for ensuring proper operation of the bus driver circuit at the clock speed of the data bus.
  • FIG. 1 shows a bus driver circuit 100 that operates according to the prior art.
  • Bus driver circuit 100 is shown as comprising NAND gate 105, pass gate 110, inverter 115, and an output buffer 120, which is shown as comprising an n-channel transistor having its source coupled to system ground VSS and its drain coupled to bus line 150.
  • a terminating resistor 125 is shown as being coupled between bus line 150 and a " terminating supply voltage V t erm- NAND gate 105 operates as an input buffer and has a first input coupled to receive a data signal DATA and a second input coupled to receive an enable signal EN.
  • NAND gate 105 operates as an inverter for inverting the DATA signal to produce an inverted data signal DATA.
  • Pass gate 110 is switched on to pass the DATA signal in response to the high level of transmit clock signal TCLK.
  • Inverter 115 receives the DATA signal and inverts it to provide a drive signal DRIVE at the input of output buffer 120.
  • Output buffer 120 is switched on to drive bus line 150 to a low voltage causing the output signal OUT to have a low voltage value when the DRIVE signal is logic high.
  • Output buffer 120 is switched off when the DRIVE signal is a logic low, and the bus line 150 is charged to the terminating voltage Vterm in response to terminating resistor 125, causing the OUT signal to have a high voltage value.
  • the slew rate of the output signal OUT is determined by the slew rate of the DRIVE signal.
  • the nominal slew rate of the DRIVE signal is known because the device sizes of inverter 115 are specified to have known values; however, variations in device sizes and device parameters (e.g. gain and threshold voltage) can occur when fabricating a semiconductor device. Therefore, the actual slew rate of the DRIVE signal may vary from the nominal slew rate due to such "process" variations, and the slew rate of the OUT signal is similarly affected. Furthermore, temperature and power supply variations that occur during operation of bus driver circuit 100 can also affect the slew rate.
  • bus driver circuit 100 may induce undesirable ringing on the bus line and voltage transients or "ground bounce" on the supply lines due to, for example, inductance of an integrated circuit package housing bus driver circuit 100 (i.e., inductance due to bond wires, the lead frame, etc.). If the actual slew rate of the DRIVE and OUT signals are too much less than their nominal values, bus driver circuit 100 may not be able to reliably operate at the frequency of the bus clock. The ability to control slew rate variations of a bus driver circuit is therefore desirable.
  • the bus driver circuit includes a slew rate indicator circuit having a process-voltage-temperature detector (PVT) circuit.
  • the PVT detector circuit includes a plurality of delay elements coupled in a chain, wherein the plurality of delay elements are configured to receive a trigger signal that propagates through the delay elements for a predetermined period of time.
  • the delay elements generate a process-voltage-temperature (PVT) code at the end of the predetermined period of time.
  • the PVT code corresponds to PVT operating conditions of the PVT detector circuit.
  • the PVT code varies with the PVT operating conditions of the PVT detector circuit and the bus driver circuit, and may affect the slew rate of the bus driver circuit.
  • Figure 1 shows a bus driver circuit that operates according to the prior art
  • Figure 2 shows an improved bus driver circuit according to one embodiment
  • Figure 3 shows a three-state inverter according to one embodiment
  • Figure 4 shows a slew rate indicator circuit of one embodiment
  • Figure 5 is a timing diagram that illustrates the manner of operation for the slew rate indicator of Figure 4 according to one embodiment
  • Figure 6A shows an alternative embodiment wherein two three- state inverters are provided in place of the single three-state inverter shown in Figure 2;
  • Figure 6B shows another embodiment wherein two three-state inverters are provided in place of the single three-state inverter shown in Figure 2;
  • Figure 7 shows one embodiment of a slew rate indicator circuit for controlling the three-state inverters of Figure 6A;
  • Figure 8 is a timing diagram that illustrates the relationship between the clock and sampling signals of one embodiment of Figure 7 and also shows waveforms "D,” "E,”, “F”, “G” and “H”;
  • Figure 9A shows one embodiment of the NMOS one-shot circuit of Figure 7;
  • Figure 9B is a timing diagram that illustrates one embodiment for the manner of operation of NMOS one-shot circuit of Figure 9A;
  • Figure 10A shows one embodiment of the PMOS one-shot circuit of Figure 7;
  • Figure 10B is a timing diagram that illustrates one embodiment for the manner of operation of PMOS one-shot circuit of Figure 10 A;
  • Figure 11 A shows combinational logic 710 according to one embodiment
  • Figure 11B shows combinational logic 710 according to another embodiment
  • Figure 12 shows another embodiment of a slew rate indicator circuit including a PVT code generator and combinational logic
  • Figure 13 shows one embodiment of the combinational logic of Figure 12
  • Figure 14A shows one embodiment of a tracking circuit having biasing voltages
  • Figure 14B shows another embodiment of a tracking circuit having biasing voltages
  • Figure 15 shows one embodiment of a slew rate indicator circuit including sampling circuitry
  • Figure 16 shows another embodiment of a slew rate indicator circuit including a control circuit, a PVT code generator, and a PVT code interpreter
  • Figure 17A shows one example of the slew rate indicator of Figure 16 including a control circuit, an NMOS PVT code generator, an NMOS PVT code interpreter, a PMOS PVT code generator, and a PMOS PVT code interpreter;
  • Figure 17B shows one embodiment of the process of operating the slew rate indicator of Figure 17A
  • Figure 18A shows one embodiment of the NMOS PVT code generator and the NMOS PVT code interpreter of Figure 17A;
  • Figure 18B show timing diagrams that illustrate exemplary waveforms for the RUN, PVTRST, and FIRE signals of Figure 18 A;
  • FIGS 19A-19C show timing diagrams that illustrate exemplary embodiments for the manner of operation of the NMOS PVT code generator and the NMOS PVT code interpreter of Figure 18A;
  • Figure 20 shows one embodiment of two of the delay elements of Figure 18A
  • Figure 21 shows one embodiment of an equivalent circuit of three-state inverter 225 and output buffer 220.
  • Figure 22 shows a NMOS transistor curve of Ids v. Vds.
  • An improved bus driver circuit including a slew rate indicator circuit and a three-state inverter are used to correct or adjust the slew rate of the bus driver circuit in response to changes in operating conditions (e.g., process, temperature, and power supply variations) that cause the slew rate to decrease to an unacceptable rate.
  • the improved bus driver circuit may drive a bus line or any other signal line.
  • the slew rate indicator is manufactured on the same semiconductor substrate according to the same process as the remainder of the bus driver circuit. The slew rate indicator is therefore subject to the same process variations and operating environment as the remainder of the bus driver circuit. This enables the slew rate indicator to track and compensate for slew rate variations as they occur. Thus, as will be described, the range of values across which the slew rate of bus driver circuit may vary is reduced.
  • Bus driver circuit 200 generally comprises NAND gate 205, pass gate 210, inverter 215, output buffer 220, and slew rate control circuit 260.
  • Slew rate control circuit 260 includes slew rate indicator 230 and a pre-driver circuit, namely three-state inverter 225.
  • output buffer 220 comprises an n-channel transistor having its source coupled to system ground VSS, its drain coupled to bus line 250, and its gate coupled to receive a DRIVE signal from inverters 215 and 225.
  • Output buffer 220 may alternatively comprise an inverter wherein the output of the inverter sets the voltage of bus line 250. Terminating resistor 255 may not be required when output buffer 220 comprises an inverter.
  • bus driver circuit 200 operates in substantially the same manner as bus driver circuit 100 shown in Figure 1.
  • Slew rate control circuit 260 receives clock signal CLK and affects the slew rate of the DRIVE signal output by inverter 215, and the OUT signal on bus line 250 in response to variations in the operating conditions of bus driver circuit 200. As will be described in more detail below, when operating conditions (e.g., process parameters, operating temperature, operating voltage, etc.) cause the slew rate of the DRIVE signal to decrease to a predetermined rate, then slew rate control circuit 260 increases the slew rate of the DRIVE signal and consequently the slew rate of the OUT signal. The slew rates of the DRIVE and OUT signals are adjusted without the use of a feedback connection from the DRIVE or OUT signal to slew rate control circuit 260.
  • operating conditions e.g., process parameters, operating temperature, operating voltage, etc.
  • Three-state inverter 225 is coupled in parallel with inverter 215 and is provided to increase the slew rate of the DRIVE signal by providing more current if the actual slew rate of the DRIVE signal would otherwise be slower than the nominal slew rate.
  • Three-state inverter 225 is disabled if the actual slew rate of the DRIVE signal is greater than or equal to the nominal slew rate.
  • Inverter 215 may be designed so that the slew rate of the DRIVE signal is not too fast under worst case operating conditions (e.g., fast process parameters, cold operating temperatures, high operating voltages) when three-state inverter 225 disabled.
  • a digital slew rate control signal SRCTL output by slew rate indicator 230 is provided to enable and disable three-state inverter 225.
  • Slew rate indicator 230 may be considered a process-voltage- temperature or "PVT" detector circuit.
  • Slew rate indicator 230 is provided to indicate whether variations in the fabrication process (e.g., transistor dimensions, dielectric dimensions, thresholds, gain, etc.), supply voltage, input voltage, or operating temperature result in variations in the slew rate of the DRIVE or OUT signals of bus driver circuit 200.
  • slew rate indicator 230 indicates that variations in operating or PVT conditions would otherwise cause the slew rate of the DRIVE signal to be too slow, slew rate indicator 230 causes the SRCTL signal to enable three-state inverter 225. If slew rate indicator 230 indicates that operating or PVT conditions may cause the slew rate of the DRIVE signal to be equal to or faster than the nominal slew rate, slew rate indicator 230 causes the SRCTL signal to disable three-state inverter 225. Because the slew rate of bus driver circuit 200 is prevented from being too slow, the range of values across which the actual slew rate of the DRIVE signal may vary is reduced. For one embodiment, the range is reduced to approximately one-half the range without slew rate indicator 230 and three-state inverter 225.
  • three-state inverter 225 and inverter 215 may be replaced with non-inverting buffers and bus driver circuit 200 may be adjusted as generally known in the art.
  • Slew rate control circuit 260 may influence the slew rates of the rising or falling edge transitions of the DRIVE signal and the OUT signal.
  • slew rate control circuit 260 may cause the slew rates of the rising and falling edges of the DRIVE signal to increase by 30-40% at the slowest operating corner (e.g., slow process parameters, high operating temperatures such as 130°C, and low operating voltages such as 2.9 V).
  • three-state inverter 225 may be sized to produce any desired increase in the slew rates of either the rising or falling edge of the DRIVE signal.
  • the slew rates of the rising and falling edges of the DRIVE signal of bus driver circuit 100 at the slowest operating corner may be approximately three times slower than the slew rates of the rising and falling edges of the DRIVE signal at the fastest operating corner (e.g., fast process parameters, cold operating temperatures such as 25°C, and high operating voltages such as 3.7 V).
  • the slew rates of the rising and falling edges of the DRIVE signal of bus driver circuit 200 at the slowest operating corner may be approximately 1.5 times slower than the slew rates of the rising and falling edges of the DRIVE signal at the fastest operating corner. Therefore, there may be an approximately 2X improvement in the comparison between the slew rates of the rising and falling edges at the fast and slow operating corners using slew rate control circuit 260.
  • Slew rate control circuit 260 may also affect the duty cycle of the DRIVE signal and consequently the OUT signal.
  • the duty cycle may be altered by designing three-state inverter 225 to asymmetrically influence the slew rate of either the rising edge or the falling edge of the DRIVE signal in response to particular PVT operating conditions. This will be described in more detail below.
  • the duty cycle of the DRIVE signal may vary with PVT operating conditions. Slew rate control circuit 260 may decrease this variability by appropriately controlling three-state inverter 225. For one embodiment, the variability of the duty cycle of the DRIVE signal of bus driver circuit 200 between the slowest operating corner and the fastest operating corner may be reduced approximately 1.5 to 2.0 times over the DRIVE signal of bus driver circuit 100. Additionally, the duty cycle error (i.e., actual duty cycle relative to a 50% duty cycle) of the DRIVE signal of bus driver circuit 200 may be decreased over the DRIVE signal of bus driver circuit 100. Furthermore, the duty cycle of the DRIVE signal of bus driver circuit 200 may be centered about a desired 50% duty cycle across PVT operating conditions.
  • Three-state inverter 225 generally includes a CMOS pair of transistors comprising p-channel transistor 305 and n-channel transistor 310 having their gates coupled to an input node 301 for receiving the DATA signal and their drains coupled to an output node 302 for strengthening the DRIVE signal when three-state inverter 225 is enabled.
  • transistors 305 and 310 are approximately the same size as the respective devices of the CMOS transistor pair of inverter 215.
  • Three-state inverter 225 further includes a three-state transistor pair comprising a p-channel transistor 315, which is coupled between the source of p-channel transistor 305 and the operating supply voltage VDD, and an n-channel transistor 320, which is coupled between the source of n-channel transistor 310 and system ground VSS.
  • slew rate control signal SRCTL is coupled directly to the gate of n- channel transistor 320
  • an inverter 325 is provided for supplying an inverted SRCTL signal to the gate of p-channel transistor 315.
  • SRCTL may be coupled directly to the gate of p-channel transistor 315 and inverter 325 may be provided for supplying an inverted SRCTL signal to the gate of n-channel transistor 320.
  • a slew rate indicator circuit may not be required.
  • a fuse may be inserted between VDD and the SRCTL signal line, and the fuse may be blown if an increased slew rate is not required.
  • Other known types of programmable elements besides a fuse may also be used.
  • Figure 4 shows one embodiment of slew rate indicator circuit 230 including one-shot circuit 405 coupled in series with clocked comparator circuit 410.
  • One-shot circuit 405 is configured to generate a pulse in response to detecting a rising edge of a reference clock signal CLK, which is provided at the input of one-shot circuit 405. Under normal operating conditions, one-shot circuit 405 is designed to generate a pulse having a nominal pulse width that is approximately equal to half of the period of the reference clock signal CLK.
  • One-shot circuit 405 may have any appropriate CMOS architecture, and other pulse generating circuits may alternatively be used.
  • Clocked comparator circuit 410 has a first input coupled to output 407 of one-shot circuit 405, a second input coupled to a reference voltage, and an enable input coupled to the reference clock signal CLK. According to the embodiment of Figure 4, the reference voltage is equal to one-half of the operating supply voltage VDD. Clocked comparator circuit 410 is enabled to compare the output of one-shot circuit 405 to the reference voltage upon detecting a falling edge of the reference clock signal CLK.
  • Figure 5 is a timing diagram showing the manner of operation for a slew rate indicator according to one embodiment under various operating conditions.
  • one-shot circuit 405 generates a pulse for each rising edge of the reference clock signal, and the nominal pulse width of the pulse output from one-shot circuit 405 is equal to approximately one-half the period of the reference clock signal CLK.
  • one-shot circuit 405 is manufactured using the same process as the remainder of bus driver circuit 200 and because one-shot circuit 405 is operating in the same environment as the remainder of bus driver circuit 200, the width of the pulse generated by one-shot signal 405 on output 407 varies with process, temperature, and supply voltage variations, and the pulse width of the pulse output by one-shot circuit 405 substantially tracks the slew rate of the DRIVE signal and the OUT signal. For example, when a short pulse width occurs at output 407, the output slew rate will be faster than the nominal slew rate. For one embodiment, a short pulse occurs when bus driver circuit 200 circuit is operating under fast operating conditions (e.g., fast process parameters, cold operating temperatures, and /or high operating voltages).
  • fast operating conditions e.g., fast process parameters, cold operating temperatures, and /or high operating voltages.
  • a long pulse width occurs at output 407, the slew rate of the DRIVE signal and the OUT signal will be slower than the nominal stew rate.
  • a long pulse occurs when bus driver circuit 200 circuit is operating under slow operating conditions (e.g., slow process parameters, hot operating temperatures, and /or low operating voltages).
  • Clocked comparator 410 samples the PVT sensitive pulse on output 407 upon detecting a falling edge of CLK.
  • Figure 5 shows a reference clock waveform CLK, an "A" waveform indicative of a fast slew rate wherein the width of the pulse is less than half the period of CLK, a "B” waveform indicative of a typical slew rate wherein the width of the pulse is approximately equal to half the period of CLK, a "C” waveform indicative of slow slew rate wherein the width of the pulse is more than half the period of CLK, a "D” waveform indicative of the SRCTL signal generated in response to waveforms A or B and CLK, and an "E” waveform indicative of the SRCTL signal generated in response to waveform C and CLK.
  • Waveforms A-C are taken from output 407 of one-shot circuit 405, as shown in Figure 4.
  • clocked comparator circuit 410 detects the output of one-shot circuit 405 as being a logic low voltage at the falling edge of CLK, and clocked comparator circuit 410 deasserts the SRCTL signal to a logic low value as indicated by waveform D.
  • Three-state inverter 225 is thus disabled, and inverter 215 alone determines the slew rate of the DRIVE and OUT signals of bus driver circuit 200.
  • one-shot circuit 405 outputs the pulse shown by waveform B
  • the falling edge of the pulse output by one-shot circuit 405 approximately matches the falling edge of reference clock signal
  • the output of clocked comparator circuit 410 may become metastable because the voltage of the pulse may be indeterminate.
  • a positive feedback connection may be placed between the output of clocked comparator 410 and the input of clocked comparator 410 coupled to node 407 to reduce the duration of metastability. Other techniques may be used to reduce the duration of metastability or eliminate the metastable condition.
  • clocked comparator circuit 410 detects the output of one-shot circuit 405 as being a logic high voltage at the falling edge of CLK, and clocked comparator circuit 410 asserts the SRCTL signal to a logic high value as indicated by waveform E.
  • Three-state inverter 225 is thus enabled to strengthen the output current of the DRIVE signal and increase the slew rate of DRIVE and OUT signals of bus driver circuit 200.
  • slew rate indicator 230 can operate continuously to track environmental changes, the SRCTL signal should be updated only when no data is being transmitted. This may be done, for example, by supplying the enable signal EN shown in Figure 2 to clocked comparator circuit 410 to prevent clocked comparator circuit 410 from sampling the output of one-shot circuit 405 when the enable signal EN is active high.
  • a latch may be supplied at the output of clocked comparator circuit 410 for latching the value of the SRCTL signal and for supplying the SRCTL signal when clocked comparator circuit 410 is disabled.
  • the range of values across which the slew rate of bus driver circuit 200 may vary may be further decreased by providing any number of additional three-state inverters and slew rate indicator circuits. For example, separate control signals may be provided to individually control the NMOS and PMOS devices of three-state inverter 225.
  • the n-channel and p-channel transistors of a CMOS circuit are typically fabricated using different process steps. Therefore, each of the n-channel and p-channel transistors may be independently subject to different process variations. Thus, the p-channel transistors may be slow (i.e., the p-channel transistors may source less current than expected) when the n-channel transistors are fast (i.e., the n-channel transistors may sink more current than expected), and the n-channel transistors may be slow when the p-channel transistors are fast.
  • the arrangements illustrated by Figures 2-5 generally correct for a reduced slew rate without regard to whether it is the n-channel transistors or the p-channel transistors that are responsible for the reduced slew rate.
  • Figure 6A shows an alternative embodiment wherein two pre- driver circuit, namely three-state inverters 225A and 225B are provided in place of the single three-state inverter 225 shown in Figure 2.
  • Each of three-state inverters 225A and 225B are controlled independently of one another by slew rate indicator circuit 700 shown in Figure 7. In this manner, slew rate variations due to n-channel process steps and p- channel process steps may be separately addressed.
  • the three-state inverters of Figure 6A may be configured to increase the slew rate of the DRIVE signal, if required.
  • inverter 215 ( Figure 2) may be selected to provide the slowest desirable slew rate, and the n-channel and p-channel devices of three-state inverters 225A and 225B may be switched on if the slew rate indicator circuit of Figure 7 determines that an increased slew rate is required.
  • three-state inverter 225A may be configured to be enabled when the slew rate of the DRIVE signal is in a nominal or typical range.
  • three-state inverter 225 A may be disabled.
  • the p-channel of n-channel transistors of three-state inverter 225A (or 225B) may be individually disabled.
  • three-state inverter 225A may be configured to enabled while the three-state inverter 225B (or 225 A) may be configured to be disabled when the slew rate of the DRIVE signal is in a nominal or typical range.
  • three-state inverter 225A may be disabled.
  • slew rate indicator 700 indicates that operating or PVT conditions cause the slew rate of the DRIVE signal to decrease beyond an acceptable amount
  • three-state inverter 225B may be enabled.
  • only the p-channel of n-channel transistors of three-state inverters 225A or 225B may be individually enabled or disabled.
  • Three-state inverter 225A comprises p-channel transistor 605, n- channel transistor 610, p-channel transistor 615, and n-channel transistor 620.
  • Transistors 605 and 610 have their drains coupled in common to an output node 601 to supplement the DRIVE signal output by inverter 215, when enabled. As shown, the gates of transistors 605 and 610 are independently controlled by slew rate control signals P0 and NO, respectively.
  • Transistor 615 has its drain coupled to the source of transistor 605, its source coupled to operating supply voltage VDD, and its gate coupled to input node 602 for receiving the DATA signal.
  • Transistor 620 has its drain coupled to the source of transistor 610, its source coupled to system ground VSS, and its gate coupled to input node 602 for receiving the DATA signal.
  • Three-state inverter 225B comprises p-channel transistor 625, n- channel transistor 630, p-channel transistor 635, and n-channel transistor 640.
  • Transistors 625 and 630 have their drains coupled in common to output node 601 to supplement the DRIVE signal output by inverter 215, when enabled. As shown, the gates of transistors 625 and 630 are independently controlled by slew rate control signals PI and Nl, respectively.
  • Transistor 635 has its drain coupled to the source of transistor 625, its source coupled to operating supply voltage VDD, and its gate coupled to input node 602 for receiving the DATA signal.
  • Transistor 640 has its drain coupled to the source of transistor 630, its source coupled to system ground VSS, and its gate coupled to input node 602 for receiving the DATA signal.
  • Transistors 605, 610, 625, and 630 may be sized (e.g., width and length dimensions) to approximately source or sink the same or different amounts of current as corresponding transistors in inverter 215.
  • each of transistors 605, 610, 625, and 630 may be sized to source or sink different amounts of current.
  • transistors P0 and PI may be sized to increase (or decrease) the amount of current sourced to the DRIVE signal in a geometric manner (e.g., in a pattern of lx, 2x, 4x, etc. of the current supplied by inverter 215.
  • transistors NO and Nl may be sized to increase (or decrease) the amount of current sourced to the DRIVE signal in a geometric manner.
  • FIG. 7 shows a slew rate indicator circuit 700 for controlling inverters 225A and 225B shown in Figure 6A.
  • Slew rate indicator circuit 700 includes a PVT code generator circuit 712 that includes NMOS one-shot circuit 701, PMOS one-shot circuit 702, clocked comparator circuits 703-706, and combinational logic 710.
  • Slew rate indicator circuit 700 may be a PVT detector circuit that generates a PVT code represented by signals W, X, Y, and Z which may be translated by combinational logic 710 to an SRC code represented by signals NO, Nl, PO, and PI . Changes in operating or PVT conditions may cause changes in the PVT code.
  • PVT code generator circuit 712 is a sampling circuit that receives the FIRE signal and generates PVT sensitive pulses U and V. Pulses U and V are then sampled by clocked comparators 703-706 in response to sampling signals SAMP1 and SAMP2 generated at predetermined delays from the FIRE signal. Providing more sample points and /or sample signals may increase the resolution of the PVT code generated by PVT code generator circuit 712.
  • NMOS one-shot circuit 701 outputs pulse U in response to detecting the rising edge of the FIRE signal.
  • PMOS one-shot circuit 702 outputs pulse V in response to detecting the rising edge of the FIRE signal.
  • NMOS one-shot circuit 701 is manufactured entirely of n-channel transistors for detecting process variations for n-channel devices independently of the p-channel process.
  • PMOS one-shot circuit 702 may be manufactured entirely of p-channel transistors for detecting process variations for p- channel devices independently of the n-channel process.
  • Clocked comparators 703 and 704 are coupled to the output of NMOS one-shot circuit 701, and clocked comparators 705 and 706, coupled to the output of PMOS one-shot circuit 702.
  • Clocked comparators 703-706 compare VDD/2, or any other reference voltage, with either U or V and generate the PVT code as signals W-Z.
  • Clocked comparator 703 is enabled to sample the output of NMOS one-shot circuit 701 in response to the falling edge of a SAMP1 signal and outputs the W signal;
  • clocked comparator 704 is enabled to sample the output of NMOS one-shot circuit 701 in response to the falling edge of a SAMP2 signal and outputs the X signal;
  • clocked comparator 705 is enabled to sample the output of PMOS one-shot circuit 702 in response to the falling edge of a SAMP1 signal and outputs the Y signal;
  • clocked comparator 706 is enabled to sample the output of PMOS one- shot circuit 702 in response to the falling edge of a SAMP2 signal and outputs the Z signal.
  • Combinational logic 710 translates the PVT codes produced by PVT code generator 712 as signals W-Z into appropriate SRC codes (signals NO, Nl, PO, and PI) for enabling or disabling transistors 605, 610, 625, and 630 in order to maintain the output slew rate of the DRIVE signal within desirable limits.
  • SRC codes signals NO, Nl, PO, and PI
  • a change in the PVT code due to changes in PVT operating conditions would cause a corresponding change in the SRC code.
  • the W-Z signals may be directly mapped to the N0-N1 and P0-P1 control signals as follows: NO is coupled to W; Nl is coupled to X; PO is coupled to the logical inverse of Y; and PI is coupled to the logical inverse of Z.
  • combinational logic 710 may simply comprise inverters for inverting Y and Z.
  • combinational logic 710 can be designed to process the PVT codes and generates desirable SRC codes, that is, the PVT codes generated under certain PVT operating conditions may be re-mapped or error-corrected to desirable SRC codes by combinational logic 710. Implementations of more complicated mapping using combinational logic 710 are discussed below with respect to figures HA and 11B.
  • the FIRE, SAMP1, and SAMP2 signals are pulses generated by a synchronous counter or a control circuit (not shown) that operates in response to the reference clock signal CLK.
  • a synchronous counter or a control circuit (not shown) that operates in response to the reference clock signal CLK.
  • the pulse width of the FIRE signal is longer than that of the SAMP2 signal, which is longer than that of the SAMP1 signal.
  • the NMOS and PMOS one-shot circuits 701 and 702 are designed such that the falling edges of U and V will typically fall within a window defined by the falling edges of the SAMPl and SAMP2 signals for nominal process conditions.
  • the SAMPl and SAMP2 signals may have different pulse widths than that described above.
  • SAMPl and /or SAMP2 may have a pulse width of one or more clock (CLK) cycles which may occur at predetermined delays after the FIRE signal has been asserted.
  • Clocked comparators 703-706 may sample the U and V pulses in response to either the rising edge or the falling edge of the SAMPl or SAMP2 signals.
  • Waveform D indicates a fast slew rate indicative of fast operating conditions (e.g., fast process parameters, cold operating temperatures, and /or high operating voltages).
  • Waveform E indicates a normal /nominal slew rate indicative of normal operating conditions (e.g., nominal process parameters, nominal operating temperatures, and /or nominal operating voltages).
  • Waveform F indicates a slow slew rate indicative of slow operating conditions (e.g., slow process parameters, hot operating temperatures, and /or low operating voltages).
  • Waveforms D-F represent possible outputs U and V from NMOS and PMOS on-shot circuits 701 and 702, respectively.
  • the nominal pulse width of waveform E may span multiple clock periods of reference clock signal CLK. For one embodiment, waveform E spans approximately eight (8) clock periods of reference clock signal CLK.
  • Clocked comparators 703-706 are enabled to sample the outputs of their corresponding one-shot circuits at the falling edge of either the SAMPl or SAMP2 signals.
  • waveforms D-F By comparing waveforms D-F to the falling edges of the SAMPl and SAMP2 signals, the following observations are made: 1) the pulse of waveform D will be detected as a logic low by comparators clocked by either the SAMPl or SAMP2 signal; 2) the pulse of waveform E will be detected as a logic high by a comparator clocked by the SAMPl signal and as a logic low by a comparator clocked by the SAMP2 signal; and 3) the pulse of waveform F will be detected as a logic high by comparators clocked by either the SAMPl or SAMP2 signal.
  • Waveform G corresponds to one embodiment of signal W output by comparator 703 or signal Y output by comparator 705 in response to waveforms E or F.
  • waveform G will transition to a high level if waveforms U or V are a high level at the falling edge of SAMPl, that is, when either waveform E or F is high at the falling edge of SAMPl.
  • Waveform H corresponds to one embodiment of signal X output by comparator 704 or signal Z output by comparator 706 in response to waveform F.
  • waveform H will transition to a high level if waveforms U or V are a high level at the falling edge of SAMP2, that is, when waveform F is high at the falling edge of SAMP2.
  • Figure 8 illustrates, for example, that if operating or PVT conditions indicate that the slew rate of the DRIVE signal is slower than desired, then the PVT code generated by PVT code generator 712 as signals W-Z will be 1111. Combinational logic 710 may then translate this PVT code into an SRC code equal to 1100 for signals NO, Nl, P0, and PI, respectively. This will cause three-state inverters 225A and 225B to be enabled to increase the slew rate of the DRIVE signal.
  • the PCT code generated by PVT code generator 712 and the translation performed by combinational logic 710 may be altered such that one or both of three- state inverters 225A or 225B is enabled or disabled when a slew rate other than a nominal slew rate of the DRIVE signal is indicated by the given PVT operating conditions.
  • FIG. 9A shows NMOS one-shot circuit 701 according to one embodiment.
  • NMOS one-shot circuit 701 includes n-channel transistors 901-903, NAND gate 910, and inverter 915.
  • An input node 907 is coupled to receive the FIRE signal.
  • the input node 907 is also coupled to the gate of transistor 901 and to one input of NAND gate 910.
  • the other input of NAND gate 910 is coupled to node 908.
  • Transistor 902 is diode-connected for biasing node 908 to a logic high value when switching transistor 901 is switched off.
  • Transistor 903 is configured as an MOS capacitor. Together, transistors 901-903 determine the rate at which node 908 is charged and discharged.
  • FIG. 9B shows the operation of NMOS one-shot circuit 701.
  • the FIRE signal transitions from a low level to a high level which causes output waveform U to be asserted to a high level.
  • the voltage on node 908 starts to drop towards Vss as the charge stored on transistor 903 discharges through transistor 901.
  • the voltage on node 908 reaches the trip point of NAND gate 910, and output waveform U is deasserted, or drops to a low level.
  • node 908 is fully discharged to VSS-
  • FIG. 10 A shows a PMOS one-shot circuit 702 of one embodiment in more detail.
  • PMOS one-shot circuit 702 comprises transistors 1001-1003, NAND gate 1010, and inverter 1015.
  • Transistors 1001-1003 are all PMOS transistors and operate substantially like transistors 901-903 of NMOS one-shot circuit 701. Thus, it may be seen that the charging and discharging of node 1008 and the output waveform V depends entirely on the PMOS process.
  • FIG. 10B shows the operation of NMOS one-shot circuit 701.
  • the FIRE signal transitions from a low level to a high level which causes output waveform V to be asserted to a high level.
  • the voltage on node 1008 starts to drop towards Vss as the charge stored on transistor 1003 discharges through transistor 1002.
  • the voltage on node 1008 reaches the trip point of NAND gate 1010, and output waveform V is deasserted, or drops to a low level.
  • node 1008 is fully discharged to VSS-
  • combinational logic 710 may re-map certain PVT codes to different SRC codes in response to PVT operating conditions previously determined to cause undesirable PVT codes.
  • Figure HA shows one embodiment of combinational logic 710 for mapping PVT codes generated under particular PVT operating conditions to desired SRC codes based on simulation data.
  • Combinational logic 710 of Figure HA is shown as including NOR gates 1101, 1108, and 1114, NAND gates 1102-1107 and 1109-1111, and inverters 1112-1113 and 1115 to 1122.
  • the output signals W-Z of clocked comparators 703-706 are coupled to the logic gates as shown.
  • Table 1 summarize how the logic of Figure 11 A may be derived.
  • Table 1 shows simulation conditions for PVT conditions including process (P), operating voltage (V), and temperature (T).
  • the first letter refers to fast (F), slow (S), or typical (T) NMOS process parameters
  • the second letter refers to PMOS process parameters.
  • optimal or desired SRC codes are determined for three-state inverters 225 A and 225B based on simulated PVT conditions. These results are tabulated in columns four through seven.
  • the PVT codes generated by PVT code generator circuit 712 are simulated under the same PVT conditions. These results are summarized in columns eight through eleven.
  • the logic can be readily designed to translate the PVT codes to the desired SRC codes or close to the SRC codes.
  • the logic of Figure HA is tabulated in columns twelve through fifteen.
  • Table 1 Figure 11B illustrates combinational logic 1128 that is another embodiment of combinational logic 710.
  • Combinational logic 1128 receives the PVT code signals W-Z and generates the SRC code signals NO, Nl, PO, and PI.
  • Combinational logic 1128 includes inverters 1130- 1137, two-input AND gates 1140 and 1141, and three-input AND gates 1138 and 1139.
  • Inverters 1130 and 1134 generate Nl having the same state as signal X.
  • Inverters 1131 and 1135 generate NO having the same state as signal W.
  • Two-input AND gate 1140 outputs PI and has one input coupled to Z via inverters 1132 and 1136, and the other input coupled to the output of three-input AND gate 1138.
  • Three-input AND gate 1138 has a first input coupled to the output of inverter 1130 to receive X', a second input coupled to W, a third input coupled to Y.
  • Two-input AND gate 1141 outputs PO and has one input coupled to Y via inverters 1133 and 1137, and the other input coupled to the output of three-input AND gate 1139.
  • Three-input AND gate 1139 has a first input coupled to the output of inverter 1130 to receive X', a second input coupled to the output of inverter 1131 to receive W, and a third input coupled to the output of inverter 1132 to receive Z'.
  • Figure HB may be generated is a similar fashion to that described above with respect to Figure HA and Table 1.
  • Table 2 summarizes the data for generating the logic of Figure HB.
  • Slew rate indicator 1200 may also be considered a PVT detector that generates varying SRC code signals in response to changes in PVT operating conditions of a device or system containing bus driver circuit 200 and slew rate indicator 1200.
  • Slew rate indicator 1200 may generate an SRC code for two three-state inverters or any number of three state inverters coupled in parallel with inverter 215 of Figure 2.
  • Slew rate indicator 1200 includes PVT code generator circuit 1230 and combinational logic 1210. As with PVT detector 712 of Figure 7, PVT code generator circuit 1230 generates a PVT code as signals W-Z. Combinational logic 1210 interprets the PVT code of signals W-Z and generates a slew rate control (SRC) code as signals NO, Nl, P0, and PI. Combinational logic 1210 may be referred to as a PVT code interpreter or an SRC code generator.
  • SRC slew rate control
  • PVT code generator 1230 includes predrivers or tracking circuits 1232, 1234, 1236, and 1238. Any number of tracking circuit may be used in PVT code generator 1230. Each tracking circuit includes a tunable current source, a biasing transistor, and a comparator. For example, tracking circuit 1232 includes tunable current source 1222 sourcing current lN0/ n-channel biasing transistor 1202, and comparator 1212. Tracking circuit 1234 includes tunable current source 1224 sourcing current n-channel biasing transistor 1204, and comparator 1214. Tracking circuit 1236 includes tunable current source 1226 sinking current Ipo, n-channel biasing transistor 1206, and comparator 1216. Tracking circuit 1238 includes tunable current source 1228 sinking current Ipi, n-channel biasing transistor 1208, and comparator 1218.
  • tracking circuit 1232 includes tunable current source 1222 sourcing current lN0/ n-channel biasing transistor 1202, and comparator 1212.
  • Tracking circuit 1234 includes tunable current
  • the tunable current sources are adjustable based on known circuit parameters (e.g., transistor sizes and process parameters) as well as likely operating conditions such that the tunable current sources may provide a constant current across changing PVT operating conditions as generally known in the art.
  • the tunable current sources may include a band gap reference circuit.
  • the tunable current sources may be tuned to correspond to the slowest transistors. Alternatively the tunable current sources may be tuned to correspond to the fastest transistors. Typical constant currents may range from 50 ⁇ A to 250 ⁇ A. Additionally, the biasing voltages may be biased accordingly to emphasize one or more of the PVT conditions. For example, process and voltage variations may be emphasized or have more impact on the PVT code than temperature conditions.
  • the function of each of n-channel tracking circuits 1232 and 1234 may be illustrated with reference to tracking circuit 1232. When PVT conditions are fast relative to nominal PVT conditions, then the impedance of transistor 1202 decreases causing the voltage at node 1240 to decrease.
  • comparator 1212 causes the W signal to have a low logic value.
  • the low logic value of the W signal may be coupled to the NO signal by combinational logic 1210 to disable n-channel transistor 610 in Figure 6A from affecting the slew rate of the DRIVE signal.
  • Vref is VDD/2.
  • comparator 1212 causes the W signal to have a high logic value.
  • the high logic value of the W signal may be coupled to the NO signal by combinational logic 1210 to enable n-channel transistor 610 in Figure 6A to increase the slew rate of the DRIVE signal.
  • each of p-channel tracking circuits 1236 and 1238 may be illustrated with reference to tracking circuit 1236.
  • the impedance of transistor 1206 decreases causing the voltage at node 1244 to increase.
  • comparator 1216 causes the Y signal to have a high logic value.
  • the high logic value of the Y signal may be coupled to the P0 signal by combinational logic 1210 to disable p-channel transistor 605 in Figure 6 A from affecting the slew rate of the DRIVE signal.
  • the impedance of transistor 1206 increases causing the voltage at node 1244 to decrease.
  • comparator 1216 causes the Y signal to have a low logic value.
  • the low logic value of the Y signal may be coupled to the P0 signal by combinational logic 1210 to enable p-channel transistor 605 in Figure 6 A to increase the slew rate of the DRIVE signal.
  • the constant currents INO INI IPO and Ipi may be equal to each other, or may be different. For example, INI may source twice as much current as INO/ an d Ipi rnay source twice as much current as Ipo.
  • the criteria for setting constant currents I O I I IPO and Ip is to tune the outputs of the tracking circuits to switch at the appropriate PVT operating conditions.
  • PVT code generator 1320 may use one, four, or any number of tracking circuits depending on the number of SRC codes signals required.
  • PVT codes on W-Z may be encoded by combinational logic 1210 to reduce the number of SRC control signals.
  • 2 ⁇ tracking circuits may be used to drive combinational logic 1210, where N represents the number of SRC codes.
  • a possible implementation of slew rate circuit 260 may include an array of N three-state predrivers 225. The array of N three-state pre-drivers may vary in strength /size in a geometric pattern to decode and utilize the encoded SRC codes.
  • a PVT operating condition corresponding to a nominal or typical slew rate for the DRIVE signal may correspond to inverter 215 being enabled and three-state inverters 225A and 225B being disabled.
  • the PVT operating condition corresponding to a nominal or typical slew rate for the DRIVE signal may correspond to inverter 215 being enabled and one of three-state inverters 225A or 225B being enabled (or either of their respective p-channel or n-channel transistors being enabled).
  • Combinational logic 1210 performs a similar function as combinational logic 710 of Figure 7, that is, combinational logic 1210 may re-map PVT codes to desired SRC codes at different PVT operating conditions. Additionally, combinational logic 1210 may error-correct or eliminate undesirable PVT codes, and combinational logic 1210 may generate SRC codes that affect the the duty cycle of the DRIVE signal.
  • combinational logic 1210 is illustrated in Figure 13.
  • Combinational logic 1210 of Figure 13 includes AND gate 1302, inverters 1304 and 1306, and OR gate 1308.
  • AND gate 1302 outputs the Nl signal in response to the X signal and the inverted Y signal received from inverter 1304.
  • OR gate 1308 outputs the PI signal in response to the Z signal and the inverted W signal output from inverter 1306.
  • Combinational logic 1210 may be used in conjunction with three-state inverters 225C and 225D illustrated in Figure 6B.
  • Three-state inverters 225C and 225D are configured in a similar fashion as three- state inverters 225A and 225B of Figure 6A with one exception: three- state inverter 225C has the drain of transistor 615 coupled to the drain of transistor 620, and three-state inverter 225D has the drain of transistor 635 coupled to the drain of transistor 640. Due to this configuration, three-state inverter 225C has the characteristic operation of increasing the slew rate of both the rising and falling slew rates of the DRIVE signal when NO is asserted to a high voltage or when P0 is asserted to a low voltage.
  • transistor 610 when NO is asserted to a high voltage, transistor 610 is conducting and will increase the rising and falling edge slew rates of the DRIVE signal at node 601. Transistor 610 may increase the falling edge slew rate to a greater degree than the rising edge slew rate. Transistor 605 operates in a similar fashion. Similarly, three-state inverter 225D has the characteristic operation of increasing the slew rate of both the rising and falling edges of the DRIVE signal when signal Nl s asserted to a high voltage or when PI is asserted to a low voltage.
  • Combinational logic 1210 may error-correct or re-map undesirable PVT codes generated by PVT code generator 1230.
  • a summary of the re-mapped PVT codes is illustrated in Tables 3 and 4.
  • the re-mapping may be useful to limit maximum slew rates. For example, when PVT operating conditions are such that the DRIVE signal has a slow rising slew rate and a fast falling slew rate, then the PVT code generated on W-Z may be 1111.
  • the SRC code signals NO, Nl, P0, and PI are also 1111, and three-state inverters 225C and 225D increase the slow rising slew rate, but also have the undesired effect of increasing the fast falling slew rate (to a lesser degree).
  • Table 3 shows a summary of simulated PVT operating conditions and at various PVT conditions similar to Tables 1 and 2.
  • the process (P) column has the NMOS process parameters listed first as fast (F), slow (S), or typical (T), and the PMOS process parameters listed second.
  • the "Actual SRC Codes" are the SRC codes enerated by combinational logic 1210 of Fi ure 13.
  • combinational logic 1210 error-corrects or eliminates several possible SRC codes.
  • the eliminated codes may be found not to occur in a particular process, or may determined not to be useful or may even have undesirable effects upon the slew rate of the DRIVE signal (e.g., increasing the slew rate of one edge of the DRIVE signal too much etc.).
  • Table 3 illustrates that the fast n- channel/slow p-channel process operating conditions have been error- corrected to fast n-channel /typical p-channel SRC codes.
  • Table 3 illustrates that the slow n-channel /fast p-channel process operating conditions have been error-corrected to typical n- channel/fast p-channel SRC codes.
  • Any SRC code may be mapped out for a given slew rate indicator given the intended PVT conditions and desired slew rate adjustments to the DRIVE signal.
  • FIG. 14A illustrates tracking circuit 1400 which is an alternative embodiment for tracking circuit 1236.
  • the p-channel transistor 1206 is no longer configured as a diode; rather, its gate is coupled to a biasing voltage Vbl.
  • comparator 1216 has its inverted input coupled to another biasing voltage Vb2 and not Vref.
  • the biasing voltages may be selected to produce a desired state to emphasize a particular PVT operating conditions.
  • the biasing voltages may be determined through characterization or simulation of actual or anticipated PVT operating conditions.
  • the biasing voltage may be selected to bias biasing transistor 1206 in a linear or saturation region of operation.
  • FIG 14B similarly illustrates tracking circuit 1402 which is an alternative embodiment or tracking circuit 1232.
  • the n-channel transistor 1202 is no longer configured as a diode; rather, its gate is coupled to biasing voltage Vbl.
  • comparator 1212 has its inverted input coupled to another biasing voltage Vb2 and not Vref.
  • the biasing voltages may be selected to produce a desired state to emphasize a particular PVT operating conditions.
  • the biasing voltages may be determined through characterization or simulation of actual or anticipated PVT operating conditions.
  • the biasing voltage may be selected to bias biasing transistor 1202 in a linear or saturation region of operation.
  • the combinational logic for combinational logic 1210 may be readily determined from Table 4.
  • the error- corrected SRC codes are readily determined from Table 4.
  • the relationship of PVT operating conditions to the function of tracking circuits 1232-1238 and 1400-1402 may be described as follows. Recall that the slew rate of the OUT signal is a strong function of the slew rate of the DRIVE signal, and the slew rate of the DRIVE signal is proportional to the switching delay of three-state inverter 225 driving the fixed load of output buffer 220. This can be approximated as an RC charging problem as shown in Figure 21.
  • Figure 21 illustrates an equivalent circuit of three-state inverter 225 having a resistance Reffp representing resistance due to PMOS transistors, and a resistance Reffn representing resistance due to NMOS transistors. Additionally, output buffer 220 is represented as a capacitive load C.
  • the slew rate of the DRIVE signal for the equivalent circuit may be expressed by as 1/Tp, where Tp is the switching delay of the equivalent circuit of three-state inverter 225. Tp may be expressed as Ieff/(C*Vswing), where Ieff is the current flowing through Reffp or Reffn, and Vswing is the voltage swing of the DRIVE signal.
  • Ibias is the bias current of the devices (e.g., INO or Ipo) which is set by constant current sources 1222 and 1226, respectively such that the slew rate of the DRIVE signal is proportional to Vds of the biasing devices (i.e., elements 1202 and 1206).
  • biasing voltage Vbl and comparator voltage Vb2 By setting biasing voltage Vbl and comparator voltage Vb2 appropriately, the conductance of biasing transistor 1202 may be measured at a region that most correlates with slew rate.
  • the voltage level on Vbl can be set to VDD, and Vb2 can be set to VDD/ 3 to measure the conductance of biasing element 1202 as it switches between the linear and saturation mode of operation.
  • Id ⁇ Cox(W/L)[(Vgs - Vt)2] for Vds > Vgs - Vt
  • Id is the drain current
  • Vgs is the voltage difference between the gate and source of a transistor
  • Vds is the voltage difference between the drain and source of a transistor
  • ⁇ is the mobility of carriers which is a function of PVT conditions
  • Cox is oxide capacitance which is a function of process parameters
  • W/L is the width/length of a transistor which is a function of process parameters
  • Vt is the threshold voltage of a transistor which is a function of PVT conditions.
  • each term in equations 1-3 has a different dependence on process, operating voltage, and temperature.
  • biasing voltages Vbl and Vb2 as in tracking circuits 1400 and 1402
  • each component of equations 1-3 may be weighted for a "best fit" to slew rate, or to emphasize one or more of the PVT effects.
  • diode connected biasing transistor 1202 results in:
  • Vds square root((2/ ⁇ Cox)(W/L)Ibias) - Vt
  • sampling circuitry may sample the PVT codes or the SRC codes over time and produce a time-averaged PVT code or SRC code.
  • the sampling circuit may select one of the sampled PVT or SRC codes.
  • the sampling circuitry may be coupled between PVT code generator 1230 and combinational logic 1210 of Figure 12, or may coupled after combinational logic 1230.
  • the sampling may be integrated with PVT code generator 1230 or with combinational logic 1210. Averaging may reduce the chances or error due to power supply noise, glitches, and other non-optimal operating conditions.
  • FIG. 15 illustrates one embodiment of slew rate indicator 1500 that generates one of the SRC code signals NO.
  • Slew rate indicator 1500 includes tracking circuit 1232, combinational logic 1210, and sampling circuitry 1510. Sampling circuitry 1510 samples the SRC code generated by combinational logic 1210 and generates the final SRC code as signal NO.
  • FIG 16 illustrates slew rate indicator 1600 that is another embodiment of slew rate indicator 230 for controlling three-state inverters 225 A and 225B shown in Figure 6 A.
  • Slew rate indicator 1600 may also be considered a PVT detector that generates varying SRC code signals in response to changes in the process, voltage, or temperature of a device or system containing bus driver circuit 200 and slew rate indicator 1600.
  • Slew rate indicator 1600 may generate an SRC code for two three-state inverters or for any number of three-state inverters coupled in parallel with inverter 215 of Figure 2.
  • Slew rate indicator circuit 1600 includes control circuit 1602 coupled to PVT code generator 1604 and PVT code interpreter 1606.
  • Control circuit 1602 may receive control signals including a clock signal, an enable signal, or a RUN signal.
  • Control circuit may provide the appropriate signals to PVT code generator 1604 and PVT code interpreter 1606 on lines 1608 and 1610, respectively, that cause slew rate indicator circuit 1600 to function properly.
  • Control circuit 1602 may be a state machine, microcontroller, or any other logic that performs the operations further outlined below.
  • PVT code generator 1604 Upon receiving the appropriate signals from control circuit 1602 on line(s) 1608, PVT code generator 1604 generates a PVT or thermometer code on line 1612.
  • the PVT code may be one signal or multiple signals.
  • Line 1612 may be one signal line or multiple signal lines.
  • the PVT code correlates with the relative strength of the semiconductor elements (e.g., transistors, etc.) included within bus driver circuit 200.
  • the relative strength of the semiconductor elements correlate with the relative slewing strength of the DRIVE signal of Figure 2.
  • the relative strength of the semiconductor elements are affected by variations in the fabrication process, supply voltage, and substrate temperature (i.e., the PVT operating conditions).
  • the PVT code on line 1612 is supplied to PVT code interpreter 1606 which uses the PVT code to generate a corresponding slew rate control (SRC) code to drive the appropriate pre-driver signals NO, Nl, P0, and PI of three-state inverters 225 A and 225B. If there are more or less pre-driver circuits than three-state inverters 225A and 225B, then PVT code interpreter 1606 may generate an appropriate slew rate control code in response to the PVT code from PVT code generator 1604. The PVT code generation, PVT code interpretation, and SRC code generation are all controlled by control circuit 1602 which coordinates the SRC code generation sequence.
  • SRC slew rate control
  • the SRC code generated by PVT code interpreter 1606 may also used to indicate PVT operating conditions, and thus may be used for circuits other than those adjusting a slew rate of a signal.
  • Figure 17 illustrates slew rate indicator 1700 that is one more detailed embodiment of slew rate indicator 1600. Because falling edge and rising edge slew rates of the DRIVE signal may need to be controlled independently, slew rate indicator 1700 includes two PVT code generators 1704 and 1708, and two PVT code interpreters 1706 and 1710.
  • NMOS PVT code generator 1704 and NMOS PVT code interpreter 1706 determine the relative strength of NMOS transistors and elements, and are used to produce the SRC code (e.g., NO and Nl) on p lines of output 1718 for NMOS transistors 610 and 630 of Figure 6A.
  • PMOS PVT code generator 1708 and PMOS PVT code interpreter 1710 determine the relative strength of PMOS transistors and elements, and are used to produce the SRC code (e.g., P0 and PI) on q lines of output 1726 for PMOS transistors 605 and 625 of Figure 6 A.
  • the number of lines p may be equal to the number of lines q, or they may be different.
  • NMOS PVT code generator 1704 includes a series of delay elements 1730-1733. The time required for a signal to travel through delay elements 1730-1733 may be determined only by NMOS devices.
  • PMOS code generator 1708 includes a series of delay elements 1734-1737. The time required for a signal to travel through delay elements 1734-1737 may be determined only by PMOS devices. Although four delay elements are illustrated in each of NMOS PVT code generator 1704 and PMOS PVT code generator 1708, any number of delay elements may be used.
  • Delay elements 1730-1737 may be any type of delay element.
  • delay elements 1730-1737 may be inverting delay elements.
  • delay elements 1730-1737 may be non-inverting delay elements.
  • delay elements 1730-1737 may be RC delay circuits.
  • control circuit 1702 is appropriately prompted by the RUN signal to start the sequence of steps to generate the SRC codes on lines 1718 and 1726.
  • control circuit 1702 send signals on lines 1712, 1720, 1716, and 1724 to reset and/or pre- charge code generators 1704 and 1708 and code interpreters 1706 and 1710, respectively.
  • Pre-charging code generators 1704 and 1708 may cause a predetermined logic state to be generated by some of delay elements 1730-1737.
  • the PVT codes on lines 1714 and 1722 may then be coupled to NMOS PVT code interpreter 1706 and PMOS PVT code interpreter 1710, respectively.
  • the PVT code interpreters may interpret the PVT codes and generate SRC codes on lines 1718 and 1726.
  • Control circuit 1702 may send signals on lines 1716 and 1724 to code interpreters 1706 and 1710, respectively, that cause the PVT code interpreters to interpret the PVT codes.
  • control circuit 1702 may cause code interpreters 1706 and 1710 to interpret user-specified PVT codes supplied by control circuit 1702 or other circuitry.
  • the user-specified PVT codes may be used, for example, to calibrate or characterize code interpreters 1706 and 1710 relative to given PVT conditions.
  • Figure 18A illustrates one embodiment of NMOS PVT code generator 1704 and NMOS PVT code interpreter 1706 for generating NO and Nl for controlling NMOS transistors 610 and 630, respectively. Similar circuitry may be used in PMOS PVT code interpreter 1708 and PMOS PVT code interpreter 1710 with modifications as generally known by one skilled in the art. The operation of Figure 18A will be described with respect to the steps of Figure 17B and with respect to the illustrative timing diagram of Figure 18B.
  • control circuit 1702 commences the SRC code determination in response to the RUN signal being asserted to a high logic state at time tO.
  • the RUN signal may also be coupled to latches 1836 and 1837 to cause them to hold their outputs.
  • control circuit 1702 sends reset signal PVTRST to NMOS PVT code generator 1704.
  • PVTRST resets latch circuits 1822-1825.
  • PVTRST resets latches 1822-1825 and may also be coupled to delay elements 1810-1821 to pre-charge their outputs. Pre-charging their outputs will cause the outputs of inverters 1815, 1817, 1819, and 1821 to have a high state as will be described in greater detail below.
  • control circuit 1702 sends a FIRE pulse to delay elements 1810-1821.
  • Delay elements 1810-1821 are inverters in Figure 18A, and may be considered to be in two parts. The first part is an untapped delay series 1808 including delay elements 1810-1813, and the second part is a tapped delay series 1806 including delay elements 1814-1821. Tapped delay series 1806 is tapped at the output of every other delay element by the inputs of latches 1822-1825. Other types of delay elements may be used such that latches 1822-1825 may tap every delay element output, or any combination of the delay element outputs.
  • Untapped delay series 1808 may contain an even number of delay elements, an odd number of delay elements, or no delay elements.
  • the FIRE pulse is sent to delay elements 1810-1821 and to the enable inputs (EN) of each of latches 1822-1825.
  • latches 1822-1825 are enabled to output the data provided by delay elements 1821, 1819, 1817, and 1815, respectively.
  • the FIRE pulse may be a low pulse or a high pulse.
  • FIRE is a low pulse.
  • control circuit 1702 causes the FIRE pulse to transition to a high logic value and thus causes latches 1822-1825 to hold their outputs.
  • the latched values are output on lines 1826-1829 and constitute the PVT or thermometer code.
  • the number of latches that have changed state corresponds to the number of delay elements the FIRE signal has traveled through during the predetermined amount of time.
  • the number of delay elements that the FIRE signal may propagate through during the predetermined amount of time may change with variations in process, supply voltage, and temperature.
  • the PVT code may change with variations in process, supply voltage, and temperature.
  • NMOS PVT code interpreter 1706 may optionally include combinational logic 1852, and one multiplexer and one latch circuit for each SRC bit output by code interpreter 1706.
  • NMOS PVT code interpreter 1706 may also simply comprise a direct connection between line 1826 and NO, and line 1828 and Nl.
  • Combinational logic 1852 may provide the same function as combinational logic 710 and 1210, that is, to prevent undesirable SRC codes which would otherwise be indicated by certain PVT codes.
  • Code interpreter 1706 generates two SRC code bits NO and Nl and includes two latches 1836 and 1837 coupled to multiplexers 1832 and 1834, respectively.
  • Multiplexer 1832 receives the signal on line 1854 and a signal from a user-defined PVT code signal on line 1838.
  • the signal on line 1854 may be the signal on line 1826.
  • multiplexer 1834 receives a signal on line 1856 and a user-defined PVT code signal on line 1839.
  • the signal on line 1856 may be the signal on line 1828.
  • the SELECT signal causes the PVT code on lines 1854 and 1856 to be output by multiplexers 1832 and 1834, respectively.
  • the RUN signal is deasserted to a low logic state and latches 1836 and 1837 are enabled to pass the signals from multiplexers 1832 and 1834 as SRC codes NO and Nl.
  • the time between tO and t4 permits three-state inverters 225A and/or 225B to operate up to time t4 when that latches 1836-1837 latch new SRC codes. This has the effect of pipelining the generation of new SRC codes.
  • control circuit 1702 may cause SELECT to enable multiplexers 1832 and 1834 to output user-defined PVT codes from lines 1838 and 1839, respectively.
  • latches 1822-1825 and 1836- 1837 may be replaced with registers and the function of NMOS PVT code generator 1702 and NMOS PVT code interpreter 1706 adjusted as generally known in the art.
  • Figure 18A illustrates that multiplexers 1832 and 1834 are coupled to PVT code lines 1854 and 1856, respectively, from combinational logic 1852.
  • multiplexers 1832 and 1834 may be coupled to any of the PVT code lines 1826-1829.
  • the determination of which PVT code lines are coupled to multiplexers 1832 and 1834 may be determined by characterization and simulation of the process, voltage, and temperature cases of interest and by monitoring the PVT codes produced on lines 1826-1829. Based on this information, multiplexers 1832 and 1834 may be coupled to the appropriate PVT code lines and combinational logic 1852 may not be required or may be kept to a minimum.
  • the size of untapped delay elements 1808 may be changed, or the number of untapped delay element may be changed. If there is not enough resolution between PVT codes, the delay through each delay element or some of delay elements 1810-1821 may be decreased.
  • Figures 19A-19C are timing diagrams for further illustrating the operation of Figure 18.
  • waveform "A” corresponds to the output of delay element 1815 on line 1843
  • waveform "B” corresponds to the output of delay element 1817 on line 1842
  • waveform "C” corresponds to the output of delay element 1819 on line 1841
  • waveform "D” corresponds to the output of delay element 1821 on line 1840.
  • FIG. 19A-19C illustrates waveforms generated after NMOS PVT code generator 1704 and NMOS PVT code interpreter 1706 have been reset, and delay elements 1815, 1817, 1819 and 1821 have been pre-charged to generate high logic states.
  • Figure 19A illustrates a condition in which the DRIVE signal may have a slew rate that needs to be increased given slow PVT operating conditions (e.g., slow process parameters, low operating supply voltage, and /or hot operating temperatures).
  • slow PVT operating conditions e.g., slow process parameters, low operating supply voltage, and /or hot operating temperatures.
  • Figure 19B illustrates a condition in which the DRIVE signal may have a slew rate that needs to be increased given the current PVT operating conditions, but may not need to be increased as much as in Figure 19A.
  • the FIRE pulse is supplied to the delay elements 1810-1821, and starts to propagate through delay elements 1810-1821. If the predetermined amount of time ends at time t2, then the output of delay elements 1815 and 1817 will have changed state from a high logic state to a low logic state.
  • the low logic state output by delay element 1817 may be latched by latch 1824, output on line 1828, passed through multiplexer 1834 and latched as Nl by latch 1837.
  • NMOS transistor 630 may then be enabled to increase the slew rate of the DRIVE signal.
  • Figure 19C illustrates a condition in which the DRIVE signal may have a slew rate that does not need to be increased given the current PVT operating conditions (e.g., fast process parameters, high operating supply voltages, and /or cold operating temperatures).
  • the FIRE pulse is supplied to the delay elements 1810- 1821, and starts to propagate through delay elements 1810-1821. If the predetermined amount of time ends at time t2, then the output of delay elements 1815, 1817, 1819, and 1821 will have changed state from a high logic state to a low logic state.
  • the low logic states output by delay elements 1817 and 1821 may be latched by latches 1824 and 1822, output on lines 1828 and 1826, passed through multiplexers 1834 and 1832, and latched as Nl and NO by latches 1837 and 1836, respectively.
  • NMOS transistors 630 and 604 may then be disabled so as not to affect the slew rate of the DRIVE signal.
  • N (T-D)/tdelay
  • N the number of delay elements in tapped portion 1806 through which the FIRE signal propagates during a predetermined time
  • T is the predetermined time of the FIRE signal
  • D is the time required for the FIRE signal to propagate through untapped portion 1808
  • tdelay is the time through a delay element in tapped portion 1806. If tdelay is a small number so as to gain fine resolution of the PVT code, then many delay elements and more circuitry (i.e., more silicon area of an integrated device) may be required to implement D.
  • D may be removed from time T, thus making N a smaller number.
  • the propagation delay of the FIRE signal through tapped portion 1806 may be process tuned by adjusting D so that under nominal operating conditions N may be manageable number (e.g., approximately five). If it is determined that more or less resolution is needed in the PVT code such that the delay of a delay element in tapped portion 1806 must be adjusted, then D may be predetermined to place the nominal case in the center of the number of elements in tapped portion 1806.
  • Figure 20 illustrates one embodiment of the inverting delay elements 1820 and 1821 of Figure 19 configured as domino logic.
  • Delay element 1820 includes NMOS pull-up transistor 2004 coupled in series with NMOS pull-down transistor 2002.
  • NMOS transistor 2004 has a source couple to the drain of NMOS transistor 2002 and line 2010, and a gate and drain coupled to a power supply rail.
  • NMOS transistor 2002 has a source coupled to ground, a gate coupled to an input signal from delay element 1819 on line 1841, and a drain coupled to line 2010.
  • Delay element 1821 includes PMOS transistor 2008 coupled in series with NMOS transistor 2006.
  • NMOS transistor 2006 has a source coupled to ground, a gate coupled to line 2010, and a drain coupled to the drain of PMOS transistor 2008 and output 1840.
  • PMOS transistor 2008 has a source coupled to a power supply rail, a drain coupled to the drain of NMOS transistor 2006 and output 1840, and a gate coupled to a PRE-CHARGE signal.
  • the PRE-CHARGE signal may be the logical complement of the FIRE signal.
  • NMOS transistor 2004 may be sized much smaller than NMOS transistor 2002 such that line 2010 settles to a voltage level well below the threshold voltage of NMOS transistor 2006.
  • PMOS transistor 2008 may then be turned off by pulling the PRE-CHARGE signal high.
  • delay elements 1820 and 1821 may quickly switch states such that a low state may be present on line 1840.
  • the same delay elements may be used for the delay elements in PMOS PVT code generator 1706, replacing NMOS transistors 2002, 2004, and 2006 with PMOS transistors, and replacing PMOS transistor 2008 with an NMOS transistor.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

La présente invention concerne un montage de circuit d'attaque de bus capable de reprendre la vitesse de balayage du bus lorsque l'état de fonctionnement font apparaître des variations inacceptables de la vitesse de balayage. Selon une réalisation, ce circuit d'attaque de bus comporte un circuit témoin de vitesse de balayage, lui-même pourvu d'un circuit de détection 'tension-température-process' ou PVT. Ce circuit de détection PVT est pourvu d'une pluralité d'éléments retard montés en chaîne, laquelle pluralité d'éléments retard est configurée de façon à recevoir un signal de déclenchement qui se propage à travers les éléments retard pendant une période définie. Ces éléments retard génèrent un code PVT (tension-température-process) à l'échéance de la période considérée. Le code PVT dénote l'état de fonctionnement du circuit de détection PVT. Le code PVT, qui varie en fonction de l'état de fonctionnement PVT du circuit de détection PVT et du circuit d'attaque de bus, vient influencer la vitesse de balayage du circuit d'attaque du bus.
PCT/US1998/003364 1997-02-18 1998-02-18 Circuit d'attaque de bus equipe d'un circuit temoin de vitesse de balayage pourvu d'une serie d'elements retard WO1998036497A1 (fr)

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US80054197A 1997-02-18 1997-02-18
US08/800,541 1997-02-18

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202702B2 (en) 2003-12-10 2007-04-10 Hewlett-Packard Development Company, L.P. Output buffer slew rate control using clock signal
WO2018187008A1 (fr) * 2017-04-04 2018-10-11 Qualcomm Incorporated Cohérence de balayage et de gigue de frontal radiofréquence pour des tensions inférieures à 1,8 volt
EP3503402A1 (fr) * 2017-12-22 2019-06-26 Commissariat à l'Energie Atomique et aux Energies Alternatives Circuit de détection pvt

Citations (5)

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Publication number Priority date Publication date Assignee Title
EP0357532A2 (fr) * 1988-09-02 1990-03-07 International Business Machines Corporation Mesure de performances de circuits intégrés du type à puce
EP0523833A1 (fr) * 1991-07-16 1993-01-20 Samsung Semiconductor, Inc. Circuit tampon de sortie programmable
EP0547349A2 (fr) * 1991-12-16 1993-06-23 Hewlett-Packard Company Circuit intégré à sortie programmable
EP0611053A2 (fr) * 1993-02-08 1994-08-17 Advanced Micro Devices, Inc. Circuits tampon
US5517136A (en) * 1995-03-03 1996-05-14 Intel Corporation Opportunistic time-borrowing domino logic

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Publication number Priority date Publication date Assignee Title
EP0357532A2 (fr) * 1988-09-02 1990-03-07 International Business Machines Corporation Mesure de performances de circuits intégrés du type à puce
EP0523833A1 (fr) * 1991-07-16 1993-01-20 Samsung Semiconductor, Inc. Circuit tampon de sortie programmable
EP0547349A2 (fr) * 1991-12-16 1993-06-23 Hewlett-Packard Company Circuit intégré à sortie programmable
EP0611053A2 (fr) * 1993-02-08 1994-08-17 Advanced Micro Devices, Inc. Circuits tampon
US5517136A (en) * 1995-03-03 1996-05-14 Intel Corporation Opportunistic time-borrowing domino logic

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Title
COX D T ET AL: "VLSI PERFORMANCE COMPENSATION FOR OFF-CHIP DRIVERS AND CLOCK GENERATION", PROCEEDINGS OF THE CUSTOM INTEGRATED CIRCUITS CONFERENCE, SAN DIEGO, 15 - 18 MAY, 1989, no. CONF. 11, 15 May 1989 (1989-05-15), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 1431 - 1434, XP000075642 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7202702B2 (en) 2003-12-10 2007-04-10 Hewlett-Packard Development Company, L.P. Output buffer slew rate control using clock signal
WO2018187008A1 (fr) * 2017-04-04 2018-10-11 Qualcomm Incorporated Cohérence de balayage et de gigue de frontal radiofréquence pour des tensions inférieures à 1,8 volt
EP3503402A1 (fr) * 2017-12-22 2019-06-26 Commissariat à l'Energie Atomique et aux Energies Alternatives Circuit de détection pvt
FR3076127A1 (fr) * 2017-12-22 2019-06-28 Commissariat A L'energie Atomique Et Aux Energies Alternatives Pvt detection circuit
US10685700B2 (en) 2017-12-22 2020-06-16 Commissariat à l'énergie atomique et aux énergies alternatives PVT detection circuit

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