WO1998028746A1

WO1998028746A1 - Redundancy for wide hierarchical i/o organizations

Info

Publication number: WO1998028746A1
Application number: PCT/US1997/024095
Authority: WO
Inventors: Donald C. Stark; Ely K. Tsern
Original assignee: Rambus, Inc.
Priority date: 1996-12-23
Filing date: 1997-12-22
Publication date: 1998-07-02
Also published as: TW410306B

Abstract

In a memory core (Figure 3) a method and apparatus for replacing global I/O lines (56, 58, Figure 3) associated with a defective column in a memory sub-array with global I/O lines not associated with such a defect. To improve yield of a memory device such as a DRAM, the device typically employs spare elements which can replace defective elements. In this invention, to reduce the die area consumed for spare elements, the global I/O line (56, 58, Figure 3) is chosen as the replaceable element. The bit position of a defective global I/O line within a bus of global I/O lines is determined. According to whether a particular column has a defect and for each normal global I/O line with a defective column, the global I/O line is replaced with an adjacent non-defective global I/O line (Figure 5). At the bit position a spare on-defective global I/O line is introduced to complete the bus. The number of defective global I/O lines that may be removed from the bus is the same as the number of spare non-defective I/O lines (40, Figure 3) available to fill in the missing bit positions at the end of the bus.

Description

REDUNDANCY FOR WIDE HIERARCHICAL I/O ORGANIZATIONS

BACKGROUND OF THE INVENTION The present invention relates to memory devices, and in particular to a redundant I/O line circuit. Semiconductor DRAMs are typically formed of lines of rows and columns. Capacitors adjacent each crossing of the row and columns store charge, representing the data to be stored, and are switched to the columns in order to receive or discharge charge upon receipt of an appropriate voltage on the rows. The rows and columns are selected so as to read and write to particular capacitors by means of row and column decoders .

There are sometimes defects associated with the columns or associated elements, such as the memory cells themselves or the sense amplifiers. For this reason DRAMs usually contain redundant (spare) columns, which involve the provision of extra memory elements and column circuitry. The extra memory and required redundant decoders to access that memory in place of defective columns use valuable semiconductor chip area and decreases the efficiency of the memory .

Larger memories are typically subdivided into sub- arrays of rows and columns. Earlier generations physically placed one sub-array on each side of a column decoder array, and the column decoders accessed the columns in each of the adjacent sub-arrays. The memory was divided into blocks, each block being formed of two sub-arrays located on either side of the column decoder. Redundant columns and column decoders were placed at a location usually at one end of each block. The address of a defective column must be programmed into a redundant decoder in order to enable a redundant column whenever the address of a defective column is received. The defective column decoder is also disabled, either electrically using the output of the redundant decoder, or physically with a local fuse.

In a 1Mbit generation DRAM there may be 2 blocks, each having a dedicated array of Y-decoders with 2 redundant decoders, 2 arrays in each block, 2 outputs per Y-decoder, and 2 databuses per array.

Redundant rows and/or columns of memory cells are provided in order to replace rows and/or columns of the main memory array which are found to be defective, during testing, e.g., during wafer sort. In general, the redundant rows and/or columns have initially unspecified addresses and redundant decoders coupled to them. The redundant decoders are programmable to match the addresses of rows and/or columns which are determined to be defective. The defective rows and/or columns are disabled.

^■In operation, when a memory read or write cycle is executed, access to the defective rows and/or columns is prevented, and the redundant decoders are responsive to only the addresses of the defective rows and/or columns, to thereby effectively replace the defective rows and/or columns with the redundant rows and/or columns, which are sometimes referred to as spare rows and/or columns .

A typical implementation of the programmable redundant decoder is an address decoder in which a polysilicon fusible link, i.e., fuse, is connected to each address bit line of a row address or column address buffer, depending upon whether the redundant decoder is a redundant row or column decoder, respectively. In order to program such a redundant decoder with the address of a column or row of memory cells having a defective memory cell, selected ones of the fuses are cut/blown, e.g., by means of a laser.

Examples of redundant column circuits are set forth in US Patent No. 5,325,334. US Patent No. 5,469,401 discusses redundant column circuitry which can be flexibly assigned to a single array, racher than all arrays. US Patent No. 5,467,655 discloses a redundant column circuit which reduces the number of fuses required. Beyond 16M DRAM technology, the memory arrays are broken up into mats, with the addition of lines of global I/O for connecting to the I/O lines for each mat, which in prior architectures would have gone directly to the integrated circuit I/O. The global I/O lines _are typically parallel to the column select lines, and perpendicular to the I/O from the sense amps for each mat. Thus, a hierarchical I/O structure is provided.

Hierarchical I/O structures offer the potential for inexpensive, high bandwidth DRAM cores for the 64Mb generation and beyond. They allow a larger number of sense amps from the same sub-array to be accessed by running the global I/O lines perpendicular to the column of sense amps rather than parallel to it . One problem for wide hierarchical I/O schemes, however, is column redundancy. If conventional redundancy is used, the number of redundant columns required is proportional to the number of I/O bits. This problem is described in detail, together with an alternative column redundancy scheme. Fig- 1 shows a conventional redundancy scheme for one sub-array with 64 column select lines (CSLs) 10 and two spare column select lines (SCSLs) 12 running vertically. Each connects four sense amps (two each in the top and bottom sense amplifier sections 14 and 16) to the local I/O line pairs 18 and 20. These local pairs connect in turn to the vertical global I/O lines 22. This conventional scheme is fairly expensive; over 3% of all the cells in the example are used for column redundancy.

SUMMARY OF THE INVENTION

The present invention provides an improved use of redundant, spare lines by connecting an adjacent line in place of a defective line , and then shifting the connections of the following lines. Thus, instead of needing to route a spare from the edge of the group of lines, each line need only be connected to its adjacent line to allow replacement. In an alternate embodiment, multiple adjacent lines can be inter- connectable to allow shifting over of two lines in the event that two defective lines need to be replaced.

By the use of shift registers or other circuitry to perform a similar function, I/O lines can be connected in the normal manner when non-defectijye areas are addressed. When a defective area is addressed, the output can be shifted at the time of the read or write attempted to the defective area (typically a defective memory cell or sense amplifier connected to the line is defective) . In a preferred embodiment, the spare global I/O line only connects^' to two sense amplifiers, one on either side of the mat. Two spare column select lines choose between these two. Instead of requiring spares for each set of columns that connect to the same global I/O lines, the present invention only requires one set of spares for the extra global I/O's. In one embodiment of the present invention, only l/16th as many spare columns are required.

For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings .

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram of a prior art redundancy scheme for column select lines.

Fig. 2 is a diagram of an overall memory circuit incorporating the present invention.

Fig. 3 is a diagram illustrating the modification to the prior art of Fig. 1 according to the present invention. Figs. 4 and 5 are diagrams illustrating a single shift and a double shift, respectively.

Fig. 6 is a more detailed diagram showing the shift register output circuitry of the present invention.

Fig. 7 is a more detailed diagram of the shift register circuitry for one bit of the shift registers of Fig. 6.

Fig. 8 is a diagram of an alternate embodiment of the shift register circuitry of Fig. 7 providing for the shift of the spare bits (or a two-bit shift) .

Fig. 9 is a circuit diagram of a spare I/O selector circuit .

DESCRIPTION OF THE INVENTION Fig. 2 shows a possible _^hierarchical array organization that would be suitable for a high bandwidth part. In the diagram, 128 global I/O lines 24 run vertically to column I/O amplifiers 26 located at the bottom. Data is multiplexed to these amplifiers using 16 eight bit shift registers 28 according to the present invention, one for each data pin. No column redundancy is shown in this figure.

Various permutations of this basic organization are possible to provide differing sub-array sizes, row decoder positions, data pins, bank counts, etc. The column redundancy schemes described can readily accommodate any of these variations .

Fig. 3 illustrates the I/O connections to the memory array using the present invention. Shown in Fig. 3 is a memory sub-array 30 consisting of an array of memory cells 32 bounded by two groups of sense amplifiers 34 and 36. These are connected to global I/O lines 38 as in Fig. 1. However, only 64 column select lines 40 are used, eliminating the two spare column select lines 12 per sub-array of Fig. 1. Preferably, sub-array 30 is repeated eight times in an integrated circuit.

According to the present invention, the spares are provided by circuitry 42 provided at the edge of the eight sets of sub-arrays. Circuitry 42 provides four spare column select lines 44 and 46, along with spare sense amplifiers 48, 50, 52 and 54. Two spare global I/O lines 56 and 58 are provided.

In the shifting redundancy scheme, a small number of spare I/O lines are used, as shown in Fig. 3. Unlike a normal global I/O line which connects to one of 64 sense amps per ' sub-array, a spare global I/O line only connects to two, one on either side of the mat. Two spare column select lines choose between these two. (Alternately, two spare I/O lines, one each for the upper and lower sense amps, could also be used, with the result multiplexed.) Since these sense amps lie at the edge of the array, the spare I/O and spare CSL signals need not necessarily fit in the tight pitch of the sense amp, but instead may be partially routed in the strap area if required. The figure, shows two such spares, although in principle any number may be used.

The area advantage of the shifting scheme over a conventional one is clear. Instead of requiring spares for each set of columns that connect to the same global I/O lines, there need only be one set of spares for the extra global

I/O's. In the example, only l/l6th as many spare columns are required (other implementations will have different savings) . The shifting scheme produces 34 column I/O's, where only 32 are required. For the redundancy to work, the spare I/O lines must be routed to replace the defective ones where required. The connection pattern between the I/O amplifiers and the data shift registers is shown in Fig. 6

Figs. 4 and 5 illustrate the shifting for a single and double shift, respectively. Fig. 4 shows a number of I/O lines 41, 43, 45, 47, 49, 51, and 53. In the example shown, an I/O line 45 has failed, or the circuitry to which it connects has failed. The spare lines are 51 and 53. The I/O lines are shown having a corresponding output buffer 41', 43', 45', 47', and 49'. In the example shown, both lines 41 and 43 connect to their respective output buffers, 41' and 43' .

However, failed line 45 is not connected. Instead, line 47 is shifted over to provide the output to buffer 45'. Similarly, line 49 is shifted over to provide its output to buffer 47' . The output of buffer 49' is provided from one of the spare redundant lines, 51.

Fig. 5 shows more of a circuit to illustrate multiple failures. Additional lines 33, 35, 37 and 39 are shown, along with their corresponding output buffers 33', 35', 37', and 39' . In the example shown in Fig. 5, there is a failure on lines 37 and 43. Accordingly, as can be seen, lines 33 and 35 are not shifted at all. Lines 39 and 41, however, are both shifted one place to buffers 37' and 39' . Since line 43 has failed, the remaining lines, 45, 47, and 49 are shifted over two buffer positions. Finally, both redundant lines 51 and 53 are used, connecting to output buffers 47' and 49', as illustrated.

The shifting and new connections can be done in any of a number of ways, and at different times. When defects are detected, fuses can blown to reroute and shift the lines, thus effectively storing the defect data. Alternately, a memory storing the defect locations can be used, with the shifting of spares into the I/O lines being done dynamically when a defective I/O line is accessed, with a dynamic shifting using the stored error data. In such an implementation, rather than using a fuse, an AND gate could be used, with one input from the memory at appropriate locations in the logic.

Defects can occur in a number of locations. For example, defect could occur in a cell itself, in the column lines, or in the I/O lines. If the defect is in the first two, the shifting depends upon whether the column lines accessed have a defect. If the defect is in the I/O lines, the shifting will always need to occur. Fig. 6 shows the global I/O lines 38 along with spare global I/O lines 56 and 58. These are provided to I/O 20 read/write (R/W) amplifiers 60 and spare I/O amplifiers 62. Four shift registers 64, 66, 68 and 70 are provided, along with a 2 -bit test shift register 72. These are interposed between the I/O amplifiers and the data I/O pads of the integrated circuit connected to lines 74.

In normal operation, the I/O lines 76 connected to shift register 64, for bits 0:7, are connected through the 8bit shift register 64 without shifting. However, when a defective area of the DRAM is addressed, the shift register may be controlled to shift the I/O lines. For example, if bit line 6 were defective, it would be disabled, with bit line 7 shifted into its place, and bit line 8 from the adjoining set would be shifted in on line 78. All the remaining lines would also be shifted, with one of the spares being shifted in at the end on one of lines 80. If another defective line is encountered in the same addressed area (same column) , a second shift may be necessary for all the positions to the right of that second defective line, in which case both spares would be shifted in on lines 80.

All shift register bits except the rightmost one are connected to two signals; the read-write data (RWD) line directly above and the RWD line to_ the right. The circuitry for controlling which line gets connected to the input or output shift register is shown in Fig. 7

Fig. 7 shows a single bit shifter circuit 82 which is a portion of one of circuits 64-72 corresponding to a single bit. Eight of these circuits would be included in shifter 64, for instance. As shown, this particular bit 10 selects between two different I/O lines 84 and 86, which are particular ones of I/O lines 76, 78 or 80 of Fig. 6. Switches 88 and 90, respectively, are controlled by a control line 92 and an inverter 94, which ensures that only one of the two lines are connected to bit shifter circuit 82.

Control line 92 has its control signal controlled by fuses 94 and 96 which couple through AND gates 98 and 100, and OR gate 102. The state of these fuses cause the I/O lines to shift when an address corresponding to the defective address appears on control lines 104 and 106. These control lines are spare selectors which are active when an address corresponds to the defective address. The fuses will be blown appropriately for positions corresponding to the defective I/O line and those to its right.

If one of the spare selectors is active and the fuse for this bit position has been blown, then the shifter is connected to bit position n+1. If neither spare select is high or the fuse for an active spare has not been blown, then the regular RWD line n is used.

Control for the rightmost bit (Fig. 8) is similar, except that it connects to both spare lines. If the corresponding spare selector is activated, then the spare I/O line is used in lieu of the regular one.

A circuit similar to Fig. 8 could be used when two shifts are allowed for putting in two different spare lines. As shown, a single shift circuit 108 is connected to three different I/O lines through switches 110, 112 and 114. Depending upon the control signal, a shift of one or two lines could be accomplished. A standard spare I/O se ector circuit can be used for the control; an example is shown in Fig. 9. This particular circuit will replace the same column address in all banks; bank selectability may be obtained by duplicating this circuit, adding extra fuses for the bank address, and Oring together the results.

To replace the I/O line at bit position m for a given column address, the spare I/O selector is programmed for that address. All fuses F₀<j> or F₁<j> for which j is greater than or equal to m are also blown. This causes I/O lines to the left of m to be connected normally, with those to the right being shifted left by 1. I/O line m itself is not used for this column address.

The above implementation is one example of the basic 15 redundancy concept. There are many possible variations, some of which are described in this section.

In the example shown in the figures, the I/O lines are separated into groups of 32 for redundancy. This may be increased for extra efficiency or decreased for extra flexibility, depending on the expected bit failure patterns. The shift registers used in the example of the figures do not allow two I/O lines to be replaced for the same column address (SP₀ and SP-L must be used for different columns) . An implementation to accomplish this is possible; each bit position must support either shift-by-1 or shift-by-2.

This implementation requires n-1 fuses (31 in the example) to indicate which I/O line is to be replaced. The same information could be encoded in log (n-1) fuses, with additional logic to convert the binary position value into the required thermometer code if fuse area is at a premium.

As will be understood by those of skill in the art, the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. For example, the shifting redundancy scheme of the present invention could be applied to not only global I/O lines, but also column lines in a sub-array, or word lines. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of_ the scope of the invention which is set forth in the following claims.

Claims

WHAT IS CLAIMED IS:

1. A memory device comprising: an array of memory cells; a plurality of lines for coupling to particular memory cells in said array of memory cells, including at least one spare line; an interface circuit having first nodes coupled to said lines; a control circuit, coupled to said interface circuit, for disabling a selected one of said lines normally coupled to a selected one of said first nodes, and causing said interface circuit to couple a first line proximate said selected line to said selected first node and to couple a plurality of said lines proximate said first line to first nodes proximate said selected first node to effectively shift said lines.

2. The memory device of claim 1 wherein said lines are global I/O lines.

3. The memory device of claim 2 wherein said first nodes are data I/O lines coupled to I/O pads of an integrated circuit.

4. The memory device of claim 1 wherein said selected line is coupled to a defective circuit.

5. The memory device of claim 4 wherein said defective circuit is a defective memory cell.

6. The memory device of claim 4 further comprising: a plurality of sense amplifiers coupled between said memory cells and said lines; wherein said defective circuit is a defective sense amplifier.

7. The memory device of claim 1 wherein said selected line is a defective line.

8. The memory device of claim 1 wherein said interface circuit includes at least one shift register.

9. The memory device of claim 1 wherein said control circuit includes a programmable fuse coupled to a control input of said shift register.

10. The memory device of claim 1 wherein said array of memory cells includes a plurality of sub-arrays, with a subgroup of said lines adjacent each sub-array, each subgroup containing at least one spare line.

11. A memory device comprising: a memory array having at least one sub-array comprising rows and columns of memory cells; at least two normal global I/O lines coupled to the sub-array, each normal global I/O line having a bit position in a normal I/O bus and each normal global I/O line being associated with at least one column of memory cells; at least one spare global I/O line coupled to the sub-array, each spare global I/O line having a bit position in a spare I/O bus, the starting bit position of spare I/O bus being adjacent to the end bit position of the normal I/O bus; and routing circuitry coupled to each normal global I/O line and to each spare global I/O line, operative, when a column with a defect is being accessed and for each normal I/O line with a defective column, to: (i) create a missing bit position in the normal I/O bus by removing from the normal I/O bus the normal line having the defective column; (ii) replace the missing bit position by coupling an adjacent non-defective global I/O line into the missing bit position.