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WO1998020545A1 - Procede de fabrication de cavites de grande tolerance dans des boitiers de puces - Google Patents

Procede de fabrication de cavites de grande tolerance dans des boitiers de puces Download PDF

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Publication number
WO1998020545A1
WO1998020545A1 PCT/US1997/018804 US9718804W WO9820545A1 WO 1998020545 A1 WO1998020545 A1 WO 1998020545A1 US 9718804 W US9718804 W US 9718804W WO 9820545 A1 WO9820545 A1 WO 9820545A1
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WO
WIPO (PCT)
Prior art keywords
routing
bit
resins
electronic component
cavity
Prior art date
Application number
PCT/US1997/018804
Other languages
English (en)
Inventor
Boydd Piper
Original Assignee
W.L. Gore & Associates, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by W.L. Gore & Associates, Inc. filed Critical W.L. Gore & Associates, Inc.
Priority to AU49872/97A priority Critical patent/AU4987297A/en
Publication of WO1998020545A1 publication Critical patent/WO1998020545A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4871—Bases, plates or heatsinks
    • H01L21/4878—Mechanical treatment, e.g. deforming
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0228—Cutting, sawing, milling or shearing

Definitions

  • the present invention relates to a method of defining high tolerance cavities in electronic components, and the resulting packages. More specifically, the present invention relates to the use of a router system for forming a cavity or cavities in at least one electronic package by inserting and advancing a router bit through the back of the electronic package and traveling the router bit in a counterclockwise direction. Routing of the cavity is conducted until a final dimension is achieved, which may be a final dimension or a predetermined dimension at which time the router bit is replaced by a finishing bit and routing is continued until the final dimensions are achieved. Routing through the back of a package according to the present invention provides a high tolerance cavity in the package where shorter bond wires are used to connect a chip to the package, thereby reducing wire bond inductance.
  • NC numerical control
  • CNC computer numerical control
  • PCWB printed circuit wiring boards
  • prior art processes may produce lips or burrs on the edges of the routed cavities. As a result of these lips or burrs, wires which are bonded to the respective contacts on the chip and package must be looped over the lips or burrs. The presence of the lips or burrs increases wire bond length and the attendant increase in inductance.
  • Cavities in ceramic chip package are usually formed by punching "green sheet", or sheets of plasticized ceramic, which are generally non-cured ceramic. Once the cavities have been punched in several green sheets, they are superimposed upon one another, e.g., stacked up, and the respective cavity in one sheet is aligned with cavities in the other sheets of the stackup. The layered green sheets are then laminated together and cured. Another technique for forming cavities in ceramic packages is by lasing cavities in fired ceramic packages.
  • metallic feature formation technology is employed. In the metallic feature technology, metallic paste is screened into pre-formed features and onto the surface of the green sheet. Thereafter, the green sheets containing the screened pre-form are subjected to firing or curing. The curing or firing causes the green sheet to shrink which is a problem. Shrinkage that occurs during the firing or curing processes, prevents formation of the feature combined with the definition of metal features by screening densities on the order of approximately 100 microns (.0039").
  • a ceramic base or metal heat spreader 1 includes layers 2, 3 and 4 thereon, each defining a cavity of increasing cross-sectional area, 5, 6 and 7, respectively.
  • Each layer can include a single or a plurality of green sheet layers.
  • a chip 9 is inserted into the cavity 10 and wire bonds 9 are attached at respective ends to conductive pads on the chip (not shown) and conductive pads on the wiring package layers (not shown). As a result of this tiered configuration, increased wiring length and increased inductance occurs.
  • FIG. 1 shows a conventional prior art package where gap 11 , the chip to package spacing distance, is greater than 1.00 mm (39.37 mils) wide.
  • the wire bond lengths for this configuration are usually greater than 2.54 mm (100 mils).
  • wire bond lengths are typically larger than 2.54 mm (100 mils), which results in a larger self-inductance than is desired in high performance packages and contributes to high simultaneous switching noise.
  • a need also exists for a manufacturing technique that can reduce the chip to package spacing, and therefore concurrently reduce wire bond length and inductance.
  • the present invention is directed to a method for forming cavities in electronic components, by mounting the component in an inverted position, engaging a router bit with the backside of the component, and moving a router with the bit along a circumscribed area on the component in a counterclockwise direction.
  • An aspect of the present invention is a method for manufacturing chip packages having reduced chip to package gaps, reduced wire bond lengths and reduced inductance.
  • Another aspect of the present invention is to provide a manufacturing protocol that will maximize cavity uniformity.
  • a purpose of the present invention is to form a chip cavity while eliminating or reducing the formation of lips or burrs on the wall edges of the cavity. It is another purpose of the present invention to minimize the chip to package spacing to reduce the inductance of undesirable wire bond lengths.
  • FIG. 1 is a side view of a conventional multi-tiered wire bond package of the prior art.
  • FIG. 2 is a schematic view of the control and routing system used in the present invention.
  • FIG. 3 is a plan view of the routing device with an electronic package mounted in an inverted position.
  • FIG. 4 is a cross-sectional view of the router bit used in the present invention.
  • FIG. 5 depicts the router bit tip used in the present invention.
  • FIG. 6 is a top view of a panel containing a plurality of electronic packages with the aligning and pinning holes for use in the present invention.
  • FIG. 7 depicts a cross-sectional view of the panel depicted in FIG. 6.
  • FIG. 8 is a bottom view of a panel containing a plurality of electronic packages with the aligning and pinning holes for use in the present invention.
  • FIG. 9 depicts a cross-sectional view of the panel depicted in FIG. 8.
  • FIG. 10 is an expanded view of the stiffener-circuit board of the present invention with protective contact sheets prior to assembly.
  • FIG. 11 shows a router bit forming the cavity according to the present invention.
  • FIGS.12-14 show the traveling path of a router according to the present invention.
  • FIG. 15 is a photomicrograph of a wire bond chip package which has a cavity routed therein.
  • FIG. 16 is a photomicrograph of a wire bond chip package wired to a chip which is placed in the cavity in accordance with the present invention.
  • FIG. 17 is a photomicrograph, magnification 5000x, of an ePTFE matrix material used for the dielectric material of a MLPWB processed in accordance with the present invention.
  • FIG. 18 is a photomicrograph, magnification 1000x, of an ePTFE matrix material used for the dielectric material of the MLPWB processed in accordance with the present invention.
  • FIG. 2 is a schematic of a known computer numerically controlled (CNC) router including the router unit 12 and controller 13.
  • the router unit 12 includes a router 14, mounting platform 15 and aligning pins 16.
  • the router 14 has a routing bit 17 which is movable along track 18 in the X-axis direction, guides 19 in the Z-axis direction, and in the Y-axis direction along rails (not shown).
  • the router 14 has a table 20, platform 21 with mounting pins 22.
  • a panel mounted multilayered circuit board 23 is mounted and aligned on platform 21 by the pins 22 which extend upwardly therefrom and fit into pinning hole 24.
  • the router bit 17 is best seen in FIGS. 4 and 5.
  • Bit 18 has three straight flutes 25 with chip-breaker style cutting facets 26 such as an RI style router bit manufactured by Megatool, Inc. of Buena Park, California.
  • the flutes 25 on the bit have facets cut into them and Vs are formed in the edge of the cut facets on the flute.
  • Bit 17 can be manufactured from tungsten carbide, or any other suitable material.
  • FIGS. 6 and 7 show a top and side view, respectively, of a panel 23 containing a plurality of electronic packages 28 of a multilayered printed wire circuit board 29, with pinning holes 24.
  • FIG. 7 is a side view of the panel 23 containing the multilayered printed wire circuit board (MLPWB) 29 having a surface 31 , with a stiffener 30 having a surface 32, where surface 32 is face-down.
  • Stiffener 30 is a solid metal carrier or stiffener, such as, copper or nickel and gold plated copper with a nominal thickness of 20 mils.
  • the stiffener 30 is laminated to MLPWB 29 with any suitable electrically and thermally conductive adhesive, such as, AblefilmTM 550 manufactured by Ablestik.
  • FIGS. 8 and 9 show a bottom and side view, respectively, of panel 23 in the "routing" position Stiffener surface 32 faces upward and the MLPWB surface 31 faces downward.
  • the panel 23 contains pinning holes 24.
  • FIG. 10 shows the panel 23 with a first phenolic entry sheet 33 disposed above surface 32 of the stiffener 30.
  • a second phenolic backup sheet 34 is disposed below the surface 31 of the MLPWB.
  • pinning holes 22 were drilled using a Concept 1 drill manufactured by Excellon.
  • holes 39 are drilled in the packages on the panel 23 where the corners of the cavity or cavities 40 are to be formed. Holes 39 were drilled using a MCO20 drill bit manufactured by Megatool, Inc., or any other suitable drill bit, having a 0.508 mm, 20 mil, diameter.
  • Holes 39 were drilled with a drill bit (not shown) at a feed rate of approximately 10 ipm and a rotational speed of 70 krpm when a solid copper is the stiffener. This bit produces a corner radius of 0.254 mm (10 mils).
  • the MCO20 bit is a "headed" bit, or a drill bit which has a flute margin that is significantly relieved approximately 20 mils from the point of the bit.
  • the panel 23 (Fig. 10), containing the pinning holes 24 was then mounted on the platform 21 (Fig. 3) by aligning the pinning holes 24 with the pins 22, using a clean phenolic backup sheet 34 which has a thickness of approximately 0.61 mm, 24 mils, which was first placed on a platform 21 of the router unit 12.
  • a second sheet of phenolic entry material 31 having a thickness of approximately 0.36 mm, 14 mils, was placed on top surface of the stiffener 30 of the panel 23.
  • the panel 23 is now positioned for forming a cavity.
  • the multilayer circuit boards 29 may contain a plurality of boards 29 arranged in a stacked array.
  • An RI style router bit manufactured by Megatool, Inc. shown in FIGS. 5 and 6, having a 1.588 mm or 62.5 mil diameter, is positioned in the chuck of a router and rotated at a speed of 30 krpm.
  • the bit 17 is inserted into the area circumscribed by holes 39 and is traveled along a loop 41 defined by the holes 39, FIG. 13, in a counterclockwise direction 35, FIGS. 13 and 14.
  • the traveling feed rate was 10 ip along the closed, rectangular loop 40 using a
  • the panel 23 which is invertedly mounted on platform 21 and includes the phenolic material 33 and 34, the stiffener 30, a MLPWB 29 containing conductive traces 36 and solder mask 37.
  • the first routing was conducted to within 50 microns of the finished cavity dimension.
  • a second (finishing) bit e.g., an RI style router bit (Megatool, Inc.) having a 0.794 mm (0.03125") diameter (not shown) was inserted into the chuck of the router. Routing was continued with the finishing bit (not shown) by feeding the finished bit at a counterclockwise direction traveling at a rate of 5 ipm and a rotational speed of 50 krpm in the cavity, to the finished cavity dimension, as shown in Fig. 14. In one embodiment, a double pass with the finishing bit was performed for the final routing to achieve the cleanest possible edges and minimal slope of the cavity wall. The cavity is cut through the entire chip package.
  • RI style router bit Megatool, Inc.
  • a chip was placed in the routed cavity.
  • the cavity had been routed such that the chip is within 10 mils or less of the edge of the cavity.
  • Wire bonds are placed on the chip and connected to the chip package. This results in a non-tiered wire bond package having short wire bond lengths.
  • the chip package is then ready for any further processing. Because the tolerance between the chip and the chip package is 10 mils or less, the length of the wire bonds is approximately 20 mils or less. This is 3-5 times smaller than conventional wire bond lengths. Thus, the smaller wire bond lengths in a package produces a lower inductance than conventional packages and therefore, better overall performance.
  • FIG. 15 and FIG. 16 A finished cavity is shown in FIG. 15 and FIG. 16 in a photomicrograph of a chip wired bonded to conductive contacts on the package.
  • tool cutting parameters are dependent on the thickness and type of material in the chip package, which can be produced from any suitable dielectric material.
  • the electronic package material is formed from any suitable dielectric material, such as, but not limited to, polyimides and polyimide laminates, epoxy resins, epoxy resins in combination with other resin material, organic materials, alone or any of the above combined with fillers.
  • Preferred dielectric materials include a fluoropolymer matrix, where the fluoropolymer can be polytetrafluoroethylene (PTFE), expanded polytetrafluoroethylene (ePTFE) or copolymers or blends.
  • Suitable fluoropolymers include, but are not limited to, polytetrafluorethyiene or expanded polytetrafluoroethylene, with or without an adhesive filler mixture.
  • Suitable materials include Speedboard® bond plies available from W. L. Gore and
  • Speedboard® C which is a prepreg of non-woven material containing a cyanate ester resin in a polytetrafluoroethylene matrix.
  • Speedboard® C has a dielectric constant, (Dk) of 2.6-2.7 at 1 MHz-10GHz, a loss tangent of 0.004 at 1 MHz-10GHz, a dielectric strength greater than 1000 V/mil, a glass transition (T g ) of 220°C, a resin content of 66-68 wt.% and is available in a variety of thicknesses.
  • Speedboard® N prepreg which is a prepreg of a non-woven material containing a multi-functional epoxy adhesive, in an expanded PTFE matrix may also be used.
  • Another suitable dielectric is an expanded PTFE matrix, shown in FIG. 17, that includes a mixture of at least two of a cyanate ester compound, an epoxy compound, a bis- triazine compound and a poly (bis-maleimide) resin.
  • a varnish solution is made by mixing 5.95 pounds of M-30 (Ciba Geigy), 4.07 pounds of RSL 1462 (Shell Resins, Inc.), 4.57 pounds of 2, 4, 6-thbromophenyl-terminated tetrabromobisphenol A carbonate oligomer (BC-58) (Great Lakes Inc.), 136g bisphenol A (Aldrich Company), 23.4g Irganox 1010, 18.1 g of a 10% solution of Mn HEX-CEM in mineral spirits, and 8.40 kg MEK.
  • the varnish solution was further diluted into two separate baths - 20% (w/w) and 53.8% (w/w).
  • the two varnish solutions were poured into separate impregnation baths, and an e-PTFE web was successively passed through each impregnation bath one immediately after the other.
  • the varnish was constantly agitated so as to insure uniformity.
  • the impregnated web was then immediately passed through a heated oven to remove all or nearly all the solvent and partially cure the adhesives, and was collected on a roll.
  • the ePTFE web any be any desired thickness, such as 25 ⁇ m, 40 ⁇ m, for example.
  • a 25 ⁇ m thick material has a mass of approximately 0.9 g and a weight per area of approximately 11.2 to 13.8 g/m 2 .
  • dielectric materials include those where a porous matrix system contains an imbibed or impregnated adhesive-filler mixture.
  • the porous matrix is a non- woven substrate that is imbibed with high quantities of filler and a thermoplastic or thermoset adhesive, as a result of the initial void volume of the substrate, heated to partially cure the adhesive and form a B-stage composite.
  • Substrates include fluoropolymers, such as the porous expanded polytetrafluoroethylene material of U.S. Patent Nos. 3,953,566 and 4,482,516, each of which is incorporated herein by reference.
  • the mean flow pore size (MFPS) should be between about 2 to 5 times or above that of the largest particulate, with a MFPS of greater than about 2.4 times that of the filler being particularly preferred.
  • suitable composites can be prepared by selecting a ratio of the mean flow pore size to average particle size ratio of greater than 1.4. Acceptable composites can also be prepared when the ratio of the minimum pore size to average particle size is at least above 0.8, or the ratio of the minimum pore size to the maximum particle size is at least above 0.4.
  • the MFPS to particle size ratio ratios are performed with a Microtrak® FRA Particle analyzer device.
  • Another mechanism for gauging relative pore and particle sizes may be calculated as the smallest pore size being not less than about 1.4 times the largest particle size.
  • porous expanded polyolefins such as ultra high molecular weight (UHMW) polyethylene, expanded polypropylene, polytetrafluoroethylene made prepared by paste extrusion and incorporating sacrificial fillers, porous inorganic or organic foams, microporous cellulose acetate, can also be used.
  • UHMW ultra high molecular weight
  • expanded polypropylene expanded polypropylene
  • polytetrafluoroethylene made prepared by paste extrusion and incorporating sacrificial fillers
  • porous inorganic or organic foams porous inorganic or organic foams
  • microporous cellulose acetate microporous cellulose acetate
  • the porous substrate has an initial void volume of at least 30%, preferably at least
  • the filler comprises a collection of particles when analyzed by a Microtrak® Model
  • FRA Partical Analyzer device which displays a maximum particle size, a minimum particle size and an average particle size by way of a histogram.
  • Suitable fillers to be incorporated into the adhesive include, but are not limited to,
  • Especially preferred fillers are SiO 2 , ZrO 2 , TiO 2 alone or in combination with non-conductive carbon.
  • Most preferred fillers include filler made by the vapor metal combustion process taught in U.S.
  • Patent No. 4,705,762 such as, but not limited to silicon, titanium and aluminum to produced silica, titania, and alumina particles that are solid in nature, i.e., not a hollow sphere, with a uniform surface curvature and a high degree of sphericity.
  • the fillers may be treated by well-known techniques that render the filler hydrophobic by silylating agents and/or agents reactive to the adhesive matrix, such as by using coupling agents.
  • Suitable coupling agents include, silanes, titanates, zirconates, and aluminates.
  • Suitable silylating agents may include, but are not limited to, functional silyating agents, silazanes, silanols, siloxanes.
  • Suitable silazanes include, but are not limited to, hexamethyldisilazane (Huls H730) and hexamethylcyclotrisilazane, silylamides such as, bis(trimethylsilyl)acetamide (Huls B2500), silylureas such as trimethyisilylurea, and silylmidazoles such as trimethylsilyiimidazole.
  • Titanate coupling agents are exemplified by the tetra alkyl type, monoalkoxy type, coordinate type, chelate type, quaternary salt type, neoalkoxy type, cycloheteroatom type.
  • Preferred titanates include, tetra alkyl titanates, Tyzor® TOT ⁇ tetrakis(2-ethyl-hexyl) titanate,
  • Tyzor® TPT ⁇ tetraisopropyl titanate ⁇ , chelated titanates, Tyzor® GBA ⁇ titanium acetylacetylacetonate ⁇ , Tyzor® DC ⁇ titanium ethylacetacetonate ⁇ , Tyzor® CLA ⁇ proprietary to
  • DuPont ⁇ Monoalkoxy (Ken-React® KR TTS), Ken-React®, KR-55 tetra (2,2 diallyloxymethyl)butyl, di(ditridecyl)phosphito titanate, LICA® 38 neopentyl(diallyl)oxy, tri(dioctyl)pyro-phosphato titanate.
  • Suitable zirconates include, any of the zirconates detailed at page 22 in the Kenrich catalog, in particular KZ 55- tetra (2,2 diallyloxymethyl)butyl, di(dithdecyl)-phosphito zirconate,
  • the aluminates that can be used in the present invention include, but are not limited to Kenrich®, diisobutyl(oleyl)acetoacetylaluminate (KA 301), diisopropyl(oleyl)acetoacetyl aluminate (KA 322) and KA 489.
  • thermosetting matrix adhesives such as, cross-linked vinylic polymers, e.g., divinylbenzene, divinyl pyridine or a sizing of any of the disclosed thermosetting matrix adhesives that are first applied at very high dilution (0.1 up to 1.0% solution in MEK) can be used.
  • certain organic peroxides such as, dicumylperoxide can be reacted with the fillers.
  • the adhesive itself may be a thermoset or thermoplastic and can include polyglycidyl ether, polycyanurate, polyisocyanate, bis-triazine resins, poly (bis-maleimide), norbornene- terminated polyimide, polynorbornene, acetylene-terminated polyimide, polybutadiene and functionalized copolymers thereof, cyclic olefinic polycyclobutene, polysiloxanes, poly sisqualoxane, functionalized polyphenylene ether, polyacrylate, novolak polymers and copolymers, fluoropolymers and copolymers, melamine polymers and copolymers, poly(bis phenycyclobutane), and blends or prepolymers thereof. It should be understood that the aforementioned adhesives may themselves be blended together or blended with other polymers or additives, so as to impact flame retardancy or enhanced toughness.
  • mean flow pore size and minimum pore size were determined using the Coulter® Porometer II (Coulter Electronics Ltd., Luton UK) which reports the value directly.
  • Average particle size and largest particle size were determined using a Microtrak® light scattering particle size analyzer Model No. FRA (Microtrak® Division of Leeds & Northup, North Wales, PA, USA).
  • the average particle size (APS) is defined as the value at which 50% of the particles are larger.
  • the largest particle size (LPS) is defined as the largest detectable particle on a Microtrak® histogram. Alternatively, the largest particle size is defined at the minimum point when the Microtrak® FRA determines that 100% of the particulate have passed.
  • the method for preparing the adhesive-filler dielectric involves: (a) expanding a polytetrafluoroethylene sheet by stretching a lubricated extruded perform to a microstructure sufficient to allow small particles and adhesives to free flow into the void or pore volume; (b) forming a paste from polymeric, e.g., thermoset or thermoplastic material and a filler; and (c) imbibing by dipping, coating, pressure feeding, the adhesive-filler paste into the highly porous scaffold, such as expanded polytetrafluoroethylene.
  • Table 1 shows the effect of the relationship of the substrate mean flow pore size (MFPS) and particulate size.
  • MFPS mean flow pore size
  • EXAMPLE 1 A fine dispersion was prepared by mixing 281.6 g TiO 2 (Tl Pure R-900, Du Pont
  • the partially-cured adhesive composite thus produced comprised of 57 weight percent TiO 2 , 13 weight percent PTFE and 30 weight percent epoxy adhesive.
  • a fine dispersion was prepared by mixing 386 g SiO 2 (HW-11-89, Harbison Walker Corp.) which was pretreated with phenyltrimethoxysilane (04330, Huls/Petrarch) into a manganese catalyzed solution of 200 g bismaleimide triazine resin (BT206OBJ, Mitsubishi Gas Chemical) and 388 g MEK.
  • the dispersion was constantly agitated so as to insure uniformity.
  • a swatch of 0.0002" thick expanded PTFE was then dipped into the resin mixture, removed, and then dried at 165°C for 1 min. under tension to afford a flexible composite.
  • a fine dispersion was prepared by mixing 483 g SiO 2 (HW-11-89) into a manganese- catalyzed solution of 274.7 g bismaleimide triazine resin (BT2060BJ, Mitsubishi Gas Chemical) and 485 g MEK. The dispersion was constantly agitated so as to insure uniformity. A swatch of 0.0002" thick expanded PTFE was then dipped into the resin mixture, removed, and then dried at 165°C for 1 min. under tension to afford a flexible composite. Several plies of this prepreg were laid up between copper foil and pressed at 250 psi in a vacuum-assisted hydraulic press at temperature of 225°C for 90 minutes then cooled under pressure.
  • the resulting dielectric thus produced comprised of 57 weight percent SiO 2 , 4 weight percent PTFE and 39 weight percent adhesive, displayed good adhesion to copper, dielectric constant (at 10 GHz) of 3.2 and dissipation factor (at 10 GHz) of 0.005.
  • a fine dispersion was prepared by mixing 15.44 kg TiO 2 powder (Tl Pure R-900,
  • TiO 2 and the membrane was not compressed at the end was then dipped into the resin mixture, removed, and then dried at 165°C for 1 min. under tension to afford a flexible composite.
  • the partially cured adhesive composite thus produced comprised of 70 weight percent TiO 2 , 9 weight percent PTFE and 21 weight percent adhesive.
  • Several plies of this prepreg were laid up between copper foil and pressed at 500 psi in a vacuum-assisted hydraulic press at temperature of 220°C for 90 minutes then cooled under pressure. This resulting dielectric displayed good adhesion to copper, dielectric constant of 10.0 and dissipation factor of 0.008.
  • a fine dispersion was prepared by mixing 7.35 kg SiO 2 (ADMATECHS SO-E2, Tatsumori LTD) with 7.35 kg MEK and 73.5 g of coupling agent, i.e.,3-glycidyloxypropyltri- methoxysilane (Dynasylan GLYMO (Petrach Systems).
  • SO-E2 is described by the manufacture as having highly spherical silica having a particle diameter of 0.4 to 0.6 mm, a specific surface area of 4-8m 2 /g, a bulk density of 0.2-0.4 g/cc (loose).
  • the Frazier number relates to the air permeability of the material being assayed.
  • Air permeability is measured by clamping the web in a gasketed fixture which is provided in circular area of approximately 6 square inches for air flow measurement.
  • the upstream side was connected to a flow meter in line with a source of dry compressed air.
  • the downstream side of the sample fixture was open to the atmosphere. Testing is accomplished by applying a pressure of 0.5 inches of water to the upstream side of the sample and recording the flow rate of the air passing through the in-line flowmeter (a ball-float rotameter that was connected to a flow meter.
  • the Ball Burst Strength is a test that measures the relative strength of samples by determining the maximum at break.
  • the web is challenged with a 1 inch diameter ball while being clamped between two plates.
  • the Chatillon, Force Gauge Ball/Burst Test was used.
  • the media is placed taut in the measuring device and pressure afixed by raising the web into contact with the ball of the burst probe. Pressure at break is recorded.
  • the web described above, FIG. 18, was passed through a constantly agitated impregnation bath at a speed at or about 3 ft./min, so as to insure uniformity.
  • the impregnated web is immediately passed through a heated oven to remove all or nearly all the solvent, and is collected on a roll.
  • Several plies of this prepeg were laid up between copper foil and pressed at 200 psi in a vacuum-assisted hydraulic press at temperature of 220°C for 90 minutes and then cooled under pressure. This resulting dielectric displayed good adhesion to copper, dielectric constant (10 GHz) of 3.0 and dissipation factor of 0.0085 (10 GHz).
  • Example 4 The physical properties of the particulate filler used in Example 4 and Example 7 are compared below.
  • An ePTFE matrix containing an impregnated adhesive filler mixture, based on SiO 2 prepared from the vapor combustion of molten silicon is prepared as follows. Two precursor mixtures were initially prepared. One being in the form of a slurry containing a silane treated silica similar to that of Example 5 and the other an uncatalyzed blend of the resin and other components. Mixture I The silica slurry is a 50/50 blend of the SO-E2 silica of Example 5 in MEK, where the silica contains a coated of silane which is equal to 1% of the silica weight.
  • the desired resin blend product is an MEK based mixture containing an uncatalyzed resin blend (the adhesive) contains approximately 60% solids, where the solid portion is an exact mixture of 41.2% PT-30 cyanated phenolic resin, 39.5% RSL 1462 epoxy resin, 16.7% BC58 flame retardant, 1.5% Irganox 1010 stabilizer, and 1% bisphenol A co-catalyst, all percentages by weight.
  • the desired product is a mixture of the silica treated with a silane, the uncatalyzed resin blend, and MEK in which 68% by weight of the solids are silica, and the total solids are between 5% and 50% by weight of the mixture.
  • the exact solids concentration varies from run to run, and depends in part on the membrane to be impregnated.
  • the catalyst level is 10 ppm relative to the sum of the PT-30 and RSL1462.
  • mixtures I and II were determined to verify the accuracy of the precursors and compensate for any solvent flash that had occurred. Then mixture I was added to a ten gallon container to provide 12 pounds of solids, e.g., 515 solids content, 23.48 pounds of mixture I. Then mixture II was added to the container to provide 5.64 pounds of solids, e.g., 59.6% solids, 9.46 pounds of mixture II. the manganese catalyst solution (0.6% in mineral spirits), 3.45 grams, was added to the mixture of mixture I and mixture II and blended thoroughly to form a high solids content mixture.
  • the bath mixture for impregnating an ePTFE matrix 28% solids mixture, was prepared by adding sufficient MEK to the high solids content mixture to a total weight of 63 pounds.
  • a fine dispersion was prepared by mixing 26.8 grams Furnace Black (Special Schwarz
  • GLYMO CAS #2530-83-8 3-glycidyloxypropyl-trimethoxysilane (Petrach Systems).
  • the dispersion was subjected to ultrasonic agitation for 1 minute, then added to a stirring dispersion of 17.5 pounds SiO 2 (SO-E2) in 17.5 pounds MEK which had previously been ultrasonically agitated.
  • SO-E2 stirring dispersion of 17.5 pounds SiO 2
  • MEK 3-glycidyloxypropyl-trimethoxysilane
  • an adhesive varnish was prepared by adding the following: 3413 grams of a 57.5% (w/w) mixture of Primaset PT-30 in MEK, 2456 grams of a 76.8% (w/w/) mixture of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w) solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w) solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010, 3.21 grams of a 0.6% (w/w) solution of Mu HEX-CEM (OMG Ltd.) in mineral spirits, and 2.40 kg MEK.
  • An adhesive varnish was prepared by adding the following: 3413 grams of a 57.5% (w/w) solution of Primaset PT-30 (PMN P-88-1591)) in MEK, 2456 grams of a 76.8% (w/w) solution of RSL 1462 in MEK, 1495 grams of a 53.2% (w/w) solution of BC58 (Great Lakes, Inc.) in MEK, 200 grams of 23.9% (w/w) solution of bisphenol A (Aldrich Company) in MEK, 71.5 grams Irganox 1010, 3.21 grams of a 0.6% (w/w) solution of Mn HEX-CEM in mineral spirits, and 2.40 kg MEK.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

La présente invention concerne un procédé destiné à former des cavités dans des boîtiers de puces, le procédé consistant à monter le boîtier en position inversée, à engager une mèche de toupie dans le boîtier, et à déplacer la mèche de toupie le long d'une zone circonscrite sur le boîtier dans le sens contraire des aiguilles d'une montre, ce qui permet de réduire l'espacement du boîtier par rapport à la puce, la longueur des câbles de connexion et l'inductance.
PCT/US1997/018804 1996-11-08 1997-10-22 Procede de fabrication de cavites de grande tolerance dans des boitiers de puces WO1998020545A1 (fr)

Priority Applications (1)

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AU49872/97A AU4987297A (en) 1996-11-08 1997-10-22 Method for manufacturing high tolerance cavities in chip packages

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US74559396A 1996-11-08 1996-11-08
US08/745,593 1996-11-08

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10526477B2 (en) 2013-05-22 2020-01-07 Eovations, Llc Plastics-based manufactured article and process for forming

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728469A (en) * 1971-03-11 1973-04-17 Owens Illinois Inc Cavity structure
US3995969A (en) * 1968-10-18 1976-12-07 Fleming Lawrence T Flat circuit insulation stripping apparatus
US4515505A (en) * 1982-10-28 1985-05-07 International Business Machines Corporation Pressure foot assembly for an end mill delete cutter
WO1991000618A1 (fr) * 1989-07-03 1991-01-10 General Electric Company Systemes electroniques disposes dans un environnement soumis a des efforts importants
EP0490653A1 (fr) * 1990-12-11 1992-06-17 Sharp Kabushiki Kaisha Dispositif semi-conducteur à support de bande
US5205032A (en) * 1990-09-28 1993-04-27 Kabushiki Kaisha Toshiba Electronic parts mounting apparatus
US5441474A (en) * 1992-11-25 1995-08-15 Osaki Engineering Co., Ltd PCB working machine and method
WO1996004681A1 (fr) * 1994-07-29 1996-02-15 Havant International Limited Fixation directe de puces
JPH0878573A (ja) * 1994-09-06 1996-03-22 Hitachi Cable Ltd Ｂｇａパッケージ

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3995969A (en) * 1968-10-18 1976-12-07 Fleming Lawrence T Flat circuit insulation stripping apparatus
US3728469A (en) * 1971-03-11 1973-04-17 Owens Illinois Inc Cavity structure
US4515505A (en) * 1982-10-28 1985-05-07 International Business Machines Corporation Pressure foot assembly for an end mill delete cutter
WO1991000618A1 (fr) * 1989-07-03 1991-01-10 General Electric Company Systemes electroniques disposes dans un environnement soumis a des efforts importants
US5205032A (en) * 1990-09-28 1993-04-27 Kabushiki Kaisha Toshiba Electronic parts mounting apparatus
EP0490653A1 (fr) * 1990-12-11 1992-06-17 Sharp Kabushiki Kaisha Dispositif semi-conducteur à support de bande
US5441474A (en) * 1992-11-25 1995-08-15 Osaki Engineering Co., Ltd PCB working machine and method
WO1996004681A1 (fr) * 1994-07-29 1996-02-15 Havant International Limited Fixation directe de puces
JPH0878573A (ja) * 1994-09-06 1996-03-22 Hitachi Cable Ltd Ｂｇａパッケージ

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 096, no. 007 31 July 1996 (1996-07-31) *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10526477B2 (en) 2013-05-22 2020-01-07 Eovations, Llc Plastics-based manufactured article and process for forming

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