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WO1998013873A1 - Condensateur de derivation de drain a emetteur integre destine aux applications pour dispositifs a energie hyperfrequence ou radiofrequence - Google Patents

Condensateur de derivation de drain a emetteur integre destine aux applications pour dispositifs a energie hyperfrequence ou radiofrequence Download PDF

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Publication number
WO1998013873A1
WO1998013873A1 PCT/US1997/017242 US9717242W WO9813873A1 WO 1998013873 A1 WO1998013873 A1 WO 1998013873A1 US 9717242 W US9717242 W US 9717242W WO 9813873 A1 WO9813873 A1 WO 9813873A1
Authority
WO
WIPO (PCT)
Prior art keywords
emitter
circuit
bypass capacitor
metal layer
bypass
Prior art date
Application number
PCT/US1997/017242
Other languages
English (en)
Inventor
Ping Li
Original Assignee
The Whitaker Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by The Whitaker Corporation filed Critical The Whitaker Corporation
Priority to AU46520/97A priority Critical patent/AU4652097A/en
Publication of WO1998013873A1 publication Critical patent/WO1998013873A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a bipolar transistor having an integrated bypass capacitor circuit to curb the ill effects of negative feedback resulting from emitter ballast resistance.
  • the present invention relates to a technique for improving the performance of semiconductor bipolar transistors, particularly for power applications.
  • ballasting resistance is optimally distributed over the emitter fingers so that the feedback can be effectively utilized to control run-away current in an individual or a small group of emitter fingers.
  • a thin film or implanted transistor is placed at the end of each emitter finger or pair of fingers.
  • This technique is advantageous in that one can readily modify the resistance value by modifying the geometry of the resistor without changing the resistor fabrication process.
  • the interface between the device contacts in the heat sink is a relatively thick region of metal.
  • This region of metal is deposited in many ways but is usually referred to as a bump.
  • the resistance at the emitter fingers intrinsically create a negative feedback which degrades the performance of the device.
  • a well known technique to reduce this negative feedback is to have a bypass capacitor of relatively large magnitude in parallel with the resistor at the emitter finger. This large magnitude bypass capacitance is an effective rf - pass. That is, the reactance from the bypass capacitor circuit is insignificant relative to the ballasting resistor at high frequencies.
  • the emitter resistor is relatively small, but has a finite resistance value.
  • the capacitor required to effectively create an rf bypass must be relatively large.
  • it is very difficult to create a bypass capacitor circuit having a large enough capacitance value on the device because of the relatively small area provided at the device level for this capacitor.
  • Attempts to form the bypass capacitance off the chip would have other potential deleterious effects.
  • bond wires require to perform the necessary electrical connections. Because the emitters fingers have to be ballasted separately, the size of the bonding wires and wire bond pads has to be less than 10 microns. The technology of today renders this task impossible .
  • the present invention is a modified silicon bipolar junction transistor in integrated form having a ballasting resistor integrated onto a silicon chip.
  • This resistor is for the purposes of thermal stability of the transistor during operation.
  • a large bypass capacitor circuit is placed in parallel with the ballasting resistor in integrated circuit form.
  • a modified metallization pattern for the silicon BJT is utilized.
  • a heterolithic microwave integrated circuit glass substrate has the integrated bypass capacitor circuit fabricated directly thereon, and this circuit is electrically in contact with the emitter fingers of the BJT.
  • the BJT is mounted in a flip-chip fashion.
  • the modified transistor has two emitter contact, the first electrically connected to the integrated ballasting resistor, while the second is directly in contact with the parallel capacitor circuit, the rf bypass capacitor.
  • the first emitter contacts are connected to a silicon pedestal of the HMIC which is connected to electrical ground.
  • the bypass capacitor is fabricated on top of the silicon pedestal, and preferably is a circuit of two or more parallel capacitors, to effect an equivalent capacitance of the desired magnitude in order to properly effect the rf bypass.
  • the capacitor has three metal layers sandwiching two dielectric layers with electrical connections to form the parallel circuit of the capacitors. These capacitors are formed by standard photolithographic techniques, making large scale fabrication readily possible.
  • the final design has the bypass capacitor circuit providing a low loss, low reactance path for the high frequency, for example rf or microwave frequency signal so that the negative feedback caused by the ballasting resistor in prior techniques is minimized as great as possible.
  • the device of the present invention has a higher output power with a higher power gain at a greater efficiency than prior techniques not utilizing the capacitance circuit of the present invention.
  • the present invention results in a HMIC BJT circuit wherein the rf signal is bypassed from the ballasting resistor enabling the use of a larger ballasting resistor without degrading the device performance. Accordingly, the resultant device has better thermal stability than devices not utilizing the capacitor circuit of the present invention.
  • bypass capacitor circuit in integrated circuit form on a HMIC.
  • Figure 1 shows the circuit of the present invention in cross section.
  • Figure 2 shows the structure of Figure 1 prior to the mounting of the BJT chip.
  • Figure 3 is a schematic circuit of the silicon transistor and ballasting and bypass circuits of the present invention.
  • Figure 4 is a top view of the metal pattern of the silicon transistor of the present invention.
  • Figure 5 is the metal pattern of the present invention on the silicon pedestal in the HMIC substrate.
  • the present invention is shown in cross sectional view in Figure 1.
  • a heterolithic microwave integrated circuit (HMIC) substrate 100 having regions of glass 101 and silicon pedestals 102 has disposed thereon the bipolar junction transistor (BJT) 103.
  • the BJT is flip-chip mounted with the collector side at 104 the base region at 105 and the emitter at 106.
  • the present invention has emitter region having two contacts designated 107 and 108 respectively.
  • the device 103 is flip-chip mounted.
  • the emitter of the modified transistor of the present invention has two emitter contacts, 307 and 308 respectively.
  • the emitter contact 308 is connected to the emitter through the bypass capacitor circuit 310 as shown.
  • This circuit is a parallel connection of capacitors designated 310.
  • the contact 307 is connected to the emitter through the ballasting resistor 309.
  • the emitter ballasting resistance can be fabricated with two methods using p * region in the p + ring to achieve the required ballasting resistance value or depositing polysilicon over the p region and the required ballasting resistance value can be achieved by adjusting the As * implantation onto the polysilicon.
  • Typical values for the ballasting resistor are in the range on order of 75 ohm to 200 ohm per emitter finger and 0.3 to 1 ohm per device and the individual capacitors of the present invention have typical capacitance's on the order of 600 to 900 pF per device for a equivalent reactance in the range of 0.05 to 0.2 ohms/device. These values are chosen for operation in the frequency range on the order of from 1 Ghz to 4 GHz .
  • the present invention is shown with the BJT not mounted to the HMIC substrate.
  • a review of Figure 2 shows the various elements of the bypass and ballasting circuitry.
  • the HMIC substrate 200 has a first bottom metal layer 201 with a first layer of dielectric material 202 disposed thereon.
  • the bottom metal layer is electrically connected to a dc ground potential. Thereafter, the middle metal layer 203 is disposed on top of the first dielectric layer 202 and a second dielectric layer 204 is disposed thereon. Finally, a top metal layer 205 together with an airbirdge 206 complete the bypass capacitor circuit.
  • the HMIC substrate of the present invention has embedded silicon pedestals. These are fabricated by known techniques. Additionally, other techniques to form HMIC substrates with silicon pedestals to effect the electrical connections, to include electrical ground, are effected by known techniques.
  • the bypass capacitor of the present invention is fabricated on top of the silicon pedestal. The capacitor has three metal layers and two dielectric layers electrically connected so as to form two capacitors connected electrically in parallel.
  • the resultant capacitance is of a magnitude great enough to effect the low reactance path at the desired frequencies as is described above.
  • the top and bottom metal layers 205 and 201 respectively, form one plate of the capacitor connecting to the ground and the middle metal layer 203 is the other plate of the capacitor connecting to the emitter. These connections are effected by standard metal bumps as is well known to one of ordinary skill in the art.
  • the various layers of metal and dielectric are formed using standard photolithographic processes. Ti/Pt/Au as the electrodes can be put down with standard lift off process while the dielectric thin film can be grown using either CVD or reactive spattering processes. Then the dielectric thin film can be patterned via either wet or dry etching processes.
  • the bottom layer of metal, 201 is disposed directly on top of the silicon pedestal while the top layer 205 is electrically in contact with the ground effected by the silicon pedestal through the airbridge 206.
  • the layers of dielectric material are preferably SiC, having a high dielectric constant and a high thermal conductivity, preferable characteristics for this application. AlN may also be used as dielectric material .
  • the metallization is preferably of Ti/PT/Au.
  • the top metal pattern of the silicon transistor is shown with the collector region on the backside of the transistor.
  • emitter contacts 408 make electrical connections to the middle metal layer as is shown in Figure 1 and 2
  • the emitter contact 407 makes contact to the bottom metal layer as is shown in Figures 1 and 2 as well.
  • the base metallization 409 makes contact to the structure on the HMIC metallization for the base at 109 in Figure 1.
  • the metal pattern on the silicon pedestal in the HMIC substrate is shown. This is a top view of the structure shown in Figure 4.
  • the middle metal layer 503 is shown as well as the dc ground layer 501, shown at 207 in Figure 2.
  • DC ground layer 507 is the same as metal layer 501.
  • the airbridge is shown at 506.
  • the present invention is designed to operate in frequencies in the range of 1 - 4 GHz at power output levels on the order of 5 - 20 w.
  • the present invention is specifically drawn to improving the gain and output power the efficiency of the bipolar junction transistor as is described above, the improvement of thermal stability through the ballasting transistor while curbing the ill effects of the negative feedback of the ballasting resistor through the use of the bypass capacitance circuit described.
  • the primary reason that the structure of the present invention provides the advantages described above is through the use of large scale integrated circuit processing techniques to effect the bypass capacitance.
  • the ability to fabricate the relatively large capacitance values required to achieve effective bypass capacitor circuit at high frequency in a relatively small area on the chip has great advantage in the performance of the device as well as in the overall cost of fabrication.
  • the ability of the bypass capacitor circuit to be formed directly on a chip enables the performance realized by avoiding unnecessary residence conditions as described above in cases where the capacitor circuit is offset of the chip.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un circuit de transistor bipolaire de puissance, destiné aux applications à énergie hyperfréquence ou radiofréquence. Le dispositif permet d'éviter le phénomène dit 'd'emballement thermique' grâce à deux contacts d'émetteur (E1 et E2) équipant le transistor. Lesdits contacts d'émetteur E1 et E2 sont respectivement connectés à un condensateur de dérivation et à une résistance ballast, selon un montage en parallèle. Le condensateur de dérivation est intégré au socle en silicium du substrat de verre d'un circuit intégré hyperfréquence hétérolithique (HMIC). On connecte le condensateur de dérivation aux contacts d'émetteur du transistor bipolaire en utilisant la technique des puces à bosses. Cela permet de créer un circuit de transistor bipolaire de puissance à HMIC avec des puces à bosses qui possède un meilleur gain et une stabilité thermique plus élevée.
PCT/US1997/017242 1996-09-27 1997-09-25 Condensateur de derivation de drain a emetteur integre destine aux applications pour dispositifs a energie hyperfrequence ou radiofrequence WO1998013873A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU46520/97A AU4652097A (en) 1996-09-27 1997-09-25 Integrated emitter drain bypass capacitor for microwave/rf power device applications

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US2683996P 1996-09-27 1996-09-27
US60/026,839 1996-09-27

Publications (1)

Publication Number Publication Date
WO1998013873A1 true WO1998013873A1 (fr) 1998-04-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/017242 WO1998013873A1 (fr) 1996-09-27 1997-09-25 Condensateur de derivation de drain a emetteur integre destine aux applications pour dispositifs a energie hyperfrequence ou radiofrequence

Country Status (2)

Country Link
AU (1) AU4652097A (fr)
WO (1) WO1998013873A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1696487A1 (fr) * 2005-02-23 2006-08-30 ATMEL Germany GmbH Arrangement haute fréquence

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211279A (ja) * 1991-11-20 1993-08-20 Nec Corp 混成集積回路
JPH07221190A (ja) * 1994-02-07 1995-08-18 Hitachi Ltd 半導体集積回路装置
WO1996026548A1 (fr) * 1995-02-24 1996-08-29 Telefonaktiebolaget Lm Ericsson Contournement des resistances de protection d'emetteur pour transistors de puissance haute frequence
WO1997021246A1 (fr) * 1995-12-08 1997-06-12 The Whitaker Corporation Circuits integres, heterolithiques, hyperfrequence servant a l'adaptation d'impedance et procede de fabrication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05211279A (ja) * 1991-11-20 1993-08-20 Nec Corp 混成集積回路
JPH07221190A (ja) * 1994-02-07 1995-08-18 Hitachi Ltd 半導体集積回路装置
WO1996026548A1 (fr) * 1995-02-24 1996-08-29 Telefonaktiebolaget Lm Ericsson Contournement des resistances de protection d'emetteur pour transistors de puissance haute frequence
WO1997021246A1 (fr) * 1995-12-08 1997-06-12 The Whitaker Corporation Circuits integres, heterolithiques, hyperfrequence servant a l'adaptation d'impedance et procede de fabrication

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 017, no. 649 (E - 1468) 2 December 1993 (1993-12-02) *
PATENT ABSTRACTS OF JAPAN vol. 095, no. 011 26 December 1995 (1995-12-26) *
PERKO R: ""GLASS MICROWAVE IC PACKAGING TECHNOLOGY"", ELECTRO INTERNATIONAL '94, BOSTON, MAY 10 - 12, 1994, 10 May 1994 (1994-05-10), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 857 - 862, XP000549404 *
PING LI ET AL: "A new technology for Si microwave power transistor manufacturing", 1996 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST (CAT. NO.96CH35915), 1996 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, SAN FRANCISCO, CA, USA, 17-21 JUNE 1996, ISBN 0-7803-3246-6, 1996, NEW YORK, NY, USA, IEEE, USA, pages 103 - 106 vol.1, XP002053834 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1696487A1 (fr) * 2005-02-23 2006-08-30 ATMEL Germany GmbH Arrangement haute fréquence
US7605450B2 (en) 2005-02-23 2009-10-20 Atmel Automotive Gmbh High frequency arrangement

Also Published As

Publication number Publication date
AU4652097A (en) 1998-04-17

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