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WO1998009327A1 - Procede de production d'un circuit integre a semiconducteur, et circuit integre a semiconducteur - Google Patents

Procede de production d'un circuit integre a semiconducteur, et circuit integre a semiconducteur Download PDF

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Publication number
WO1998009327A1
WO1998009327A1 PCT/JP1996/002408 JP9602408W WO9809327A1 WO 1998009327 A1 WO1998009327 A1 WO 1998009327A1 JP 9602408 W JP9602408 W JP 9602408W WO 9809327 A1 WO9809327 A1 WO 9809327A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
semiconductor integrated
circuit device
manufacturing
logic
Prior art date
Application number
PCT/JP1996/002408
Other languages
English (en)
Japanese (ja)
Inventor
Hiroyuki Araya
Masaaki Kudo
Mitsuru Aiba
Akira Ohtaka
Yoshiki Nakamura
Kazuo Tanaka
Terumi Sawase
Original Assignee
Hitachi, Ltd.
Hitachi Tohbu Semiconductor, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/002408 priority Critical patent/WO1998009327A1/fr
Publication of WO1998009327A1 publication Critical patent/WO1998009327A1/fr

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Definitions

  • Patent application title Method for manufacturing integrated circuit device and semiconductor integrated circuit device
  • the present invention relates to a semiconductor integrated circuit device manufacturing method and a semiconductor integrated circuit device technology, and more particularly to a technology that is effective when applied to a semiconductor integrated circuit device required to be developed in a short time.
  • the gate array is a semiconductor integrated circuit device that prepares a master wafer that has been subjected to a diffusion process in advance and realizes a logic circuit desired by a user in a wiring process.
  • a plurality of elements such as transistors and resistors are arranged regularly on a semiconductor substrate in advance, and when developing a product, these elements are connected by wiring according to the logic desired by the user.
  • a semiconductor integrated circuit device that configures a logical function desired by the user.
  • FPGA field integrated circuit
  • FPGAs place logic cells, wiring, program elements, etc. on a semiconductor substrate in advance.
  • the semiconductor integrated circuit device that connects the logic cells and the like by programming the program element according to the logic desired by the user, and then configures the logic function desired by the user. It is.
  • manufacture starts from a wiring process in a gate array, while manufacture starts from a writing process to a program element after an assembly process in an FPGA. Because you can get started, FPGAs can have much shorter TATs than gate arrays.
  • SRAM Static Random Access Memory
  • the semiconductor integrated circuit device having an anti-fuse element is described in, for example, Nikkei BP, October 1992, “Nikkei Micro Devices”, pp. 43-45.
  • This document describes a structure in which a hole is made in an interlayer film sandwiched between upper and lower metal wiring layers, and a dielectric amorphous silicon film is filled therein in such a manner as to contact the upper and lower metal wiring layers. An anti-fuse element is described.
  • nM ⁇ S n-channel metal oxide semiconductor
  • MOS FET n-channel metal oxide semiconductor
  • timing verification in the FPGA can be used directly for the gate array.
  • the area of the semiconductor chip is increased by the amount of the program element, and the yield is lower and the cost is higher than that of a gate array.
  • the area can be made smaller than when an SRAM cell is used.However, since a special manufacturing process of forming an anti-fuse is added, the yield is lower than that of a gate array. The cost is high. Also, when a large number of FPGAs are required, each of them needs to be programmed, and on the other hand, the user side becomes complicated and time-consuming and time-consuming. From this point of view, FPGAs are mainly used as prototypes of semiconductor integrated circuit devices for the purpose of debugging the logic operation when manufacturing gate arrays in advance by taking advantage of the short TAT. Many.
  • the timing design and the placement and routing design are redone. Rather, to provide a technology capable of manufacturing a semiconductor integrated circuit device that forms a predetermined logical circuit.
  • Another object of the present invention is to provide a semiconductor integrated circuit having the same desired logic circuit using an anti-fuse type field programmable semiconductor integrated circuit device. It is an object of the present invention to provide a technique capable of manufacturing a semiconductor integrated circuit device having a predetermined logic circuit without significantly adding a photomask when manufacturing a circuit device.
  • Another object of the present invention is to provide a semiconductor integrated circuit device having the same desired logic circuit using an anti-fuse type field programmable semiconductor integrated circuit device. It is an object of the present invention to provide a technology capable of reducing a logic de-nocking process of a semiconductor integrated circuit device.
  • Another object of the present invention is to provide a semiconductor integrated circuit device having the same desired logic circuit using an anti-fuse type field programmable semiconductor integrated circuit device. It is an object of the present invention to provide a technology capable of shortening a development period of a semiconductor integrated circuit device.
  • Still another object of the present invention is to provide a semiconductor integrated circuit device having the same desired logic circuit as an anti-fuse type field programmable semiconductor integrated circuit device.
  • An object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor integrated circuit device having a circuit.
  • the method of manufacturing a semiconductor integrated circuit device of the present invention uses a field-programmable semiconductor integrated circuit device capable of forming a desired logic circuit by a write T.
  • a field-programmable semiconductor integrated circuit device capable of forming a desired logic circuit by a write T.
  • connection hole such that the-part of the first wiring pattern is exposed in the second interlayer insulating film. Drilling a hole,
  • the photomask used in the manufacture of the field programmable semiconductor integrated circuit device is shared. Can be used.
  • the operation check is performed based on the logic used during the logic debugging of the field programmable semiconductor integrated circuit device. For verification Wiring board can be used.
  • FIGS. 1 and 2 are flowcharts showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
  • FIG. 3 is a flow chart showing a semiconductor integrated circuit device obtained through the manufacturing process of the semiconductor integrated circuit device of FIG.
  • FIGS. 4 to 7 are explanatory diagrams for explaining a method of writing data to the anti-fuse portion.
  • FIGS. 8 to 14 are semiconductor integrated circuits having an anti-fuse portion in the manufacturing process of the semiconductor integrated circuit device of FIG.
  • FIG. 22 is a plan view of a principal part of a semiconductor integrated circuit device manufactured by a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention
  • FIGS. FIG. 4 is an explanatory diagram for describing a method of manufacturing a semiconductor integrated circuit device studied by the present inventors.
  • the FPGA is a semiconductor integrated circuit device in which a user can freely configure a logic circuit by writing information of a predetermined logic circuit.
  • a standard manufacturing process in an anti-haze type FPGA studied by the present inventors will be described with reference to FIG.
  • the photomask 31a1 is a mask used for transferring a pattern in an exposure step in an element forming step and a wiring forming step (step 500).
  • the semiconductor wafer 3 on 0 a is deposited an interlayer insulating film made of silicon dioxide (S i 0 2) or the like by a CVD (Chemical Vapor Deposition) method or the like (Step 5 0 1).
  • the photomask 31a2 is a mask for transferring the pattern of the connection hole to the area where the antifuse portion is to be formed, and is a mask unique to the manufacture of FPGA (step 502).
  • an antifuse portion is formed on the semiconductor wafer 30a (step 503). That is, after an antifuse formation film made of, for example, amorphous silicon is deposited on the semiconductor wafer 30a by CVD or the like (step 503a), the antifuse formation film is subjected to photolithography technology. The antifuse portion is formed by performing etching using etching technology.
  • the photomasks 3 1 a 3 is a mask for transferring a pattern of the anti-fuse unit, which is a unique masks in the manufacture of FPGA (Step 5 0 3 b).
  • FPGA is manufactured by forming subsequent wiring dust and a protective film.
  • This photomask 31a4 is a mask used when transferring the wiring pattern of the (N + 1) th layer and the wiring patterns of the wiring layers thereafter (step 504).
  • Step 600 After depositing an interlayer insulating film made of, for example, SiO 2 on the semiconductor wafer 30 b (step 601), the interlayer insulating film is formed in a region for connecting upper and lower wiring layers in the interlayer insulating film.
  • connection hole that exposes a part of the underlying wiring is formed by photolithography and etching.
  • the photomask 31b2 is a mask used for transferring a pattern of a connection hole for connecting different wiring layers, and is a mask unique to the manufacture of a gate array (step 62).
  • a gate array is manufactured by forming a wiring layer and a protective film thereafter.
  • the photomask 31b3 is a mask used when transferring the wiring pattern of the (N + 1) th layer and the wiring patterns of the wiring layers thereafter, and is a mask unique to the manufacture of the gate array ( Step 63).
  • the manufacturing process a logic de-nocking is performed using an FPGA, and the obtained logic circuit is obtained.
  • the manufacturing technology of a gate array having the same logical function will be described with reference to FIG. 25
  • the left side shows the manufacturing process of the FPGA
  • the right side shows the manufacturing process of the gate array.
  • connection relationship between the logic circuits is determined based on the data of the logic circuit desired by the user (step 701). Then, based on the data obtained in the logic design process, connection data of the logic circuit (hereinafter, referred to as a netlist) is created (step 702).
  • Step 703 After converting the netlist into an FPGA format (Step 703), a plurality of logic circuit blocks are appropriately arranged in the semiconductor chip area based on the converted data. Then, a wiring route between the logic blocks is determined (step 704).
  • timing simulation is performed on the FPGA.
  • step 706A programming (programming) is performed on the FPGA (step 706A) to obtain the FPGA 32 in which the logic circuit desired by the user is configured, and the logic for mounting the FPGA 32 when performing the logic debugging of the FPGA 32 is performed.
  • a wiring board 33a for logic verification is obtained through a design process 706B1 and a manufacturing process 706B2 of a verification wire board for verification.
  • a plurality of FPGAs 32 are mounted on the above-described wiring board 33a, and logic debugging of the FPGAs 32 is performed.
  • the logic of the manufactured FPG A is verified, and if correction is necessary, the data is fed back to the logic design process 701, the placement and routing in the FPGA 704, etc. ( Step 707).
  • a gate array based on the netlist is converted.
  • a plurality of logic circuit blocks are appropriately arranged in the chip area, and a wiring path between the logic circuit blocks is determined (step 709).
  • a timing simulation is performed on the gate array.
  • a simulation or the like of a logic circuit in consideration of the delay time in the wiring or the circuit is performed (step 710).
  • the gate array 34 is obtained using the photomask (step 711 A2).
  • the design process 711B1 and the manufacturing process 711B2 of the wiring board for logic verification on which the gate array 34 is mounted A wiring board 33b for logic verification of the gate array is obtained separately from the board 33a.
  • a plurality of gate arrays 34 are mounted on the above-described wiring board 33b, and logic debugging of the gate arrays 34 is performed.
  • the logic of the manufactured gate array is verified, and if correction is necessary, the data is fed back to the above step (709) and the like (step 712).
  • the placement and wiring step 709 and the timing simulation step 710 are required in the manufacturing process of the gate array.
  • FIG. 26 shows a case where the FPGA is replaced with a gate array by the above-described method.
  • the gate array 34 manufactured by this method has a FPGA 32 And size are completely different, and usually smaller than FPGAs. Also, the position of the bonding head 35 for the power supply and the input / output signal is different.
  • the configuration is as shown in FIG.
  • the manufacturing steps for the FPGA and the gate array are shared. Therefore, the photomask used in the steps 100 to 105 uses the same photomask for the FPGA and the gate array.
  • the data of the connection hole where the anti-fuse portion of the anti-fuse portion of the FPGA which is to be a conductive portion is left, and the non-conductive portion is left.
  • Data conversion is performed to remove the data in the connection hole where the anti-fuse section is located, and the resulting data is obtained.
  • pattern data of a heat mask used in the step 106B1 of forming a connection hole in the interlayer insulating film is created.
  • a common photomask is used for patterning the second layer wiring in the manufacturing process of the FPGA and the gate array.
  • This semiconductor wafer is made of, for example, a Si single crystal of a predetermined conductivity type, and is commonly used by the FPGA and the gate array (step 100).
  • an element such as a MOS FET, a bipolar transistor, a diode, a resistor and a capacitor is formed (Step 101).
  • first interlayer insulating film made of, for example, silicon dioxide (SiO 2 ) is deposited on the semiconductor wafer by a CVD (Chemical Vapor Deposition) method or the like.
  • CVD Chemical Vapor Deposition
  • the conductive film is patterned by using photolithography technology and dry etching technology, etc.
  • a layer wiring (first wiring pattern) is formed (step 104).
  • an interlayer insulating film (second interlayer insulating film) is deposited on the semiconductor wafer by a CVD method or the like.
  • the interlayer insulating film is made of, for example, S i 0 2, etc., the first layer wiring Yotsute thereto is covered (step 105).
  • the steps up to step 105 are common manufacturing steps for the FPGA and the gate array. Therefore, for example, the photomasks FM1 and FM2 used in the element forming step 101 and the first layer wiring patterning step 104 also use a common photomask for the FPGA and the gate array.
  • the manufacture of the FPGA or the gate array can be started from the step 106 A 1, 106 B 1 of forming a connection hole in the insulating layer between the second and third layers. Therefore, the gate array The manufacturing period can be shortened.
  • this semiconductor wafer from this semiconductor wafer,
  • FPG A can be manufactured, and gate arrays can also be manufactured.
  • the process is divided into an FPGA manufacturing process and a gate array manufacturing process.
  • the manufacturing process of the gate array will be described after the manufacturing process of the FPGA is described.
  • connection hole is formed in the second layer insulating film so that a part of the first scrap wiring is exposed.
  • the photomask FM3 used for drilling the connection holes is a mask unique to the FPGA manufacturing process (Step 106A1).
  • an amorphous silicon or the like is deposited by a CVD method or the like (Step 106 A).
  • the antifuse forming film is patterned by photolithography and dry etching.
  • the anti-fuse forming film is also a photomask unique to the manufacture of FPG A (Step 106A3).
  • a conductor film for forming the second layer wiring is deposited by a sputtering method or the like (Step 106A4), and then the conductor film is patterned by a photolithography technique, a dry etching technique, or the like, thereby forming the second layer.
  • Form wiring (second wiring pattern).
  • the photomask FM4 used at this time is a common mask between the FPGA and the gate array (Step 106 A5).
  • Step 106 A6 After a surface protective film or the like is deposited on the semiconductor wafer to cover the second layer wiring, an opening for a bonding pad is formed at a predetermined position, and the wafer process is completed (Step 106 A6). ).
  • the semiconductor wafer is divided into individual semiconductor chips, and the individual semiconductor chips are packaged (process). 1 06A 7). This produces the FPGA.
  • a connection hole is formed in the second interlayer insulating film so that a part of the first layer wiring is exposed.
  • the used photomask FM5 is a mask that is proprietary for manufacturing a gate array.
  • the pattern on the photomask FM5 is formed based on data of a logic circuit obtained by logic debugging using an FPGA as described later (step 106B1).
  • Step 106B2 a conductor film for forming a second-layer wiring is deposited on the semiconductor wafer by a sputtering method or the like.
  • the conductor film is patterned by photolithography, dry etching, or the like.
  • the photomask FM4 used at this time uses a common mask for the FPGA and the gate array (step 106B3).
  • step 106 B 4 After a building surface protection film or the like is deposited on the semiconductor wafer to cover the second layer wiring, an opening for a bonding pad is formed at a predetermined position, and the wafer process is completed (step 106 B 4). ).
  • Step 106 B 5 After conducting an electrical test on the individual semiconductor chips on the semiconductor wafer, dividing the semiconductor wafer into individual semiconductor chips, and packaging the individual semiconductor chips ( Step 106 B 5). In this way, a gate array is manufactured.
  • FIG. 2 the left side shows the manufacturing process of the FPGA, and the right side shows the manufacturing process of the gate array.
  • connection relationship between the logic circuits is determined based on the data of the logic circuit desired by the user (step 201). Then, a netlist of the logic circuit is created based on the data obtained in the logic design process.
  • This netlist is a design data representing the connection relationship of the logic circuit desired by the user, and is in a form that can be processed by a computer (step 202).
  • Step 203 after converting the netlist into a format for the FPGA (Step 203), based on the converted data, a logic such as a basic cell or a macro cell is placed in a semiconductor chip area.
  • Appropriate circuit block Place 1mm and determine the wiring route between the logical circuit blocks.
  • this wiring process is performed, for example, in a wiring layer The process is performed in consideration of process restrictions such as number, delay time from operation speed of the semiconductor integrated circuit device, and impedance of power supply wiring. (Step 204).
  • This timing simulation step is a step in which a computer verifies whether or not the logic circuit data and the test data realize the logical operation as intended by the user, and the wiring and each circuit (gate and cell) are verified. This is the step of performing logic simulation taking into account the delay time (step 205).
  • step 206A writing (programming) is performed on FPG A (step 206A). Writing to the FPGA depends on whether the antifuse section is conducting or not. The FPGA writing method will be described later in detail.
  • the FPGA 1 in which the logic circuit desired by the user is configured is obtained, and at the time of logic debugging of the FPGA 1, the FPG A 1 is mounted.
  • B1 and the manufacturing process 206B2 a wiring board 2 for logic verification is obtained.
  • a plurality of FPGAs 1 are mounted on the wiring board 2 for logic verification described above, and logic debugging of the FPGA 1 is performed.
  • a simulation is performed on the manufactured FPGA 1 using a computer to check the operation order of each instruction and the contents of the register, etc. Feedback in the layout and wiring process 204 etc. in 201 and FPGA (process 207)
  • a photomask for manufacturing a gate array is manufactured based on data of a logic circuit obtained through a logic debugging process 207 using an FPGA.
  • a pattern for forming a connection hole such that a part of the first-layer wiring is exposed in the above-described second-layer eyebrow insulating film is formed (Step 208).
  • the gate array is not required.
  • the manufacturing process of the array has become very simple, and the manufacturing period can be greatly reduced.
  • the gate array 3 is obtained through another manufacturing process such as a manufacturing process using the photomask and a wiring forming process and a deposition process of an edge film (process 209). After that, the completed gate arrays 3 are mounted on the wiring board 2 for logic verification used at the time of logic debugging of the FPGA 1, and the operation of the gate array 3 is confirmed (Step 210). .
  • the wiring board 2 for logic verification of the FPGA 1 can be used as it is as a wiring board for confirming the operation of the gate array 3.
  • this includes the chip size in the manufactured gate array 3, the arrangement position of the bonding pad, the arrangement position of the logic circuit block such as the logic gate, and the arrangement position of the wiring. This is because the configuration is exactly the same as the configuration of FPGA 1.
  • FIG. 3 shows a plan view of the FPGA 1 and the gate array 3 manufactured by the method of manufacturing a semiconductor integrated circuit device according to the present embodiment.
  • the left side of FIG. 3 is FPGA 1, and the right side is gate array 3.
  • the semiconductor chips 1 a and 3 a constituting the FPGA 1 and the gate array 3 are both formed of, for example, rectangular small pieces made of a single conductive Si single crystal, and have the same size. .
  • a plurality of rectangular bonding pads 1 BP, 3 BP are regularly arranged along the outer periphery of the main surface of the semiconductor chips 1 a, 3 a.
  • the bonding pads 1 BP and 3 BP are extraction electrodes for extracting the electrodes of the semiconductor integrated circuit in the semiconductor chips 1 a and 3 a to the outside.
  • aluminum (A 1) or A 1 Si—copper (Cu) alloy for example, aluminum (A 1) or A 1 Si—copper (Cu) alloy.
  • the semiconductor chip 1 The arrangement of the bonding pads 1 BP and 3 BP of a and 3 a, that is, the positions of the signal terminals and the power supply terminals are also the same.
  • a plurality of input-output circuit region 1 b, 3 b is placed along the outer periphery of the semiconductor chip 1 a, 3 a I have.
  • an input circuit, an output circuit, or a bidirectional input / output circuit is formed in the input / output circuit regions 1b and 3b.
  • the input circuit has a function of converting a signal or the like input from the outside into a signal level suitable for the internal circuit, a function of protecting the internal circuit from noise, and the like. It has a function to convert the signal level so that the signal is transmitted to the external device without being attenuated in the wiring route on the way when the signal is transmitted to the outside.
  • a semiconductor integrated circuit having a predetermined logic function is formed in the semiconductor chip 1 a, 3 a, input-output circuit region ib, 3 b of ⁇ , ie, the internal circuit region.
  • the semiconductor chip 1 a, 3 a, the semiconductor integrated circuit of the same logical function is formed.
  • This semiconductor integrated circuit is composed of a plurality of basic cells arranged in an internal circuit area.
  • the basic cell is a minimum unit cell necessary for forming a logic circuit such as an inverter circuit, a NAND circuit, a NOR circuit, and the like, and is composed of, for example, nM0S and pM0S.
  • a plurality of the basic cells are arranged side by side in FIG. 3 to form a basic cell row.
  • the plurality of basic cell columns are arranged in the vertical direction in FIG. 3 with a wiring channel interposed between adjacent basic cell columns.
  • the arrangement state of the basic cells is not limited to this, and can be variously changed. For example, it is possible to arrange the basic cells by laying them all over the internal circuit area.
  • a circuit block such as a flip-flop circuit is formed by combining a plurality of such basic cells, and a semiconductor integrated circuit having a predetermined logic function is formed by combining a plurality of circuit blocks.
  • the arrangement positions and the sizes of the components such as the basic cells and the circuit blocks in the semiconductor chips 1a and 3a are the same.
  • the environment such as the internal temperature distribution and the power supply noise of the semiconductor chips 1a and 3a can be made equal to each other.
  • the wiring lengths between the components in the semiconductor chips 1a and 3a are completely equal, the delay time in each logical path can be made equal to each other.
  • the jigs, packaging, and aging boards used for the probing inspection and the like between the FPGA 1 and the gate array 3 can be shared, thereby simplifying the manufacturing process of the semiconductor integrated circuit device. The development period can be shortened, and the manufacturing cost can be reduced. Therefore, in the first embodiment, a semiconductor integrated circuit having exactly the same function and performance as the FPGA 1 is manufactured by the FPGA method or by the normal gate array method without using the FPGA. It is possible to manufacture with less production.
  • the FPGA 1 and the gate array 1 can be applied to predetermined electronic devices such as portable communication devices, video cameras, computers, and the like.
  • a writing method of the FPGA will be described with reference to FIGS.
  • the antifuse portion, the first-layer wiring, and the second-layer wiring are hatched to make the drawings easy to see.
  • FIG. 4 and FIG. 5 are a plan view schematically showing an antenna fuse portion before writing data to the FPGA and a cross-sectional view taken along a line VV thereof.
  • the semiconductor substrate 4 is made of, for example, a predetermined conductive Si single crystal, and has a main surface on which predetermined elements such as a transistor, a resistor, and a capacitor are formed.
  • an interlayer insulating film 5a is deposited on the upper surface of the semiconductor substrate 4. Its Sotoi insulating film 5 a is made of, for example, S i 0 2, etc., on its, that have first scrap wire 6 a is formed.
  • the first-layer wiring 6a is made of, for example, A1 or A1-Si-Cu alloy, and has an end at one end through a connection hole 7a formed in the interlayer insulating film 5a.
  • S ⁇ FET first switching element
  • the source of 8Q1 is connected in a thunderstorm manner.
  • MOS S ⁇ FET 8 Q1 for writing is an anti-fuse to which data is written It is an element for selecting a part, and is composed of, for example, pM0S formed on the semiconductor substrate 4.
  • interlayer insulating film 5b is deposited on the interlayer insulating film 5a, thereby covering the first layer wiring 6a.
  • Interlayer insulating film 5 b is made of, for example, S i 0 2, etc., on its upper surface, the second layer wiring 6 b is formed.
  • the second layer wiring 6b is made of, for example, A1 or A1-Si-Cu alloy, and is formed so as to cross the first layer wiring 6a.
  • An antifuse portion 9af is arranged at the intersection of the first layer wiring 6a and the second layer wiring 6b.
  • the antifuse 9 af is made of, for example, amorphous silicon, and is formed in a state of being sandwiched between the first layer wiring 6 a and the second layer wiring 6 b in the connection hole 7 b formed in the interlayer insulating film 5 b. Have been.
  • the first-layer wiring 6a and the second-layer wiring 6b are connected via the anti-fuse portion 9af at the connection hole 7b.
  • the antifuse portion 9af is made of, for example, amorphous silicon, the first-layer wiring 6a and the second-layer wiring 6b are not electrically connected at this stage.
  • the first layer wiring 6a is electrically connected to one end of the second waste wiring 6b through a connection hole 7c formed in the interlayer insulating film 5b, and the first layer wiring 6a is The drain of a writing MOS FET (second switching element) 8Q2 is electrically connected through a connection hole 7d formed in the interlayer insulating film 5a.
  • a writing MOS FET second switching element
  • the write MOS FET 8Q2 is a pair of the write MOS FET 8Q1n and is an element for selecting an anti-fuse portion for writing data. Consists of the formed nM0S.
  • a high electric field is applied to the anti-fuse section 9 af to cause a leakage current i to flow.
  • the potential of the gate electrode is controlled to make the write MOSFET8Q1 conductive, and the write MOS This is done by controlling the potential of the gate electrode of the MOS FET8Q2 to make the MOS FET8Q2 for writing conductive.
  • 6 and 7 schematically show the anti-fuse section 9af after data writing. It is a top view and the sectional view of the VII-VII line.
  • a conductive portion 9 af 1 made of an alloy of the anti-fuse material and the wiring material is formed between the first layer wiring 6 a and the second layer wiring 6 b in the connection hole 7 b. Is done. As a result, the first layer wiring 6a and the second layer wiring 6b are electrically connected. At this time, the leakage current i increases from several nA to several mA.
  • writing of FPG A data requires MOS ⁇ FET 8Q1 and 8Q2 for writing.
  • the potentials of the gate electrodes of the MOSFETs 8Q1 and 8Q2 are controlled so as to be cut off after the writing process.
  • the data for forming the logic circuit of the FPGA (including the data of the anti-fuse portion) is replaced with the data for forming the logic circuit of the gate array (including the data of the anti-fuse portion).
  • the method of conversion to (not including data overnight) will be specifically described with reference to FIGS.
  • FIGS. 8 to 14 the X-axis and the Y-axis are shown for easy understanding of the relative positional relationship between different drawings, and the antifuse section and the first The layer wiring and the second layer wiring are hatched.
  • FIGS. 8 and 9 are a plan view of a main part of an anti-fuse type FPGA having the same two-layer wiring layer structure as described above, and a cross-sectional view taken along line IX-IX.
  • the leftmost first-layer wiring 6a is electrically connected to the second-layer wiring 6b1 through a connection hole 7c formed in the interlayer insulating film 5b. .
  • the first scrap wiring 6a arranged in the center is connected to the second layer wiring 6b2 via the antifuse portion 9af in the connection hole 7b1 formed in the interlayer insulating film 5. It is connected. However, the first layer wiring 6a and the second layer wiring 6b2 are not electrically connected.
  • the first layer wiring 6a disposed on the rightmost side is connected to the second wiring via the anti-fuse portions 9af in the connection holes 7b2 and 7b3 formed in the interlayer insulating film 5b. It is connected to layer wiring 6b3 and 6b4.
  • the anti-fuse portion 9af is made of, for example, amorphous silicon as described above, so that almost no current normally flows.However, when a high voltage or the like is applied, the anti-fuse portion 9af is alloyed with the wiring material to reduce the resistance. The current can flow.
  • connection holes 7 b 1, 7 b 2, 7 b 3, 7 c are simultaneously drilled in the above-mentioned step 106 A 1 of FIG. That is, the normal connection hole 7c and the connection holes 7b1, 7b2, 7b3 where the anti-fuse portions 9af are formed are simultaneously patterned with the same photomask. This makes it possible to suppress an increase in the number of manufacturing steps of the semiconductor integrated circuit device.
  • FIG. 10 shows a schematic diagram of the pattern data thus obtained.
  • connection holes 7c The pattern of the connection holes 7c is arranged such that the coordinates (X3, y1) become the center mark. Also, the patterns of the connection holes 7 b 1, 7 b 2, 7 b 3 in which the anti-fuse portions 9 af are arranged are represented by coordinates (X 2, y 1), ( ⁇ l, y 2) and (xl, y 1) is arranged to be the center coordinates.
  • the pattern data shown in FIG. 10 is superimposed on the write rate information to the antifuse section 9af in the evening.
  • a schematic diagram of the pattern data obtained by this is shown in FIG. Note that the write layout information W 1 and W 2 are indicated by X marks in order to make the surface easier to see.
  • the write rate information W1 and W2 are places where a conductive portion is formed in the antifuse section 9af when writing a desired logic into the FPGA (programming), and is determined by a logic desired by the user.
  • the anti-fuse section 9af to which the write rate information W1 and W2 is applied is applied with a high voltage or the like in the above-described writing step 206A of the FPGA in FIG.
  • the first-layer wiring 6a and the second-layer wiring 6b are electrically connected to each other in the writing portion, thereby forming a predetermined logic circuit.
  • the anti-fuse section 9af without the write rate information W1, W2 is not applied with a high pressure or the like, and remains in a non-conductive state.
  • the anti-hull is performed based on the pattern data of FIG. -No. Remove the pattern data of the connection hole where the anti-fuse section 9 af without the turn data and write layout information W 1 and W 2 is arranged.
  • Figure 12 shows the pattern data obtained in this way.
  • the pattern data includes the pattern data of the normal connection holes 7c existing before the writing process and the pattern data of the connection holes 7b1, 7b2 in which the pattern of the anti-fuse section with the write layout information is arranged. And are left.
  • a photomask used in the step 106B1 of forming an interlayer insulating film in the manufacturing process of the gate array of FIG. Produces FM 5.
  • FIGS. 13 and 14 show a plan view of a main part of a gate array manufactured using the photomask thus obtained and a cross-sectional view taken along the line XIV-XIV thereof.
  • the above antifuse portion is not formed in FIGS. 13 and 14, the same connection relationship as that of FIG. 11 used in manufacturing the FPGA is obtained in FIGS. 13 and 14.
  • FIGS. 15 to 22 hatching is applied to the anti-fuse portion, the first layer wiring, and the second layer wiring to make the drawings easy to see.
  • the X-axis and Y-axis are shown to make it easier to understand the relative positional relationship between different drawings.
  • FIG. 15 shows a plan layout diagram of internal cells in the FPGA before writing.
  • MOS FETs 10Q1 and 10Q2 are elements that make up a logic gate.
  • the MOS FET 10Q1 is made of, for example, a pMOS
  • the MOS FET 10Q2 is made of, for example, an nMOS.
  • the first-layer wiring 6a is electrically connected to the MOS gates 10Q1 and 10Q2 for configuring the logic gate through the connection hole 7e.
  • the first waste wiring 6a1 is a wiring for supplying a high potential power supply voltage
  • the first layer wiring 6a2 is a wiring for supplying a power supply voltage having a GND potential.
  • the MOS-FETs 10Q1 and 10Q2 are electrically connected to the first layer wirings 6a1 and 6a2 for the power supply depending on the conduction state of the antifuse section.
  • the writing MOS FETs 8Q1 and 8Q2 are elements for writing data to the antifuse section as described above, and at least one is electrically connected to one wiring.
  • FIG. 16 shows a cross-sectional view of the MOS FET 10Q2 for the logic gate configuration of FIG.
  • the MOS FET 10Q2 is formed on the p-well pw of the semiconductor substrate 4 and has semiconductor regions 10a, 10a, a gate insulating film 10b, and a gate electrode 10c. ing.
  • the field insulating film 11 is an element isolation portion, for example, s i
  • the p-well pw contains, for example, boron as a p-type impurity.
  • the semiconductor region 10a is a region for forming source and drain regions and contains, for example, n-type impurity phosphorus or As.
  • the semiconductor region 10a is electrically connected to the first layer wiring 6a through a connection hole 7e formed in the interlayer insulating film 5a.
  • Gate one gate insulating film 1 0 b is made of, for example, S i 0 2.
  • the gate electrode 10c is formed, for example, by depositing a silicide film such as tungsten silicide on low-resistance polysilicon.
  • a cap insulating film 12 is deposited on the upper surface of the gate electrode 10c, and side walls 13 are formed on the side surfaces.
  • Cap insulating film 12 and the side wall 13 are both made of, for example, S i 0 2.
  • the second-layer wiring 6b is covered with a surface protection film 5c.
  • the surface protective layer 5 c for example S i 0 2 or S i 0 2 silicon nitride film on the ing been Uzutaka ⁇ .
  • FIG. 17 shows a schematic diagram in which write layout information is added to FIG. Note-Write layout information is indicated by an X to make the drawing easier to read.
  • a conductive portion is formed in the antifuse portion 9 af marked with an X mark. That is, in the places marked with X, the first layer wiring 6a and the second layer wiring Line 6b is electrically connected.
  • a two-input NAND circuit is formed by the connection state as shown in FIG.
  • the FPG A is written using this data.
  • FIG. 18 is a schematic diagram showing a case where only the data of the patterns of the connection holes 7 b and 7 c and the pattern of the anti-fuse portion 9 af are extracted.
  • FIG. 18 shows a normal connection hole 7 for connecting the first layer wiring 6a and the second iff wiring 6b (see FIG. 15 etc.). Turn and the antifuse section 9af. A turn and a pattern of a connection hole 7b in which the antifuse portion 9af is arranged are shown.
  • FIG. 19 is a schematic diagram when the write layout information is overlaid on the anti-fuse section 9 a f in FIG.
  • a conductive portion is formed in the antifuse portion 9af marked with an X mark, and the first layer wiring 6a and the second layer wiring 6b are electrically connected at that location.
  • FIG. 20 shows a schematic diagram of the pattern data thus obtained.
  • a pattern of a normal connection hole 7c for electrically connecting the first layer wiring 6a and the second layer wiring 6b, and an antifuse part in which a conductive part is formed are arranged.
  • the pattern of the connection holes 7b is arranged.
  • a photomask pattern used in the connection hole forming step 208 in FIG. 2 is formed.
  • FIG. 21 is a plan view of a main part of a gate array manufactured using such a photomask. Although the above-described anti-fuse portion is not formed in 3 ⁇ 421, the same connection relationship as that of FIG. 17 used in manufacturing the FPGA is obtained in FIG. 21 as well. That is, a two-input NAND circuit having exactly the same logical function and the same performance as that of the FPGA can be formed in the gate array 3.
  • the gate array 3 having exactly the same logical function and performance as the FPGA 1 can be manufactured.
  • shifting from the manufacturing process of the FFGA 1 to the manufacturing process of the gate array 3 there is no need to perform the arrangement E-line process or the timing simulation process again. That is, it is possible to reduce the arrangement and wiring process and the timing simulation process in the manufacturing process of the gate array 3.
  • the gate array 3 having the same logical function and performance as the FPGA 1 can be manufactured.
  • the wiring board used for logic verification used can be used as it is as a wiring board for confirming the logical operation of the gate array 3, and a wiring board for logic verification can be designed again for the manufacture of the gate array 3. There is no need to manufacture. That is, it is possible to reduce the design and manufacturing steps of the wiring board for logic verification in the manufacturing process of the gate 3.
  • the gate array 3 having exactly the same logical function and performance as the FPGA 1 can be manufactured. Need not be performed. That is, it is possible to reduce the logic debugging step in the manufacturing process of the gate array 3.
  • the gate array 3 having the same logical function and performance as the FPGA 1 can be manufactured.
  • the substrate for the probing jig paging test used in the above can be used as it is in the manufacturing process of the gate array 3, and the probing jig and the substrate for the aging test are renewed for the production of the gate array 3.
  • a set of photomasks used from the formation of the element layer to the end of the wafer process are manufactured.
  • the FPGA manufacturing process The photomasks FM1, FM2, and FM4 to be used may be shared, and only the photomask FM5 for transferring the connection hole pattern may be created. That is, the number of photomask manufacturing steps can be greatly reduced, and the number of photomasks can be significantly reduced.
  • the write MOS FETs 8Q1 and 8Q2 also remain electrically connected to the semiconductor integrated circuit.
  • the diffusion capacitance of the write MOS FETs 8Q1 and 8Q2 is added as an extra load on each logic gate, and the delay time is longer than that of a normal gate array, and the performance is reduced. Can be the cause.
  • the second embodiment has a structure in which, for example, the write MOS FET is removed from the logic circuit of the gate array. This is shown in ⁇ 22.
  • connection hole 7c for electrically connecting the first-layer wiring 6a and the second-layer wiring 6b, the second-layer wiring 6b and the MOS 'FETs 8Q1,8Q
  • the connection hole 7c provided only for connecting 2 and was removed.
  • the second-layer wiring 6b and the first-layer wiring 6a are also electrically connected.
  • the connection hole 7c provided for the connection is left as it is. This makes it possible to cut off a part of the MOSS / FET8Q 1.8Q2 for writing from the logic circuit that composes the gate array, thereby preventing the diffusion capacitance from attaching to the logic circuit. ing.
  • the load associated with the logic circuit can be reduced, and the delay time in the logic circuit is reduced.
  • the length can be shortened, and the performance of the gate array 3 can be improved.
  • an antifuse portion may be provided between the semiconductor region of the semiconductor substrate and the first layer wiring, between the second layer wiring and the fourth layer ffi line, or between the third layer wiring and the fourth layer. It may be provided between wirings.
  • an anti-fuse portion is used as a program element.
  • an SRAM element is used as a program element. It may be used or a fuse may be used. When this fuse is used, when data is converted from the FPGA to the gate array, the data must be converted so that the fuse is cut at a portion corresponding to the position where the fuse is cut in the wiring of the gate array.
  • connection hole for narrowing the first layer wiring and the second layer wiring in order to separate the write MOS FET from the logic circuit, a method of eliminating a part of the connection hole for narrowing the first layer wiring and the second layer wiring is described.
  • the present invention is not limited to this, and various changes can be made.For example, the connection hole for connecting the first-layer wiring to the writing MOS FET is eliminated, and the wiring layout shape and the like are eliminated. You may change it.
  • the holes in the inter-dust insulating film covering the first-layer wiring are provided.
  • the case where the gate array is manufactured from the opening step has been described.
  • the present invention is not limited to this.
  • the write portion (conductive portion) in the FPGA is known in advance, the manufacture of the gate array from the element formation layer is performed. If it is found that a modification is found by logic debugging using the FPGA, the FPGA is modified, and the logic circuit data of the modified FPGA is used to cover the first layer wiring.
  • the gate array may be re-manufactured from the step of drilling the connection holes in the insulating film.
  • the case where the basic cells are arranged on the semiconductor chip has been described. However, the present invention is not limited to this, and various changes can be made.
  • the present invention is not limited to this.
  • a macro cell for logic such as a microprocessor and a macro cell for memory such as a RAM or a ROM may be used.
  • the present invention can be applied to a technique for manufacturing a semiconductor integrated circuit device having a large macro cell in the same semiconductor chip.
  • the method for manufacturing a semiconductor integrated circuit device and the semiconductor integrated circuit device according to the present invention can be used to manufacture a semiconductor integrated circuit device incorporated in a terminal device such as a mobile communication device, a video camera or a computer. It is suitable for use in a method or a semiconductor integrated circuit device.

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Abstract

Lorsqu'un circuit prédiffusé ayant la même fonction logique que celle d'un circuit FPGA du type à antifusibles est fabriqué au moyen du circuit FPGA, des éléments et des conducteurs communs sont formés sur un substrat de semiconducteur commun au circuit FPGA et au circuit prédiffusé, au moyen d'un masque photographique commun FM1, FM2 et FM4 dans les procédés précédant et suivant les procédés 106A1-106A3 de formation des antifusibles du circuit FPGA. Dans lesdits procédés de formation des antifusibles du circuit FPGA et pour réaliser les trous de connexion du circuit prédiffusé correspondant aux antifusibles, un masque photographique (FM5) inhérant au circuit prédiffusé est réalisé au moyen de données de motifs qui sont obtenues par conversion des informations écrites dans les antifusibles en informations concernant les trous de connexion du circuit prédiffusé.
PCT/JP1996/002408 1996-08-28 1996-08-28 Procede de production d'un circuit integre a semiconducteur, et circuit integre a semiconducteur WO1998009327A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/002408 WO1998009327A1 (fr) 1996-08-28 1996-08-28 Procede de production d'un circuit integre a semiconducteur, et circuit integre a semiconducteur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/002408 WO1998009327A1 (fr) 1996-08-28 1996-08-28 Procede de production d'un circuit integre a semiconducteur, et circuit integre a semiconducteur

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WO1998009327A1 true WO1998009327A1 (fr) 1998-03-05

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638369B2 (en) 2005-02-24 2009-12-29 Nec Electronics Corporation Semiconductor chip and method of fabricating the same
JP2017195368A (ja) * 2012-02-09 2017-10-26 株式会社半導体エネルギー研究所 半導体装置

Citations (2)

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Publication number Priority date Publication date Assignee Title
JPH05114654A (ja) * 1991-10-23 1993-05-07 Fujitsu Ltd 半導体装置
JPH05267457A (ja) * 1992-03-24 1993-10-15 Kawasaki Steel Corp 半導体集積回路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05114654A (ja) * 1991-10-23 1993-05-07 Fujitsu Ltd 半導体装置
JPH05267457A (ja) * 1992-03-24 1993-10-15 Kawasaki Steel Corp 半導体集積回路

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638369B2 (en) 2005-02-24 2009-12-29 Nec Electronics Corporation Semiconductor chip and method of fabricating the same
JP2017195368A (ja) * 2012-02-09 2017-10-26 株式会社半導体エネルギー研究所 半導体装置
US10600792B2 (en) 2012-02-09 2020-03-24 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device and method for manufacturing semiconductor device

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