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WO1998006139A1 - Cellule memoire non volatile - Google Patents

Cellule memoire non volatile Download PDF

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Publication number
WO1998006139A1
WO1998006139A1 PCT/DE1997/001600 DE9701600W WO9806139A1 WO 1998006139 A1 WO1998006139 A1 WO 1998006139A1 DE 9701600 W DE9701600 W DE 9701600W WO 9806139 A1 WO9806139 A1 WO 9806139A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
silicon oxide
oxide layer
gate electrode
thickness
Prior art date
Application number
PCT/DE1997/001600
Other languages
German (de)
English (en)
Inventor
Hans Reisinger
Reinhard Stengl
Hermann Wendt
Josef Willer
Volker Lehmann
Martin Franosch
Herbert Schäfer
Wolfgang Krautschneider
Franz Hofmann
Ulrike GRÜNING
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to EP97937411A priority Critical patent/EP0916161A1/fr
Priority to JP10507343A priority patent/JP2000515325A/ja
Publication of WO1998006139A1 publication Critical patent/WO1998006139A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered

Definitions

  • Non-volatile memory cell
  • Non-volatile memory cells so-called SONOS or MNOS cells, each comprising a special MOS transistor, have been proposed for the permanent storage of data (see, for example, Lai et al. IEDM Tech. Dig. 1986, pages 580 to 583).
  • the MOS transistor comprises a gate dielectric which comprises at least one silicon nitride layer below the gate electrode and a SiO 2 layer between the silicon nitride layer and the channel region. Charge carriers are stored in the silicon nitride layer to store the information.
  • the thickness of the SiO 2 layer in these non-volatile memory cells is a maximum of 2.2 nm.
  • the thickness of the silicon nitride layer in modern SONOS memory devices is usually about 10 nm.
  • a further SiO 2 layer is usually provided between the silicon nitride layer and the gate electrode. which has a thickness of 3 to 4 nm.
  • the gate electrode is wired in such a way that the charge carriers stored in the silicon nitride layer tunnel through the 2.2 nm thick SiO 2 layer in the channel region and from the channel region, charge carriers of the opposite conductivity type tunnel through the SiO 2 layer into the silicon nitride layer.
  • the memory cells described which are often referred to as SONOS cells, have a data retention time of ⁇ 10 years. This time is too short for many applications, for example for storing data in computers.
  • EEPROM cells with a floating gate as the non-volatile memory.
  • a floating gate electrode is arranged between a control gate electrode and the channel region of the MOS transistor, which is completely surrounded by dielectric material. The information is stored in the form of charge carriers on the floating gate electrode.
  • These memory cells which are also referred to as FLOTOX cells, can be electrically written and erased.
  • the control gate electrode is connected to such a potential that charge carriers flow from the channel area onto the floating gate electrode (writing) or charge carriers flow from the floating gate electrode into the channel area (erase).
  • These FLOTOX cells have data retention times greater than 150 years.
  • Radiation hardness refers to the insensitivity of the stored charge to external radiation sources and / or electromagnetic fields.
  • the invention is based on the problem of specifying a non-curse memory cell which has a data retention time of at least 150 years, which is simple in structure and can be integrated in a high packing density and which has improved radiation hardness in comparison with the FLOTOX cells having.
  • This problem is solved according to the invention by a memory cell according to claim 1. Further configurations emerge from the subclaims.
  • the non-volatile memory cell comprises a MOS transistor with source region, channel region, drain region, gate dielectric and gate electrode, which has a dielectric triple layer as the gate dielectric.
  • the dielectric triple layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer.
  • the silicon nitride layer is arranged between the two silicon oxide layers.
  • the first silicon oxide layer and the second silicon oxide layer each have a thickness of at least 3 nm.
  • the thicknesses of the first silicon oxide layer and the second silicon oxide layer in the memory cell according to the invention are chosen so that they differ by an amount in the range between 0.5 and 1 nm.
  • the smaller of the two thicknesses of the first silicon oxide layer and the second silicon oxide layer is in the range between 3 and 5 nm.
  • the thickness of the silicon nitride layer is at least 5 nm.
  • the MOS transistor has a gate electrode made of n + -doped silicon. In this memory cell, the dielectric triple layer is electrically symmetrical. Due to the different thicknesses of the first silicon oxide layer and the second silicon oxide layer, the work function differences between the channel region and the gate electrode and mainly the generally positive gate voltage applied during reading operation are taken into account.
  • the memory cell according to the invention differs from conventional SONOS cells in that the first silicon oxide layer, which is arranged between the channel region of the MOS transistor and the silicon nitride layer, has a thickness of at least 3 nm. In conventional SONOS cells, this thickness is a maximum of 2.2 nm.
  • the invention makes use of the knowledge that in conventional SONOS cells the charge is transported through the first silicon oxide layer mainly via direct tunneling and modified Fowler-Nordheim tunneling.
  • the tunnel probability for direct tunneling and modified Fowler-Nordheim tunneling and thus the current intensity for the transport of charge carriers through direct tunneling and modified Fowler-Nordheim tunneling depends mainly on the thickness of the tunnel barrier, that is, the thickness of the first silicon oxide layer, and on the electrical one Field. Since in conventional SONOS cells the first silicon oxide layer has a maximum thickness of 2.2 nm and the second silicon oxide layer is 3 to 4 nm thick, the current by direct tunneling through the first silicon oxide layer always prevails in electrical fields below 10 MV / cm. Via this direct tunnel current and modified Fowler-Nordheim tunneling, the writing as well as the deletion of the information takes place by appropriate wiring of the gate electrode.
  • the invention also makes use of the knowledge that even without connecting the gate electrode in conventional SONOS cells, a tunnel current, which is due to direct tunneling, flows through the first silicon oxide layer from the silicon nitride layer to the channel region. It was found that this direct tunnel current is decisive for the time for the data retention.
  • the invention makes use of the knowledge that the tunneling probability for direct tunneling decreases sharply with increasing thickness of the first silicon oxide layer and becomes very small with a thickness of at least 3 nm, by several (approximately 3) orders of magnitude smaller than at 2 nm.
  • first silicon oxide layer and the second silicon oxide layer are each at least 3 nm thick in the memory cell according to the invention, a layer is stored in this memory cell.
  • Manure carrier transport from the silicon nitride layer to the gate electrode or to the channel area largely avoided by direct tunneling. This means that the charge stored in the silicon nitride layer remains practically indefinitely.
  • the time for data retention in the memory cell according to the invention is therefore significantly longer than in conventional SONOS cells, more than 1000 years instead of 10 years.
  • the tunnel probability for direct tunneling of charge carriers through the two silicon oxide layers is very small.
  • a charge carrier transport through the first silicon oxide layer or second silicon oxide layer takes place during writing and reading only through Fowler-Nordheim tunnels.
  • the current intensity of the charge carrier transport through Fowler-Nordheim tunnels only depends on the strength of the applied electric field. It is not explicitly dependent on the thickness of the tunnel barrier, that is to say the thickness of the first silicon oxide layer or second silicon oxide layer.
  • the Fowler-Nordheim tunneling of electrons dominates charge carrier transport regardless of the polarity of the applied field. This means that both when a positive voltage is applied and when a negative voltage is applied to the gate electrode, Fowler-Nordheim tunneling of electrons into the silicon nitride layer. If a positive voltage is present at the gate electrode, electrons tunnel from the channel region through the first silicon oxide layer into the silicon nitride layer. If, however, there is a negative voltage at the gate electrode, electrons tunnel through the second silicon oxide layer into the silicon nitride layer through Fowler-Nordheim tunnels from the gate electrode.
  • a gate voltage of typically + 12 V is applied to write information into this memory cell.
  • a gate voltage of typically + 3 V is applied to read the information.
  • the first silicon oxide layer has a smaller thickness than the second silicon oxide layer. If the memory cell is to be operated with a negative read voltage, the second silicon oxide layer has a smaller thickness than the first silicon oxide layer.
  • the memory cell is integrated in memory cell arrangements which have a plurality of identical memory cells in the form of a matrix.
  • the MOS transistor in the memory cell can be designed both as a planar and as a vertical MOS transistor.
  • Figure 1 shows a memory cell with a planar MOS transistor.
  • Figure 2 shows a memory cell with a vertical MOS transistor.
  • a source region 2 and a drain region 3, which are n-doped, for example, are provided in a substrate 1, which comprises monocrystalline silicon at least in the region of a memory cell.
  • a channel region 4 is arranged between the source region 2 and the drain region 3.
  • Source region 2, channel region 4 and drain region 3 are arranged next to one another on the surface of the substrate 1.
  • a dielectric triple layer 5 is arranged above the channel region 4 and comprises a first SiO 2 layer 51, an Si3N 4 layer 52 and a second SiO 2 layer 53.
  • the first SiO 2 layer 51 is arranged on the surface of the channel region 4 and has a thickness of 3 to 6 nm, preferably 4 nm.
  • the Si3N4 layer 52 is arranged on the surface of the first SiO 2 layer 51.
  • the second SiO 2 layer 53 is arranged on the surface of the Si 3 4 layer 52, whose thickness is 0.5 to 1 nm greater than the thickness of the first SiO 2 layer 51, that is to say in the range between 3.5 and 6 nm, preferably 4.5 to 5 nm.
  • a gate electrode 6 made of, for example, n-doped polysilicon is arranged on the surface of the dielectric triple layer 5.
  • the gate electrode 6 has a thickness of, for example, 200 nm and a dopant concentration of, for example, 10 21 cm "3 .
  • a semiconductor layer structure 11 made of, for example, monocrystalline silicon comprises a source region 12, a channel region 14 and a drain region 13 in vertical succession (see FIG. 2).
  • the source region 12 and the drain region 13 are, for example, n-doped with a dopant concentration of 10 20 cm "3.
  • the channel region 14 is, for example, p-doped with a dopant concentration of 10 17 cm -3
  • Source region 12, drain region 13 and channel region 14 have a common flank 110, which preferably extends perpendicularly or slightly inclined to the surface of the semiconductor layer structure 1.
  • the flank 110 can be both the flank of a trench or a step in a substrate and the flank of a raised structure, for example a mesa structure.
  • a dielectric triple structure 15 is arranged on the flank 110 and comprises a first SiO 2 layer 151, an Si3N 4 layer 152 and a second SiO 2 layer 153.
  • the surface of the second SiO 2 layer 153 is covered with a gate electrode 16.
  • the gate electrode 16 is formed, for example, in the form of a spacer made of n-doped polysilicon or metal, for example aluminum.
  • Layer 153 has a thickness of, for example, 3 to 5 nm, preferably 4 nm.
  • the Si 3 N 4 layer 152 has a thickness of at least 5 nm, preferably 8 nm.
  • the first SiO 2 layer 151 is 0.5 to 1 nm thicker than the second SiO 2 layer 153, that is to say it has a thickness between 3.5 and 6 nm. It preferably has a thickness of 4.5 nm.
  • the thicknesses of the first SiO 2 layer 151, the Si 3 N 4 layer 152 and the second SiO 2 layer 153 are each measured perpendicular to the flank 110.

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une cellule mémoire non volatile, inscriptible une seule fois, comprenant un transistor MOS qui présente, en tant que diélectrique de la grille, une triple couche diélectrique constituée d'une première couche d'oxyde de silicium (51), d'une couche de nitrure de silicium (52) et d'une deuxième couche d'oxyde de silicium (53). La première couche d'oxyde de silicium (51) et la deuxième couche d'oxyde de silicium (53) présentent chacune une épaisseur d'au moins 3 nm. Cette cellule mémoire est non effaçable et présente une durée de conservation des données supérieure à 1000 ans.
PCT/DE1997/001600 1996-08-01 1997-07-29 Cellule memoire non volatile WO1998006139A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP97937411A EP0916161A1 (fr) 1996-08-01 1997-07-29 Cellule memoire non volatile
JP10507343A JP2000515325A (ja) 1996-08-01 1997-07-29 不揮発性メモリセル装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19631147A DE19631147C2 (de) 1996-08-01 1996-08-01 Nichtflüchtige Speicherzelle
DE19631147.0 1996-08-01

Publications (1)

Publication Number Publication Date
WO1998006139A1 true WO1998006139A1 (fr) 1998-02-12

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1997/001600 WO1998006139A1 (fr) 1996-08-01 1997-07-29 Cellule memoire non volatile

Country Status (6)

Country Link
EP (1) EP0916161A1 (fr)
JP (1) JP2000515325A (fr)
KR (1) KR20000035785A (fr)
DE (1) DE19631147C2 (fr)
TW (1) TW335555B (fr)
WO (1) WO1998006139A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003472A3 (fr) * 2001-06-26 2003-10-30 Infineon Technologies Ag Ensemble transistor, procede pour l'exploitation d'un ensemble transistor comme memoire de donnees et procede pour la production d'un ensemble transistor
WO2004001856A1 (fr) * 2002-06-21 2003-12-31 Micron Technology, Inc. Memoire morte non volatile verticale
DE10352641A1 (de) * 2003-11-11 2005-02-17 Infineon Technologies Ag Charge-Trapping-Speicherzelle und Herstellungsverfahren
US7265413B2 (en) 2002-09-05 2007-09-04 Infineon Technologies Ag Semiconductor memory with vertical memory transistors and method for fabricating it

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10110150A1 (de) * 2001-03-02 2002-09-19 Infineon Technologies Ag Verfahren zum Herstellen von metallischen Bitleitungen für Speicherzellenarrays, Verfahren zum Herstellen von Speicherzellenarrays und Speicherzellenarray
KR100426481B1 (ko) * 2001-06-26 2004-04-13 주식회사 하이닉스반도체 코드 저장 메모리 셀 제조 방법
FR2861123B1 (fr) * 2003-10-15 2006-03-03 Somfy Procede d'initialisation et de commande d'une installation comprenant des ecrans sensibles au vent.
US7790516B2 (en) 2006-07-10 2010-09-07 Qimonda Ag Method of manufacturing at least one semiconductor component and memory cells

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) * 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer
US5436481A (en) * 1993-01-21 1995-07-25 Nippon Steel Corporation MOS-type semiconductor device and method of making the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408115A (en) * 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5311049A (en) * 1991-10-17 1994-05-10 Rohm Co., Ltd. Non-volatile semiconductor memory with outer drain diffusion layer
US5436481A (en) * 1993-01-21 1995-07-25 Nippon Steel Corporation MOS-type semiconductor device and method of making the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T.Y. CHAN ET AL.: "A true single-transistor oxide-nitride-oxide EEPROM device", IEEE ELECTRON DEVICE LETTERS., vol. EDL-8, no. 3, 3 March 1987 (1987-03-03), NEW YORK US, pages 93 - 95, XP002047234 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003003472A3 (fr) * 2001-06-26 2003-10-30 Infineon Technologies Ag Ensemble transistor, procede pour l'exploitation d'un ensemble transistor comme memoire de donnees et procede pour la production d'un ensemble transistor
US7154138B2 (en) 2001-06-26 2006-12-26 Infineon Technologies Ag Transistor-arrangement, method for operating a transistor arrangement as a data storage element and method for producing a transistor-arrangement
WO2004001856A1 (fr) * 2002-06-21 2003-12-31 Micron Technology, Inc. Memoire morte non volatile verticale
US6842370B2 (en) 2002-06-21 2005-01-11 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
US6853587B2 (en) 2002-06-21 2005-02-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
US7265413B2 (en) 2002-09-05 2007-09-04 Infineon Technologies Ag Semiconductor memory with vertical memory transistors and method for fabricating it
DE10241172B4 (de) * 2002-09-05 2008-01-10 Qimonda Ag Halbleiterspeicher mit vertikalen Speichertransistoren und Verfahren zu dessen Herstellung
DE10352641A1 (de) * 2003-11-11 2005-02-17 Infineon Technologies Ag Charge-Trapping-Speicherzelle und Herstellungsverfahren

Also Published As

Publication number Publication date
EP0916161A1 (fr) 1999-05-19
DE19631147C2 (de) 2001-08-09
KR20000035785A (ko) 2000-06-26
TW335555B (en) 1998-07-01
DE19631147A1 (de) 1998-02-05
JP2000515325A (ja) 2000-11-14

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