WO1997039477A1

WO1997039477A1 - P-type silicon carbide formation by ion implantation and p-type silicon carbide

Info

Publication number: WO1997039477A1
Application number: PCT/US1997/006116
Authority: WO
Inventors: Jian H. Zhao
Original assignee: Rutgers, The State University
Priority date: 1996-04-16
Filing date: 1997-04-14
Publication date: 1997-10-23
Also published as: AU2458997A

Abstract

Ion implantation of SiC using approximately equal amounts of C and a p-type acceptor such as A1 or B creates p-doped SiC single crystal semiconductors with high uniformity, reproducibility, and crystal and electrical properties. Moreover, excellent ohmic contacts can be formed on the p-doped SiC layer using this method. This implantation approach makes it possible to create and fabricate both integrated circuit and discrete SiC devices.

Description

477 PC17US97/06116

DESCRIPTION

P-TYPE SILICON CARBIDE FORMATION BY ION IMPLANTATION AND P-TYPE SILICON CARBIDE

TECHNICAL FIELD

The present invention relates to novel and improved methods of forming novel p-type silicon carbide with high uniformity, reproducibility, and crystal and electrical quality. BACKGROUND ART

Semiconductors are materials generally defined as having electrical conductivities somewhere between the high conductivity characteristics of metals and the low conductivity characteristics of insulators. Since the invention of the transistor, the development of electrical devices based on semiconductors has revolutionized the electronics industry.

At the present time, silicon remains the most common semiconductor material for doping and device manufacture. However, recently there has been much interest generated in other semiconductor materials including gallium arsenide (GaAs) and indium phosphide (InP). Many techniques exist for producing pure crystals of these basic elements and compounds and for fabricating them into devices and circuits.

Another material which has generated much interest, but for which limited success in producing practical crystals and devices has been achieved, is silicon carbide (SiC). As a semiconductor material, silicon carbide offers a number of advantageous characteristics which have long been recognized, one of which is its high thermal stability.

Although silicon vaporizes at a temperature of approximately

1400°C , silicon carbide remains stable at temperatures approaching 2800°C. Fundamentally, this means that silicon carbide can exist as a solid at extremely high temperatures at which silicon and silicon based electronic devices would not only be useless, but would also be completely destroyed.

Another advantage is that silicon carbide has a relatively wide band gap, (i.e. the energy difference between its valence and conduction bands), of approximately 2.2 electron volts (eV) (beta) or 3.0 (eV) (6H - alpha). This is a rather large gap in comparison to that of silicon (1.1 eV) and means that electrons will have less tendency to move from the valence band to the conduction band solely on the basis of thermal excitation. In practical terms, this allows for silicon carbide-based devices to operate at higher temperatures than the equivalent silicon-based devices.

Additionally, silicon carbide has a high thermal conductivity, a low dielectric constant, a high breakdown electric field, and a high saturated electron drift velocity. These characteristics mean that, at high electric field levels, devices made from silicon carbide can perform at higher speeds than devices made from any of die other conventional semiconductor materials. Because of these inherent characteristics, silicon carbide has been a principal and perennial candidate material for applications having high temperature, high power, and high speed requirements.

In order to produce a useful electronic device from a semiconductor such as silicon carbide, however, the semiconductor must have some capacity to allow the flow of conducting species from place to place. The two most common species for carrying charge are electrons and holes. Electrons are one of the fundamental subatomic particles carrying negative charge, while "holes" represent an energy level position within an atom where an electron could be placed, but for some reason is temporarily or permanently absent. Because holes are left behind when electrons move, holes can also be thought of as moving from place to place and as carrying a positive charge. In silicon carbide, both the silicon atoms and the carbon atoms have the same number of valence electrons. Other than crystal lattice defects and ordinary thermal population of different energy levels by the electrons, there is no reason for electrons or corresponding holes to move from atom to atom, and thereby carry a flow of current. If, however, an appropriate number of slightly different atoms can be added to the silicon carbide crystal, for example aluminum (Al), boron (B), phosphorous (P), or nitrogen (N), a more conductive material will result.

The greater conductivity results from one of two phenomena: Using nitrogen, for example, which has five valence electrons, the presence of nitrogen atoms in a silicon carbide crystal provides a number of extra electrons which would not be present in a purer silicon carbide crystal. These extra electrons can be encouraged to move from the mtrogen atoms to empty electron positions in the silicon or carbon atoms, resulting in a flow of current. Conversely, using aluminum, which has three valence electrons, the presence of the aluminum atoms in the silicon carbide crystal provides available electron positions into which other electrons can move from the silicon or carbon atoms, and thereby carry current by the movement of "holes" . In terms familiar to the semiconductor industry, such added atoms are referred to as "dopants," and die process of introducing them into semiconductor materials is known as "doping. " By doping a semiconductor material such as silicon carbide wim either atoms with more valence electrons such as nitrogen (n-type doping) or fewer valence electrons, such as aluminum (p-type doping), a semiconductor material can result which has certain specific electrical characteristics, and tiirough which current can be made to flow under particular controlled conditions. Such materials can be fabricated into devices of many types, common examples of which are diodes, capacitors, junction transistors, and field effect transistors, all of which in turn can be built into circuits and more complicated devices.

In order to produce useful semiconductor electronic devices, at least three basic requirements must be met: first, an appropriate semiconductor material must by available, often in the form of a single crystal or a monocrystalline thin film; second, the ability must exist to dope the semiconductor material in the desired manner; and third, proper techniques must be developed for forming devices from the doped materials. Accordingly, much interest, research, publication activity, and indeed patent literature, has been directed at producing silicon carbide, doping it, and manufacturing devices from it. In spite of this high level of attention, commercial devices formed from silicon carbide have to date failed to move beyond the literature or the research lab into the commercial marketplace. Two main categories of failure have existed: a lack of any reproducible and precise methods for forming the necessary single crystals of silicon carbide essential for device manufacture; and the lack of successful doping techniques for creating doped monocrystalline silicon carbide having high enough purities, low enough defect levels, and sufficient electrical activation of the dopant species to form any commercially useful devices.

Recently, however, techniques have been developed for successfully growing monocrystalline silicon carbide of high purity and low defect level in each of the two most common forms of silicon carbide, the cubic or beta structure and the hexagonal 6H alpha structure. Such technology is described, for example, in "Beta-SiC Thin Films and Semiconductor Devices Fabricated Thereon," U.S. Pat. No. 4,912,063, and Homoepitaxial Growth of Alpha-SiC Thin Films and Semiconductor Devices Fabricated Thereon," U.S.Pat. No. 4,912,064, which are herein incorporated by reference.

From the doping standpoint, a number of potential methods exist for introducing an appropriate dopant into a semiconductor substrate, such as diffusion and ion implantation. Unlike silicon technology, thermal diffusion cannot be used in doping silicon carbide due to a very low diffusion coefficient of the impurities. This leaves ion implantation as the only viable selective doping technique for silicon carbide device production. In ion implantation, ions of the dopant atoms are formed by any appropriate method, for example by application of a strong enough field to strip one or more electrons from each dopant atom. The ions are then accelerated, typically through a mass spectrometer to further separate and accelerate the desired dopant atoms, and finally directed into a target material (usually a single crystal or monocrystalline thin film) at energies typically between about 50 and about 300 kilo electron volts (KeV).

On an atomic level, this results in severe collisions between the accelerated ions and the atoms of the target crystal. This initially can result in two problems. First, the dopant ions may not be in positions at which electrons and holes can be transferred, i.e. they are not yet "electrically activated." Secondly, a great deal of damage to the target crystal results. In particular, atoms in the crystal lattice are dislodged from their proper positions to a greater or lesser extent. As is known to those familiar with semiconductor crystallography, such damaged crystals often do not have the electrical properties required for useful semiconductor devices. Accordingly, various attempts and techniques have been developed for dealing with the damage done during implantation.

A first technique is to heat or anneal the doped substrate material following implantation. This heating step, when followed by an appropriate rate of cooling, should theoretically encourage the atoms in the crystal lattice, most of which are atoms of the semiconductor, to recrystallize in an orderly fashion. This process repairs the damage to the semiconductor crystal lattice and allows the dopant atoms to position themselves for electrical activation. Other researchers have attempted to raise the temperature of the target during implantation, an example of which is U.S. Pat. No. 3,293,084 to McCaldin (Dec. 20, 1966), which discusses ion implantation of silicon, germanium, silicon, and germanium alloys with sodium, potassium, rubidium, or cesium as the doping atom. In 1966, however, analytical tools such as transmission electron microscopy (TEM) and deep level transient spectroscopy (DLTS) were unavailable and the residual defects formed under these conditions remained undiscovered.

Accordingly, the more recent development of these analytical tools has demonstrated that ion implantation in silicon which is conducted at high temperatures results in lattice defects. As presentiy understood, when silicon is ion implanted at high temperatures, sufficient energy is imparted to the lattice by the incoming ions to cause individual point defects to arrange themselves in a lower energy configuration. These configurations include planar (stacking faults) and, slightly less often, line (disclosure or loops) defects. These defects are, of course, detrimental to the operation of any resulting device formed from that material.

As a result, in recent years, emphasis has shifted to ion implantation which is conducted when the target is at a rather low temperature, specifically temperatures on the order of the boiling point of liquid nitrogen (77° K., - 196° C). Under such circumstances, the implantation bombardment of ions creates a totally amoφhous region in the target crystal, i.e. one in which no specific crystal structure is present. Annealing following low temperature implantation encourages the implanted region (i.e. the layer represented by the depth to which the bombarding ions have penetrated) to recrystallize into a layer which resembles an epitaxial growth portion, giving this technique the name "solid-phase-epitaxy. " Under these conditions, the majority of the defects formed by the initial bombardment remain at the boundary between the recrystallized layer and the layer which was too deep in the crystal to be affected by the bombardment.

To date, such low temperature implantation followed by annealing represented today's best technologies for producing doped silicon materials for electrical devices. Indeed, the quality and performance of electrical devices formed from any given semiconductor material is one of the best indications of the quality of the original material and of the doping technique used to give it its desired properties.

Accordingly, in attempting to find a suitable ion implantation technique for adding dopants to silicon carbide, researchers have attempted to reproduce those techmques found successful with silicon alone. For example, Tohi et al., U.S. Pat. Nos. 3,629,011 and 3,829,333, which is incorporated herein by reference, discuss techniques for implanting ions in silicon carbide at room or "ordinary" temperatures or at relatively low temperatures following which the bombarded silicon carbide is annealed at high temperatures (up to 1600° C). To date, however, this has proved unsuccessful in producing any doped silicon carbide crystals of sufficient quality to use in devices.

In an attempt similar to those described by Tohi, Edmond et al., which is herein incorporated by reference, found that implanting dopants into silicon carbide at liquid nitrogen temperatures indeed produced amorphous layers, but annealing resulted in polycrystalline forms of silicon carbide or defective single crystals or silicon carbide, neither of which were suitable for manufacturing electrical devices. J. A. Edmond, S. P. Withrow, H. S. Kong and R.F. Davis, Beam Solid Interactions and Phase 77 8 PC17US97/06116

Transformations, edited by H. Urz, G. L. Olson and J. M. Poate (Materials Research Society, Pittsburgh, 1986), p. 395.

Other attempts have likewise been made to implant silicon carbide at ordinary or "room" temperatures. At room temperatures (approximately 293° K. to 298° K.), no technique which produces consistent results has been developed. Some crystals tend to remain crystalline, while others become amorphous in a manner similar to that which occurs upon low temperature implantation.

The layers which remain crystalline during bombardment tend to recover properly upon annealing, but certain problems in the technique remain. At certain dosages of the dopants (dosage control being a requirement for imparting desired electrical properties to the target material), the crystal structure became amorphous. Furthermore, successful annealing has to be conducted at temperatures of approximately 1800° C. These temperatures are well above the vaporization point of the silicon substrates upon which silicon carbide was always deposited prior to the concurrent inventions discussed earlier which produce silicon carbide upon silicon carbide.

Most recently, successful n-type SiC formation by nitrogen ion implantation has been reported, for example, by M. Ghezzo et al. in IEEE Electron Device Letters Vol. 13, No. 12, pp. 639-641, December, 1992 which is herein incorporated by reference. However, there are no successful techniques in the art for producing high quality, single crystal ion implanted p-type SiC semiconductor suitable for device applications. DISCLOSURE OF THE INVENTION

It is therefore an object of the present invention to provide a method of producing p-doped regions in silicon carbide suitable for semiconductor electronic devices. It is another object of the invention to produce appropriately doped monocrystalline silicon carbide in a manner which substantially prevents permanent damage to the silicon carbide crystal while electrically activating, in an appropriate fashion, the dopant introduced. It is a further object of the invention to provide a method for producing doped monocrystalline silicon carbide by ion beam implantation.

A further aspect of the invention provides novel p-type silicon carbide having activation efficiencies of 3%, 10%, 20%, 30%, 40%, or 50% or more. Still higher activation efficiencies, desirably above about 80% and most desirably above about 90%, are achievable. A further aspect of the invention provide the p-type silicon carbide with hole mobility greater than 1, cm /V sec at room temperature, and more preferably with higher hole mobility, i.e., above about 5; above about 10, above about 20, above about 40, above about 80 and most desirably 160 cm /V sec at room temperature. Yet another aspect of the invention provides the p-type silicon carbide with hole concentration greater than IO¹⁶ /cm³ at room temperature, and more

17 preferably with higher hole concentration, above about 10 , above about IO¹⁹ , and most desirably above about 10²⁰/cm³ at room temperature. The most preferred p-doped SiC materials according to the invention combine all of the desirable attributes, and provide high hole concentration, high hole mobility and high activation efficiency as aforesaid.

One aspect of the present invention uses ion implantation to create a large amount of vacancies favorable to acceptor activation in the silicon carbide lattice before p-type acceptor ion implantation is performed. For example, carbon ion implantation will create a large amount of silicon vacancies (i.e., vacancies at sites which would be occupied by silicon) and aluminum or boron ions can be used for p-type acceptor ion implantation.

In this case, because the aluminum sitting on silicon site behaves as a p-type acceptor in silicon carbide, the large amount of silicon 77 ₁₀ PC17US97/06116

vacancies drastically enhances the acceptor concentration, therefore making it possible to form a heavily doped p-type silicon carbide for ohmic contacts.

A desired method of producing a p-doped region of silicon carbide suitable for semiconductor electronic devices, comprises the following steps: a) directing a first ion beam onto a silicon carbide substrate to create vacancies favorable to acceptor activation; b) directing a second ion beam onto said silicon carbide substrate, said second ion beam consisting of p-type acceptor atoms and having an atomic concentration per cubic centimeter in about the same range as the atomic concentration per cubic centimeter of said first ion beam, to form an implanted silicon carbide structure; and c) annealing said implanted silicon carbide structure in an inert gas or vacuum environment at about between 1000°C to 1700°C. In a preferred embodiment the first ion implantation beam is carbon and the second ion implantation beam consists of aluminum or boron. Moreover, the implanted silicon carbide structure is annealed in a high purity silicon carbide crucible or other non-contaminating compartment, filled with silicon carbide powder. In a particularly preferred process, the implanted silicon carbide structure is disposed in intimate contact with another silicon carbide structure. Thus, a silicon carbide crystal may overly the surface of the implanted silicon carbide during the annealing step. Although the present invention is not limited by any theory of operation, it is believed that the -^referred annealing conditions suppress loss of silicon from the surface of the implanted silicon carbide structure.

The ion implantation steps can be performed at temperatures ranging from between about -200° C to 1500° C, including room temperature. However, according to a further aspect of the invention, it has been found that conducting one or, most preferably, both of the ion implantation stages at elevated temperatures, desirably above about 300°C; more desirably above about 450 °C and most desirably at about 600 °C or more, results in a doped crystal with enhanced properties, including enhanced hole mobility. This indicates that the degree of damage to the crystal structure occurring during implantation is reduced by conducting the implantation at elevated temperatures. In less preferred embodiments, the ion implantation stages can be conducted at about room temperature or slightly above room temperature, such as at about 100°C to about 300°C, which provides less enhancement of the properties than implantation at higher temperatures. The annealing temperature may be between about 1000°C and about 1600°C, such as between about 1400°C and 1500°C, but more preferably the annealing temperature is between about 1550°C and 1700°C, most preferably around 1650°C.

This implantation approach makes it possible to create and fabricate both IC and discrete SiC devices, including pn diodes, BJT transistors, thyristors, MOS-gated thyristors, IGBT's, UMOS, FET's and digital, as well as analog IC chips. Potential applications for this technology include: high temperature power electronics; high power microwave communications; high temperature nonvolatile RAM; and ultrahigh power density switches. Practical devices could be made from a silicon carbide semiconductor having an activation efficiency greater than 3%, 10%, 20% , or 30% or more. BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be better understood in light of and with reference to the attached drawings. Some elements of the drawings are not drawn to scale for purpose of illustration.

Fig. 1 is a cross-sectional illustration of the first critical step of implantation of ions to create vacancies favorable to acceptor activation, in this case C, into either n or p type SiC mounted on a temperature-controlled sample holder.

Fig. 2 shows the second step of co-implantation of p-type acceptor atoms, in this case Al or B, having a similar atomic concentration per cubic centimeter to that of C. The Al or B ions are implanted into the same region which was implanted by C and may be performed at similar or different temperatures. The annealing temperature and time depend on the dose and depth and can be from 1,000° C to over 1600° C and last from a few seconds to a few hours. Figure 3(a) shows the typical current-voltage relations for C and Al co-implanted 6H-SiC and Al implanted 6H-SiC measured using the transmission line model (TLM) structure shown in Fig.3(b) wherein ohmic contacts are formed on the implanted and annealed surface with various spacings between the metal contacts. Figure 4 shows the resistance between each pair of the ohmic contacts plotted as a function of the spacing between the ohmic contacts for 6H-SiC implanted by Al only at 600°C. The sheet resistance and resistivity of the implanted SiC are determined by the intercept (8.4 k-ohm in this illustration) and the slope (615 ohm/cm in this illustration). Figure 5 shows the resistance between each pair of the ohmic contacts plotted as a function of the spacing between the ohmic contacts for 6H-SiC implanted by C then Al at room temperature. The sheet resistance and resistivity of the implanted SiC are determined by the intercept (0.3 k- ohm in this illustration) and the slope (100 ohm/cm in this illustration). Figure 6 is a diagrammatic sectional view depicting an annealing chamber and silicon carbide wafers utilized. BEST MODE OF CARRYING OUT INVENTION

The following example will further illustrate the present invention. EXAMPLE 1

A 6H-SiC sample with 10 micron epilayer of n = 1 x IO¹⁶ cm^"3 on heavily doped n-type 6H-SiC substrate (off-axis, 3.5° ±_ 0.5° off {0001} toward < 1120> , purchased from Cree Research, Inc., Durham, N.C.) was used as a starting wafer. The sample was cut into two pieces of equal size. One of them was used as a control sample, i.e., implanted by Al only, and is referred to here as No. 5. The other piece, referred to here as No. 6, was first implanted with C and then Al according to the technique of the present invention using a Veeco implantor. Sample No.5 was implanted by Al-27 ions at 600° C using multiple doses and energies of 5.00 x 10¹⁵ cm^'2 at 196keV, 1.96 x 10¹⁵ cm^'2 at 118 keV, 1.00 x IO¹⁵ cm^"2 at 118keV, 1.00 x 10¹⁵ cm^"2 at 74 keV, and 4.95 x IO¹⁴ cm^"2 at 50keV. 600°C implantation was used because at lower implantation temperatures, too much damage may be generated in the substrate and the Al activation efficiency may be too low to be measured reliably.

Sample No. 6 was first implanted by C-12 at room temperature to create Si vacancies and the desired damage level so that the Al atoms, which will be implanted next, can more easily fill the Si vacancies that are created. The doses and energies for the C-12 implantation were 3.18 x IO¹⁵ cm^"2 at 122keV, 1.75 x IO¹⁵ cm^"2 at 75keV, 1.31 x 10¹⁵ cm^"2 at 43keV, and 9.21 x IO¹⁴ cm ² at 20keV.

After carbon implantation, the sample was then implanted by

Al-27 at room temperature. The Al-27 multiple doses and energies used were identical to the ones used for sample No. 5 for ease of comparison between the samples. The uniformly implanted profile had a depth of 2,200

Angstroms.

The implanted samples are then placed into a high purity graphite compartment filled with high purity SiC powder and loaded into a high temperature furnace which is pumped to IO^"3 Torr and annealed for 30 minutes at 1,500°C.

Transmission Line Model measurement (TLM) pattern as shown in Fig. 3(b) are then fabricated onto the implanted surface for electrical evaluation by using standard photolithography techniques. The metal used for the contact is Al and is deposited onto SiC by e-beam evaporation at a base pressure of 4 x 10^" Torr. The spacings used between the TLM Al patterns are SI = 5 microns, S2 = 10 microns, S3 = 15 microns, S4 = 20 microns, and S5 = 25 microns. The stripe length is 150 microns and the width is 60 microns. The Al contacts were then annealed at 950°C for 5 minutes in Ar ambient.

Fig. 3(a) shows a typical I-V characteristics between the patterns separated by 20 microns for samples No. 5 and No. 6. It shows that even for room temperature implantation, the C plus Al co-implantation technique of this invention results in a dramatically reduced resistance in comparison to just Al implantation done at 600°C .

By using the standard TLM analysis as described in the article "Obtaining the specific contact resistance from transmission line model measurements" by G.K. Reeves and H.B. Harrison published in IEEE Electron Device Letters, Vol. EDL-3, No. 5, p. 111. 1982, which is herein incorporated by reference, the sheet resistance Rg is determined to be 92.3 k-ohm/square for sample No. 5 and 15k-ohm/square for sample No. 6. The specific contact resistivity _c is found to be 4.3 x 10^" ohm-cm for sample No. 5 and 3.4 x IO^"4 ohm-cm² for sample No.6. In other words, the C co- implantation technique of this method dramatically reduces the specific contact resistivity by a factor of 252.

The resistivity of implanted material is equal to

P = R_s d = 1 q P >_P where d is the implantation depth, q is the elemental electron charge, p is hole concentration, and μ^ is hole mobility. Because R₈ is 15k-ohm/square and d = 0.22 microns, it is found that for sample No.6:

p = 0.33 ohm-cm Additionally, the activation efficiency of sample No. 6 was found to be in the range of 30% to 70%. This wide range is due to the uncertainty in the dependence of hole concentration (p) to N_a, the activated acceptor concentration which is measured in atoms/cm . This is because of the well known multiple acceptor ionization energy level in 6H-SiC. 50% activation efficiency is an estimated mean value because if N_a is equal to 2 x 10 cm^' (which is 50% of the implanted Al

17 1 concentration), the hole concentration p is 6 x 10 cm^" , assuming a single ionization level of 200 meV for Al in 6H-SiC. Then: p = 1 = 0.33 ohm-cm q ^' p ^' μ_p for μ_p equal to 30 cm²/V- sec. This mobility value is consistent with those reported values for Al- doped 6H-SiC grown by CVD as summarized in the article "SiC devices: physics and numerical simulation" by M.Ruff et al. in IEEE Trans, on

Electron Devices, Vol. 41, No. 6, p. 1040, 1994 which is herein incorporated by reference. Table 1 summarizes the results of the above example.

TABLE 1

Sample #5 ( Al only) Sample #6 (C plus Al) resistivity (ohm-cm) 2.03 0.33

sheet resistivity 92.3 15

(kilo-ohm/square) specific contact res. 4.3 x lO^"2 3.4 x 10^"

(ohm-cm²) The annealing steps desirably are perfoπned using a physical arrangement as shown in Fig. 6. The annealing apparatus includes a base 10 and lid 12, both formed from silicon carbide or graphite, which cooperatively define an enclosed chamber. Base 10 defines an inner compartment 14, a partition wall 16 surrounding inner compartment 14; an outer compartment 18 surrounding the inner compartment and an outer wall 20 surrounding outer compartment 18. The outer wall defines a shoulder 22 higher than the top of partition wall 16. Lid 12 rests on shoulder 22 and covers both compartments, but does not seal the compartments from one another. The implanted SiC wafers 24 are stacked within inner compartment 14 together with unimplanted, high-purity sacrificial SiC wafers 26 so that each implanted wafer 24 is closely covered by a surface of a sacrificial wafer 26. In Fig. 6, the wafers are stacked in alternating order, so that each implanted wafer lies between two sacrificial wafers, but this is not essential. The implanted surface of each implanted wafer should be in contact with another high-purity sacrificial SiC wafer. Desirably, the contacting surfaces are flat so that the contacting surfaces are intimately engaged with one another.

In a variant of this stacking approach, the bottom or unimplanted surface of each implanted wafer may be in contact with the implanted surface of another implanted wafer, so that the bottom surface of each implanted wafer acts as a sacrificial surface for the neighboring wafer.

The outer compartment 18 is filled with a high-purity sacrificial SiC powder 30. The powdered SiC may be replaced by other forms of SiC having relatively large surface area as, for example, whiskers or fibers of SiC, or a rough-surfaced SiC article. Preferably, the total exposed surface area of the sacrificial SiC powder and sacrificial SiC wafer surfaces exposed within the enclosed chamber is greater than the surface area of the implanted wafer surfaces. Although the present invention is not limited by any theory of operation, it is believed that the sacrificial SiC in the powder and in the sacrificial wafers evolves Si vapor, thereby protecting the implanted surfaces from damage during annealing. EXAMPLE 2 A 6H-SiC sample that has the same epilayer structure and doping concentration as the starting wafer discussed in Example 1, , was used for this experiment to compare the hole mobilities in sample implanted at 600C and room temperature with the same does of C and Al at die same energies. The starting SiC sample was cut into two pieces. The first pieces was implanted at 600C and the second piece was implanted at room temperature, both with multiple doses and energies of lxlO¹⁶ cm^"2 at 196 keV, 4xl0¹⁵ cm^'2 at 115 keV, 2.3xl0¹⁵ cm^'2 at 65 keV for Al and 6.3xl0¹⁵ cm^"2 at 122 keV, 3.4xl0¹⁵ cm^"2 at 80 keV, 2.6xl0¹⁵ cm^"2 at 52 keV, and 1.9xl0¹⁵ cm^"2 at 30 keV for C. C-12 ions were implanted first followed by Al-27. The uniformly implanted profile had a depth of around 2.200 Angstroms. The samples were annealed in apparatus as shown in Fig. 6. The implanted samples were covered first by high quality p-type 6H-SiC wafers and then loaded into the high purity graphite inner compartment 14 with the outer compartment IB filled with high purity SiC powder. The rest of the experimental procedure is the same as that described in Example 1.

After annealing, thermally evaporated Al ohmic contacts were formed on the four corners of the two implanted samples for the measurement of hole mobilities based on Hall effect. The hole mobility was measured at room temperature. It was found that the hole mobility in 600C implanted sample was improved by a factor of 4 in comparison to the hole mobility in the sample implanted at room temperature, indicating the higher implantation temperature better preserves the monocrystal quality compared to room temperature implantation. The invention described herein has been disclosed in terms of specific embodiments and applications. However, other embodiments, in light of this teaching, may be obvious to those persons skilled in the art. Accordingly, it is to be understood that the drawings and descriptions are illustrative of the principles of the invention, and should not be construed to limit the scope thereof. All of the references, patents, standards, etc. referenced in this application are incorporated herein by reference. CROSS-REFERENCE TO RELATED APPLICAΉQNS

With respect to the United States of America, the present application is a continuation-in-part of commonly assigned, copending United States Patent Application 08/632,866, the disclosure of which is hereby incorporated by reference herein.

Claims

CLAIMS:

1. A method of producing a p-doped region of silicon carbide comprising the following steps: a) directing a first ion beam onto a silicon carbide substrate to create vacancies favorable to acceptor activation; b) directing a second ion beam onto said silicon carbide substrate, said second ion beam consisting of p-type acceptor atoms and having an atomic concentration per cubic centimeter in about the same range as the atomic concentration per cubic centimeter of said first ion beam, to form an implanted silicon carbide structure; and c) annealing said implanted silicon carbide structure in an inert gas or vacuum environment at between about 1000°C to about 1700°C.

2. The method of claim 1 wherein said first ion beam consists of carbon ions.

3. The method of claim 1 wherein said second ion beam consists of aluminum ions.

4. The method of claim 1 wherein said second ion beam is made of boron ions.

5. The method of claim 1 wherein the implanted silicon carbide structure is annealed in a high purity silicon carbide crucible or other non- contaminating compartment.

6. The method of claim 1 wherein the implanted silicon carbide structure is annealed in a high purity silicon carbide crucible or odier non- contaminating compartment, said silicon carbide crucible or otiier non- contaminating compartment filled with silicon carbide powder therein.

7. The method of claim 1 or claim 6 wherein the implanted silicon carbide structure is covered by a sacrificial silicon carbide structure during step c.

8. The method as claimed in claim 7 wherein during steps a and b, said ion beams are directed into a surface of the silicon carbide substrate to thereby form the p-doped region of the substrate adjacent said surface, whereby said surface constitutes the implanted surface of the substrate, and wherein said sacrificial silicon carbide structure overlies the implanted surface of the silicon carbide substrate.

9. The method of claim 1 wherein step c is performed at between about 1000°C and 1600°C.

10. The method of claim 1 wherein step c is performed at between about 1500°C and 1700°C.

11. The method of claim 1 wherein step a is performed at 300°C or higher

12. The method of claim 11 wherein step b is performed at between about 300°C or higher.-.

13. A p-type silicon carbide semiconductor made by the method of claim 1.

14. A p-type silicon carbide semiconductor formed by ion implantation having an activation efficiency greater than 3 % .

15. A p-type silicon carbide semiconductor as claimed in claim 14 having an activation efficiency greater than 10% .

16. A p-type silicon carbide semiconductor as claimed in claim 14 having an activation efficiency greater than 50%.

17. A p-type SiC semiconductor as claimed in claim 14 having an activation efficiency greater than 80%.

18. A p-type SiC semiconductor as claimed in claim 14 having an activation efficiency greater than 90% .

19. A p-type SiC semiconductor as claimed in claim 14 having hole mobility greater tiian 1 cm /V sec at room temperature.

20. A p-type SiC semiconductor as claimed in claim 14 having hole mobility greater than 5 cm /V sec at room temperature.

21. A p-type SiC semiconductor as claimed in claim 14 having hole mobility greater than 40 cm N sec at room temperature.

22. A p-type SiC semiconductor as claimed in claim 14 having hole mobility greater than 160 cm /V sec at room temperature.

23. A p-type SiC semiconductor as claimed in claim 14 having hole concentration greater than IO¹⁶ /cm³ at room temperature.

24. A p-type SiC semiconductor as claimed in claim 14 having

17 3 hole concentration greater than 10 /cm at room temperature.

25. A p-type SiC semiconductor as claimed in claim 14 having hole concentration greater than 10 19 /cm at room temperature

26. A p-type SiC semiconductor as claimed in claim 14 having hole concentration greater than 10 /cm room temperature.