WO1997035393A1

WO1997035393A1 - Data separating device

Info

Publication number: WO1997035393A1
Application number: PCT/JP1996/000676
Authority: WO
Inventors: Hiroshi Gunji; Junko Nakase; Yukio Fujii; Katsumi Matsuno
Original assignee: Hitachi, Ltd.
Priority date: 1996-03-15
Filing date: 1996-03-15
Publication date: 1997-09-25
Also published as: JPH1198098A; US5742361A; KR970032140A; JP3641336B2

Abstract

A data separating device which can reduce the load on an analyzer. The data separating device comprises a write control section (102), memory (104), an analyzer (105), and transfer control sections (106 and 107). The write control section (102) writes packets in the memory (104) in their arriving order and send the written information to the analyzer (105), which analyzes the packets in their arriving order based on the written information and sends only the results to the transfer control sections (106 and 107). The sections (106 and 107) send the data read out from the memory (104) in the arriving order of the packets to decoders based on the above-mentioned analyzed results.

Description

Description Data separation equipment Technical field

The present invention relates to an apparatus for separating a stream obtained by multiplexing data such as video data and audio data. Background art

With the spread of applications for transmitting or recording digital video and audio data, a technique for multiplexing a plurality of video and audio data is required.

On the reproduction side, it is required to separate desired video and audio data from these multiplexed data and send them to a video decoder and an audio decoder. Such a device is called a multiplexed stream separation device.

One of the standards for multiplexing multiple videos and such data is

MPEG (Moving Pictures Expert Group) system standard Is raised.

MPEG is an international standard for digital video / audio coding and multiplexing, and the part related to multiplexing is called the MPEG system standard. The following description is based on a stream format called a transport stream (TS) in the MPEG2 system standard.

TS is a stream format that allows multiple programs to be multiplexed on a single stream, and is mainly applied for broadcasting. The TS is a series of fixed-length packets of 188 bytes, and each packet includes coded video data, audio data, and information about a stream. A header is provided at the beginning of each packet, and by examining a packet identification field called a PID (Packet Identifier) in this header, the type of the bucket can be known. Can be.

Next, the procedure for separating the video and audio data of the desired program from the TS will be briefly described.

First, the TS contains information about the stream called PSK Program Specific Information in addition to the video and audio data as described above. By analyzing the PSI, a bucket containing the video and audio data of each program is included. You can see the value of PID attached to. PSI is PAT (Program Association table) and PMT (Program Map Table) .First, the PAT bucket is analyzed and the PID of the PT corresponding to the desired program number is obtained. You will get the PID of the packet containing the video and audio data of the program. If a value of $ 5 for video and audio packets is obtained, video and audio data are extracted from the corresponding packets and transferred to their respective decoders (decoders).

FIG. 4 shows a configuration example of a multiplexed stream separation device based on the MPEG system standard. The transmitted TS data 101 is separated by a separation unit 402 into a video packet, an audio bucket, and a PSI bucket.

The PSI packet is sent to the PSI analysis unit 404 through the buffer 403, where PAT and PMT are analyzed. In the initial state, only the PAT is sent to the PSI analysis unit 404, and the PAT force analysis is performed. If the PID power attached to the PMT packet is found, * the PSI analysis unit 404 sends (ii) to the separation unit 402, and the PAT and PMT are sent to the PSI analysis unit 404. Further, when the PMT is analyzed and the PID values of the video packet and the audio packet are obtained, the PSI analysis unit 404 sends the PID to the separation unit 402. In this way, the video bucket and the audio bucket are transferred from the separation unit 402 to the buffer 403, respectively, and sequentially sent to the video decoder and the audio decoder (108, 109). However, since it is necessary to remove the TS header and the like to the video decoder and the audio decoder before sending, it is necessary to skip the header when writing / exiting the buffer 403. Disclosure of the invention

In the multiplexed stream demultiplexer having the above-described configuration, a buffer is provided for each bucket type, and the management of those buffers becomes complicated. In particular, if PSI analysis and TS header reading are skipped, and buffer management is performed by the CPU of one PSI analysis unit 404 (software management), it is necessary to perform multiple buffer management processes independently. Instead, the load on the analysis processing unit, which is the CPU, becomes heavy.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a data separation device capable of reducing the processing of an analysis processing unit.

The above purpose is to construct the data separation device with a write control unit, a memory, an analysis processing unit, and a transfer control unit. The analysis processing unit analyzes the buckets in the order of arrival of the buckets based on the above information, sends only the analysis results to the transfer control unit, and reads them from the memory in the order of arrival of the buckets. The transfer control unit basically achieves the data by sending the data to the decoder based on the analysis result. Specific embodiments of the present invention include:

A data separation device for separating an input stream obtained by multiplexing a plurality of data and outputting desired data,

A memory (104, 304) for storing the data of the input stream in a plurality of storage areas; and receiving the data of the input stream and storing the data in bucket units obtained from the data in the memory (104, 304). A write control unit (102, 302) for writing to one storage area of the plurality of storage areas of (304);

An analysis processing unit (105) for reading the data in units of the bucket from the memories (104, 304), analyzing the type of the read data, and generating analysis information;

A plurality of transfer controllers (106, 107) for transferring data read from the memories (104, 304) to the output thereof in response to the analysis information from the analysis processor (105). Become

When the plurality of packet units of data are sequentially written from the write control unit (102, 302) to the memories (104, 304), the write address information of each of the plurality of bucket units of data is read from the FIFO. Stored in the memory (FIFO) sequentially,

The analysis processing unit (105) sequentially reads data in bucket units from the memories (104, 304) according to the write address information sequentially read from the FIFO memory (FIFO), and analyzes the type of data. Generate analysis information sequentially,

One transfer control unit of the plurality of transfer control units (106, 107) selectively responds to the analysis information from the analysis processing unit (105), and stores one storage area of the memory (104, 304). It is characterized by transferring the data read out from the output to its output (see FIGS. 1 and 3).

More specific embodiments of the present invention are:

The memory (104, 304), the analysis processing unit (105), and the plurality of transfer control units (106, 107) are interconnected via a bus (103),

The analysis processing unit (105) is configured by a CPU,

The FIFO memory is hardware inside the CPU of the analysis processing unit (105).

Other more specific embodiments of the present invention include:

The analysis processing unit (105) is configured by a CPU,

The FIFO memory is realized by software for controlling the operation of the CPU of the analysis processing unit (105).

A more preferred embodiment of the present invention is

One of the plurality of transfer control units (106, 107) is the analysis processing unit. In response to the analysis information from (105) as a transfer request interrupt signal, data is read from one storage area of the memory (104, 304), and the read data is output to its output. It is characterized by transferring.

Preferred embodiments of the present invention are:

The above input stream is data in which at least two data of video and audio are multiplexed,

The plurality of transfer control units (106, 107) include at least two of a video transfer control unit (106) and an audio transfer control unit (107),

The analysis processing unit (105) sequentially reads data in bucket units from the memories (104, 304) in accordance with the write address information sequentially read from the FIFO memory (FIFO), and at least the video and audio data are read. By analyzing the two types of data, analysis information is generated sequentially,

The video transfer control unit (106) selectively responds to the fact that the analysis information of the analysis processing unit (105) is the type of video data, and stores the data in the memories (104, 304). Transfer the data read from one storage area to its output,

The audio transfer control unit (107) selectively responds to the fact that the analysis information from the analysis processing unit (105) is the type of audio data, and responds to one of the memories (104, 304). Data read from the storage area is transferred to its output.

A more preferred embodiment of the present invention is

The memory (304) is a dual-port memory in which a write data terminal is connected to the burn-in control unit and a read data terminal is connected to the plurality of transfer control units.

Other objects and novel features of the present invention will become apparent from the following examples. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a configuration of a multiplexed stream separation device according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the flow of management information in the multiplexed stream demultiplexer according to the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a multiplexed stream separating apparatus according to another embodiment of the present invention.

FIG. 4 is a diagram showing the configuration of a multiplex stream separation device according to a conventional system. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a configuration of a multiplex stream separation apparatus according to an embodiment of the present invention will be described with reference to the drawings. And the operation will be described in detail. The embodiments described below relate to a device for separating TS specified in the MPEG2 system standard, and can be applied to a multiplexed stream separating device that receives another multiplexed stream and other data separating devices. Things.

Example 1

FIG. 1 is a diagram showing a first embodiment of a multiplexed stream separation device according to a first embodiment of the present invention.

In FIG. 1, reference numeral 102 denotes a write control unit for writing input TS data to a memory 104; 103, a data path; 104, a memory; 105, an analysis processing unit for analyzing a TS packet; and 106, video data. A video transfer control unit (Video) 107 for transferring the audio data to the video decoder is an audio transfer control unit (Audio) for transferring the audio data to the audio decoder.

Note that a packet buffer for storing the received TS packet is provided in the memory 104, and a plurality of packets can be stored.

The analysis processing unit 105 is implemented using a CPU (Central Processing Unit) because of its complicated processing.

Further, in the memory 104, a storage area as a main memory for storing software for controlling the operation of the CPU as the analysis processing unit 105 is also allocated. This main memory can be connected to the data bus 103 separately from the memory 104.

In FIG. 1, the transmitted TS data 101 is divided into bucket units by a write control unit 102 and transferred to the memory 104 in bucket units. The transfer control from the write control unit 102 to the memory 104 may be performed by the write control unit 102 itself, or the arrival of the bucket may be notified to the analysis processing unit 105 by an interrupt or the like, and the analysis processing unit 105 may perform DMA (Dircct Memory Access ) May be performed. That is, in the latter case, when the CPU as the analysis processing unit 105 receives a DMA transfer interrupt request, the TS data 101 in bucket units is directly DMA transferred from the write control unit 102 to the memory 104 via the data bus 103. You.

In any case, at the time of DMA transfer of the TS data 101 in bucket units from the write control unit 102 to the memory 104, the analysis processing unit 105 sends bucket write address information on where in the memory 104 the packet was written. Is sent. The packet harmful address information may be an address signal in a memory or a packet buffer number. The case of a packet buffer number will be described below. The analysis processing unit 105 performs bucket analysis based on the bucket write address information based on the bucket buffer number. Since the bucket analysis needs to be performed in the order of arrival of the bucket, the analysis processing unit 105 has a First in First Out memory (hereinafter, referred to as FIFO), Packet address information (packet buffer number) is sequentially stored in this FIFO. Since the analysis processing unit 105 is configured by the CPU as described above, this FIFO can be realized by dedicated hardware inside the CPU, and the operation of the CPU stored in the memory 104 as the main memory can be performed. It can also be realized by software that controls

That is, the analysis processing unit 105 sequentially reads the bucket buffer number from the FIFO realized in this way, reads data from the packet buffer of the memory 104 corresponding to the bucket buffer number, and performs analysis processing on the data of this bucket. I do. As a result of analysis, if the bucket is PSI, the analysis result is retained. If the packet is a video or audio data bucket, transfer the bucket buffer number, video or audio type information, and the position of the data to be transferred to the video or audio decoder in the bucket data. The information is sent to each video transfer control unit 106 and audio transfer control unit 107 as information.

The video transfer control unit 106 and the audio transfer control unit 107 receive the above-described transfer information from the FIFO, and selectively transfer the bucket data read from the memory 104 in the order of the bucket arrival in accordance with the type of video or audio. Forward to output. That is, when the transfer information from the FIFO indicates that the data of the read packet is video, the video transfer control unit 106 selectively responds to the transfer information to read the packet. Transfer the data to its output. At this time, the video transfer control unit 106 reads the data of the corresponding bucket from the memory 104 in response to the transfer information from the FIFO as an interrupt signal of the DMA transfer request, and transfers the data to the video decoder of the output. Conversely, when the transfer data from the FIFO indicates that the data of the bucket from which the data is read is audio, the audio transfer control unit 107 selectively reads the packet read in response to the transfer information. To the output. At this time, the audio transfer control unit 107 reads the data of the corresponding bucket in the memory 104 in response to the transfer information from the FIFO as an interrupt signal of the DMA transfer request, and transfers the read data to the audio decoder. I do. The actual transfer of the data to the output of the video transfer control unit 106 or the audio transfer control unit 107 is in response to a request from a video or audio decoder (108, 109).

When the PSI analysis processing by the analysis processing unit 105 is completed, or when the transfer to the video transfer control unit 106 or the audio transfer control unit 107 is completed and the transfer processing of one bucket is completed, the analysis processing unit 105 , video transfer control unit 106, or audio transfer control unit 107 is transferred via the data bus 103 a packet Tobaffa number that has been bucket ^solved? store finished already analysis processing or transfer processing to the write processing section 102. In response to the transferred bucket buffer number, the write processing unit 102 empties the corresponding bucket buffer and can store the next arriving TS bucket. To

FIG. 2 shows the flow of management information of the multiplexed stream demultiplexer having the configuration shown in FIG. 1 described above. When one bucket of data is sequentially written into the bucket buffer of the memory 104 by the write control unit 102 when the TS bucket arrives, the number of the written bucket buffer is sequentially output from the write control unit 102 (201). The output bucket buffer number is sent to the analysis processing unit 105 through the FIFQ 210, and is sequentially read out by the analysis processing unit 105. The order of reading bucket buffer numbers from the ECFO is the order of writing packet buffer numbers to the FIFO. That is, the analysis processing unit 105 reads the bucket buffer number from the FIFO 210 to analyze the contents of the bucket in the order of arrival.

If the bucket is a PSI, after the analysis is completed, the corresponding bucket buffer number is transferred to the damage control unit 102 (204), and the corresponding bucket buffer in the memory 104 is set to “free”.

On the other hand, when the content of the bucket is video or audio, transfer information such as a bucket buffer number is transferred from the FIFQ211 to the corresponding transfer control unit 106, 107. The transfer controllers 106 and 107 selectively respond to the transfer information read from the FIFQ 211, and transfer one packet of video or audio data to the video or audio decoder on the output side. More specifically, the video or audio transfer control units 106 and 107 read the corresponding bucket data from the memory 104 in response to the transfer information from the FIFO as an interrupt signal of the DMA transfer request, and output the video or Transfer to audio decoder. After the transfer of one bucket is completed, the transfer control units 106 and 107 send the corresponding packet buffer numbers to the write control unit (205 and 206), and make the corresponding packet buffer in the memory 104 “empty”.

Next, the write control unit 102 writes the next arrived TS packet into the above-mentioned “empty” packet buffer. At this time, if there are multiple “empty” bucket buffers, it is optional to write the arrived TS packet to which packet buffer. This is because, as described above, the data can be transferred to the analysis / decoder in the order of arrival of the TS packets despite writing to any bucket buffer in the memory 104. , ヽヽ * The management can be simplified.

In the above description, only the PSI, video, and audio packets required for processing are shown.However, actual TS buckets include other packets that are not required for processing, such as data from other programs. Have been. It is necessary to discard such an invalid bucket, but since the invalid bucket can be determined by the PID attached to the packet, the value of the PID of the bucket necessary for processing is written from the analysis processing unit 105 and controlled. Sent to section 102, and writes only the packet that matches this to the pro to the packet buffer. With such a configuration, the amount of transferred data can be reduced.

Example 2

The In Figure 3 _c illustrates a structure of the multiplexed stream demultiplexer apparatus according to second embodiment, 302 is a write control unit for writing the TS bucket bets to be input to the memory 304 of Figure 3 is the invention, 304 Dual Port memory, 103 is a data bus, 105 is an analysis processor that analyzes TS packets, 106 is a video transfer controller (Video) that transfers video data to a video decoder, and 107 is audio that transfers audio data to an audio decoder It is a transfer control unit (Audio).

The embodiment of FIG. 3 is particularly different from the embodiment of FIG. 1 in that a memory 304 for storing a plurality of received TS buckets is a dual-port memory in which writing and reading can be performed independently. . That is, the write data terminal of the dual port memory 304 is connected to the write control unit 304, while the read data terminal is connected to the video transfer control unit 106 and the audio transfer control unit 107 via the data bus 103, Writing and reading can be performed in parallel. Therefore, in parallel with the process of sequentially writing TS packets from the write control unit 302 to the dual port memory 304, the transfer from the dual port memory 304 to the video transfer control unit 106 and the audio transfer control unit 107 is performed. Sequential reading of data of one packet .Transfer processing becomes possible. The processing of the sequential insertion and the sequential reading and transfer follow the bucket buffer numbers sequentially stored in the FIFO of the CPU 105 in the same manner as in the embodiment of FIG. In order to perform the parallel processing of the dual port memory 304, the path for transferring the packet buffer number from the control unit 304 to the FIFO of the CPU 105 is independent of the data bus 103 as shown by the broken line in FIG. It is desirable that

The operation of the multiplexed stream demultiplexer according to the second embodiment of the present invention shown in FIG. 3 is basically the same as that of the first embodiment shown in FIG.

With the configuration as in the first and second embodiments, the buffer management in the analysis processing unit as the CPU is simplified, and the load on the analysis processing unit as the CPU is reduced.

Further, by adopting the configuration as in the second embodiment, it is not necessary to use the data bus 103 to which the CPU is connected to write the TS data to the memory 304, and the write control unit 302 and the analysis processing unit 105 are connected. It can be used more efficiently.

Although the embodiments of the present invention have been described in detail, the present invention is not limited to the above-described specific embodiments, and it goes without saying that various modifications can be made within the scope of the technical idea. No.

For example, in the description of the above embodiment, the case where the analysis processing unit is configured by the CPU has been described. However, the same applies when the analysis processing unit is configured by the dedicated hardware. The process can be performed. Also, the write control units 102 and 302, the video transfer control unit 106, and the audio transfer control unit 107 do not necessarily need to be dedicated hardware, and any or all of them can be processed by the CPU.

According to the present invention, it is possible to provide a data separation device capable of reducing the processing of the analysis processing unit. Industrial applicability

INDUSTRIAL APPLICATION This invention can be utilized for the apparatus which isolate | separates the stream which multiplexed data, such as video and audio. In particular, it can be applied to a decoder that multiplexes video and audio data according to the MPEG system standard.

Claims

The scope of the claims

1. A data separation device for separating an input stream obtained by multiplexing a plurality of data and outputting desired data,

A memory for storing the data of the input stream in a plurality of storage areas; receiving the data of the input stream; and storing data in bucket units obtained from the data in one of the storage areas of the memory; A write control unit for writing to the storage area of the

An analysis processing unit that reads the data in the bucket unit from the memory, analyzes the type of the read data, and generates analysis information;

And a plurality of transfer control units for transferring data read from the memory to the output in response to the analysis information from the analysis processing unit,

When a plurality of bucket units of data are sequentially written into the memory from the harm control unit, the write address information of each of the plurality of bucket units of data is sequentially stored in a FIFO memory.

The analysis processing unit sequentially generates data by sequentially reading data in packet units from the memory according to the write address information sequentially read from the FIFO memory and analyzing the type of data,

One transfer control unit of the plurality of transfer control units selectively responds to the analysis information from the analysis processing unit and transfers data read from one storage area of the memory to its output. A data separation device, comprising:

2.The memory, the analysis processing unit, and the plurality of transfer control units are interconnected via a bus,

The analysis processing unit is configured by a CPU,

2. The data separation device according to claim 1, wherein the FIFO memory is hardware inside the CPU of the analysis processing unit.

3.The memory, the analysis processing unit, and the plurality of transfer control units are mutually connected via a bus,

The analysis processing unit is configured by a CPU,

2. The data separation device according to claim 1, wherein the FIFO memory is realized by software for controlling an operation of the CPU of the analysis processing unit.

4.One transfer control unit of the plurality of transfer control units selectively responds to the analysis information from the analysis processing unit as a transfer request interrupt signal, reads data from one storage area of the memory, 4. The data separation device according to claim 1, wherein the read data is transferred to an output thereof.

5. The input stream is data in which at least two data of video and audio are multiplexed,

The plurality of transfer control units include at least two of a video transfer control unit and an audio transfer control unit,

The analysis processing unit sequentially reads data in packet units from the memory according to the write address information sequentially read from the FEFO memory, and analyzes by analyzing at least two types of data of video and audio. Information is generated sequentially,

The video transfer control section selectively responds to the fact that the analysis information from the analysis processing section is the type of video data, and transfers the data read from one storage area of the memory to its output. And

The audio transfer control unit selectively responds to the fact that the analysis information from the analysis processing unit is of the type of genius data, and converts the data read from one storage area of the memory. The data separation device according to any one of claims 1 to 4, wherein the data is transferred to the output.

6. The memory according to claim 1, wherein the memory is a dual-port memory having a write data terminal connected to the write control unit and a read data terminal connected to the plurality of transfer control units. The data separation device according to any one of the ranges up to the fifth paragraph.