WO1997035341A1 - Semiconductor storage device and its manufacture - Google Patents

Abstract

Short circuits often occur between upper and lower capacitor electrodes due to particles deposited on side edges of a very small multilayer capacitor during its dry etching for a lithographic process. This problem is solved by using an electrode material (for example, Pt) whose reaction products caused by etching have low volatility. After the upper metallic electrode (111) is dry-etched, a side wall spacer (114) is formed before the dry etching of the lower metallic electrode (108) is started. Since nothing is deposited on the tapered part of the spacer (114) due to a self-cleaning action which occurs during the dry etching, no short circuit occurs between the electrodes (111 and 108).

Description

 Description: Semiconductor storage device and method of manufacturing the same

 The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a dynamic random access memory (DRAM) or a domain-inverted nonvolatile memory suitable for a large-scale integrated memory. Background art

To obtain a suitable small area and a large capacity capacitor in large-scale integrated memory, it is effective to use a high-dielectric insulating film such as Ta ₂ 0 ₅ and BST as a capacitor insulating film. If a ferroelectric insulating film such as PZT is used as a capacitor insulating film, a nonvolatile memory using spontaneous polarization can be obtained. Since ferroelectric substances have extremely large relative dielectric constants of hundreds to thousands, they are also effective as a capacitor insulating film of Dynamitsu Random Access Memory <High dielectric insulating film / ferroelectric insulating film When using as a capacitor insulating film, the selection of the electrode material becomes important. This is because if the electrode material is oxidized during the formation of the insulating film to form an insulator having a low dielectric constant, the capacity of the capacitor is reduced.

Therefore, materials that are difficult to be oxidized or materials in which oxides are used as conductors have been selected as compressible materials. Pt, 0s, Au, etc. are less susceptible to oxidation, and Pt is generally used. Oxides are the material becomes a conductor has Ru0 _2, I r0 _2, as an electrode material _{Ru, Ru0 2, I r,} I r0 2 , etc. are used. As a capacitor structure using these insulating film and electrode materials, a structure as shown in Fig. 26 was reported in IEDM (International ELECTRON DEVICES Meeting) Technical Digest, 1994, P.843-P.846. This structure requires multiple masks and has a small effective area relative to the total area of the capacitor.

 Also, as shown in Fig. 27, the technique of processing the upper electrode, insulating film, and lower electrode in one lithography process is described in Mat. Res. Soc. Symp. Proc. Vol. 310 (1993) P .127-P.133, Japanese Patent Application Laid-Open Nos. 05-299601 and 6-342774.

 Further, as a Pt etching method, Japanese Patent Application Laid-Open No. 5-89662 discloses a technique of performing etching while suppressing Pt re-adhesion using a Ti mask.

 Furthermore, Japanese Patent Laid-Open No. 4-159679 discloses a technique for changing the area of the upper electrode and the lower electrode, or processing the end of the strong dielectric insulating film obliquely to eliminate the distortion of the film thickness change due to the polarization reversal. It is disclosed in the official gazette.

 Then, after etching the lower electrode and the strong dielectric insulating film. By forming a side wall and then forming an upper electrode, a technology to increase the mask alignment margin and prevent short-circuit between electrodes And Japanese Patent Application Laid-Open No. 6-132482.

 By the way, it has been recognized by the present inventors that the following problems occur when dry etching is performed on the structure shown in FIG.

As shown in FIG. 28, there is a problem that the side wall adhesion film 113 mainly composed of the electrode material adheres to the side walls of the mask 112, the upper metal electrode 111, the capacitor insulating film 109, and the lower metal electrode. This is remarkable when Pt or the like which is hardly oxidized is used as the electrode material. The fact that it is difficult to oxidize means that it is difficult to change to a volatile substance by a chemical reaction, and the electrode material is mainly etched by physical sputtering. This sputtered electrode material adheres to the side walls. Oxide becomes conductor

Even for RuO ₂ and IrO ₂ , the etching reaction product has low volatility, so that the sidewall adhesion film 113 is also formed.

 This side wall adhesion film 113 must be removed because it causes a short circuit of the capacitor. However, for example, wet cleaning using an acid or the like has a problem that the capacitor insulating film is deteriorated. Next, techniques proposed prior to the present invention as solutions to the above-described problems will be described below.

 The proposed technology uses the fact that the etch rate in dry etching varies depending on the incident angle of ions, and removes side wall deposits on the electrode material by self-cleaning during dry etching. That is.

The principle of this self-cleaning is shown in FIG. The etch speed depends on angle 0. Let this be R (0). Since e = o on the bottom surface, the etching speed on the bottom surface of the electrode material is R (0). Assuming that a proportion of the etched electrode material adheres to the pattern sidewall, the deposition rate is aR (0). Assuming that the taper angle of the pattern is 0, the etch rate of the deposited film on the side wall is R (0). Here, in order to obtain a clean side wall by self-cleaning, the etch rate R (Θ) on the side wall needs to be higher than the vertical thickness aR (O) / cos0 of the deposited film. In other words, aR (0) / cos 0≤R (ø) force, ', conditions for obtaining clean side walls. Transform this conditional expression Then, R (0) cos 0 / R (O) ≥ a, and the left side is a value that can be calculated from literature values, and the right side is a value that can be obtained from experiments. Figure 30 shows the calculated and experimental values. Using α = 0.3 obtained from experimental values, it can be seen that when the taper angle is 75 degrees or less, dry etching without side wall adhesion film is possible by self-cleaning. In other words, if the angle of the taper of the mask and capacitor is set to 75 degrees or less, the problem of sidewall deposits can be solved.

 Figure 31 shows an improved capacitor structure based on the above findings. The semiconductor memory device S shown in FIG. 31 is a cross-sectional view of a main part at the stage when a capacitor of a semiconductor memory is formed.

In FIG. 31, an element isolation region 102 is first formed on a semiconductor substrate 101. Next, an M0S transistor including the gate electrode 104 and the diffusion layer 105 is formed. Next, after flattening with an interlayer insulating film 105, a plug 106 is formed in the through hole of the interlayer insulating layer 105 by using CVD and dry etching. On this plug, a barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using a mask and a mask 112 of each electrode. Here, the mask 112 is previously formed into a taper shape having a taper angle of 75 degrees or less, and the taper angle of the capacitor can be formed to 75 degrees or less by dry etching based on Ar physical sputtering. In this way, a capacitor having no sidewall adhesion film can be formed. The completed capacitor has a tapered shape, and depending on the thickness of each layer of the capacitor, there is a limit to the degree of integration due to an increase in the bottom area of the capacitor. However, there is no problem in practical use. Semiconductor memory such as DRAM The major challenge is to reduce the cell area as the capacity increases and to improve the degree of integration.

 Therefore, a typical object of the present invention is to overcome the above-mentioned problems, and to provide a highly integrated and highly reliable semiconductor memory device.

 Another representative object of the present invention is to provide a manufacturing method capable of realizing the above-described semiconductor memory device by a relatively simple process. Disclosure of the invention

According to a semiconductor storage device according to a representative embodiment of the present invention, a stacked capacitor including a lower electrode, an insulating film, and an upper electrode is provided on a main surface of a semiconductor substrate, and charges are stored in the capacitor. Alternatively, in a semiconductor storage device having a function of storing an electric signal by polarization inversion of an insulating film, a side wall of the capacitor has a side wall spacer, and the upper electrode is provided with the upper electrode. It is located inside the doorspacer. This ensures that the side of the lower electrode and the side of the upper electrode are electrically separated, so that there is no short between the two electrodes, and the semiconductor memory device is particularly suitable for high integration. According to a method of manufacturing a semiconductor memory device having a multilayer capacitor according to a typical embodiment of the present invention, after performing dry etching of an upper electrode, forming a sidewall spacer prior to dry etching of a lower electrode. It is characterized by: As a result, the tapered portion of the side wall spacer does not adhere to the side wall due to self-cleaning during dry etching, so that processing without a short shot becomes possible, and high reliability and high integration are achieved. Thus, a semiconductor memory device is obtained. BRIEF DESCRIPTION OF THE FIGURES

 FIG. 1 is a sectional view of a main part of a semiconductor memory device according to a first embodiment of the present invention.

 FIG. 2 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention.

 FIG. 3 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 2;

 FIG. 4 is a fragmentary cross-sectional view following FIG. 3 showing the manufacturing steps of the semiconductor memory device S of the first embodiment of the present invention.

 FIG. 5 is a fragmentary cross-sectional view following FIG. 4, showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention;

 FIG. 6 is a fragmentary sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 5;

 FIG. 7 is an essential part cross sectional view showing the manufacturing process of the semiconductor memory device of the first embodiment of the present invention, following FIG. 6;

 FIG. 8 is a cross-sectional view of the essential part showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG.

 FIG. 9 is a fragmentary cross-sectional view following FIG. 8, showing the manufacturing steps of the semiconductor memory device of the first embodiment of the present invention.

 FIG. 10 is an essential part cross sectional view showing the manufacturing step of the semiconductor memory device of the first embodiment of the present invention, following FIG. 9;

 FIG. 11 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 10;

FIG. 12 shows a semiconductor according to the first embodiment of the present invention, following FIG. FIG. 14 is a cross-sectional view of a main part showing a manufacturing step of the storage device.

 FIG. 13 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 12;

 FIG. 14 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the first embodiment of the present invention, following FIG. 13;

 FIG. 15 is a fragmentary cross-sectional view showing a semiconductor memory device according to a second embodiment of the present invention.

 FIG. 16 is a sectional view showing a main part of a semiconductor memory device according to a third embodiment of the present invention.

 FIG. 17 is a sectional view showing a main part of a semiconductor memory device according to a fourth embodiment of the present invention.

 FIG. 18 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the fifth embodiment of the present invention.

 FIG. 19 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device of the fifth embodiment of the present invention, following FIG. 18;

 FIG. 20 is a fragmentary cross-sectional view showing a manufacturing step of the semiconductor memory device according to the sixth embodiment of the present invention, following FIG. 19;

 FIG. 21 is a plan view showing a sixth embodiment, in particular, a memory cell layout to which the first embodiment is applied.

 FIG. 22 is a sectional view taken along the line AA of FIG. 21.

 FIG. 23 is a plan view showing a seventh embodiment, in particular, another memory cell layout to which the first embodiment is applied.

 FIG. 24 is a plan view showing an eighth embodiment, in particular, another memory cell layout to which the first embodiment is applied.

 FIG. 25 is a sectional view taken along the line AA ′ shown in FIG. 24.

FIG. 26 is a cross-sectional view of a main part of a conventionally known memory cell. FIG. 27 is a cross-sectional view of main parts of another conventionally known memory cell. FIG. 28 is a fragmentary cross-sectional view for explaining problems in the method of manufacturing the memory cell shown in FIG. 27;

 FIG. 29 is an explanatory diagram of a method of obtaining a clean side wall condition, which is a means of the present invention.

 FIG. 30 is a graph showing a range of clean side wall conditions, which is a means of the present invention.

 Fig. 31 is a cross-sectional view of the main part of the capacitor proposed earlier. BEST MODE FOR CARRYING OUT THE INVENTION

 The present invention will be described in more detail with reference to the accompanying drawings.

 (Example 1)

 A first embodiment of the present invention will be described with reference to FIG.

 FIG. 1 is a cross-sectional view of a main part of a semiconductor pathological device (hereinafter referred to as a semiconductor memory) at a stage where a capacitor is formed. The manufacturing process of this semiconductor memory is briefly described as follows.

 First, an element isolation region 102 is formed on a substrate 101. Next, a MISFET (absolute gate field effect transistor) including the gate electrode 104 and the semiconductor region (diffusion layer) 103 is formed.

Next, after flattening with an interlayer insulating film 105, a plug 106 is formed using CVD and dry etching. On this plug 106, a barrier layer 107, a lower metal electrode 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using the same mask as the deposition of each layer. On the plug 106, a barrier species 107, a lower metal cladding 108, a capacitor insulating film 109, and an upper metal electrode 111 are formed by dry etching using the same mask as the deposition of each layer, In this embodiment, after etching the upper electrode 111 and the capacitor insulating film 109, a side wall spacer 114 is formed, and then the lower metal electrode 108 and the barrier layer 107 are etched to form a capacitor. Since a taper angle (Θ) is formed at the portion of the wall spacer 114, the deposited electrode material is removed by self-cleaning at this portion, so that a capacitor having no side wall deposition film can be formed.

 As is clear from the present embodiment, the completed multilayer capacitor has the side wall of the upper electrode U1 covered with the side wall base 114. That is, the upper electrode 111 is located inside the side wall spacer 114.

 The method for forming the capacitor will be specifically described with reference to cross-sectional views of essential parts showing the manufacturing process shown in FIG. 2 to FIG.

 First, as shown in FIG. 2, an element isolation region 102 is formed in a semiconductor substrate (for example, a P-type Si substrate or a P-type well region) 101. Specifically, the element isolation region 102 is formed of an oxide film selectively formed on the main surface of the semiconductor substrate 101 by LOCOS (Local Oxidation of Silicon) technology. Next, a MISFET is formed by the gate electrode 104 and the diffusion layer 103. Although not shown in FIG. 2, the gate oxide film below the gate electrode 104 is formed to a predetermined thickness prior to the formation of the gate electrode.

Next, after an interlayer insulating film, for example, a SOG (Spin On Glass) film 105 is covered and flattened by a reflow process, a through hole is provided in the interlayer insulating film 105. Then, the W (tungsten) plug 106 is formed so as to fill the through hole provided in the interlayer insulating film 105 by using a CVD technique and an etch pack by dry etching. A capacitor is formed on the plug 106. That is, the barrier layer 107, the lower metal layer 115, the insulating film layer 116, the upper metal layer 117, the hard mask layer 118 and a resist mask 119 are sequentially formed. When Pt is used for the lower metal layer and the upper metal layer, if W is used for the hard mask layer 118, an etching using Ar plasma can obtain a Pt / W selectivity of 2 or more. The Nono Domasuku layer 118 may be an insulating material such as Si0 ₂ or Si ₂ N ₃ or A1 ₂ 0 _3, it may be used a metal such as A1 or Cu. Further, as the barrier layer 107, TiN is preferable. As the insulating film layer 116, high dielectric or the like Ta ₂ 0 ₅ or BST, other ferroelectrics such as PZT or PLZT, even in the case of using a dielectric such as Si0 ₂ or Si ₂ N 3, the electrode material This is effective when the side wall is formed by etching.

Next, as shown in FIG. 3, a hard mask 120 is formed. The hard mask 120 is processed so as to have a taper angle of 75 degrees or less. As for the taper processing method, when a metal is used as a hard mask, tapering can be performed by processing under conditions that allow side etching by dry etching, or processing may be performed by wet etching. If an insulator is used as a hard mask, it can be processed by either time modulation dry etching, in which deposition and dry etching are alternately performed, or wet etching. For example, when using W as a hard mask, if the temperature of the substrate (semiconductor substrate) is etched near room temperature by dry etching using SF ₆ plasma, taper processing by side etching is possible. The taper angle can be controlled by controlling the side etching amount and controlling the ion energy by the bias. Next, as shown in FIG. 4, the resist mask on the hard mask 120 is removed by an ashing step.

Next, as shown in FIG. 5, the upper metal S (117) is dry-etched to form an upper metal electrode 111. When Pt is used as the upper metal layer, for example, Ar gas is When sputter etching is performed under the conditions of a pressure of 10 mTorr and RF of 500 W, etching can be performed at an etching speed of 20 nm / min. When using the same as the hard mask 120, 3 is obtained as the mask selectivity under this condition. Even when using a less oxidized material, such as an electrode material Pt and 0s and Pd and Ail, even if they are use a material oxide exhibits conductivity, such as Ru and I r and Ru0 ₂ and I r0 ₂ Dry etching may be performed by physical sputtering using a rare gas plasma such as Ar or Ar, or dry etching using a halogen-based gas containing F, C 1, or Br. Even in dry etching by physical sputtering using Ar gas plasma with Pt, if the hard mask 120 has a taper angle of 75 degrees or less, there is no side wall adhesion on the side wall of the hard mask 120 due to self-cleaning during dry etching. Dry etching is possible.

Next, as shown in FIG. 6, the capacitor insulating film 109 is processed by etching. If sputtering by Ar plasma or the like is used for this etching, since the selectivity with the lower metal layer 115 is low, the base metal layer 115 is shaved at the end of the etching, and the side wall adhesion film is formed on the side of the capacitor insulating film 109. There is a drawback that it may be formed on the wall, but there is no practical problem if the in-plane distribution of the etching rate is controlled uniformly. Also, if a gas containing halogen such as Cl ₂ or SF ₆ or a mixed gas thereof or a mixed gas with a rare gas is used, the selectivity with the lower metal layer becomes higher, and the abrasion of the base metal S 115 is further reduced. It is difficult to get up. Further, as will be described in a later embodiment, the process may proceed to the next step before the etching of the capacitor insulating film 109 is completed. When PZT is used as the insulating film of the capacitor, for example, using a mixed gas of Ar and CF ₄ gas as an etching gas, the PZT etch is performed at RF 500 W and a pressure of 10 mTorr in a parallel plate type etching apparatus. Etching can be performed at a speed of 40 nm / min. W as hard mask 120 In this case, a mask selectivity of 4 is obtained under these conditions. When Pt is used as the lower metal layer, a selectivity of 3 against the lower metal under this etching condition is obtained.

Next, as shown in FIG. 7, an insulating film layer 121 is deposited by a CVD method. Specifically, absolute緣膜layer 121 is Si0 ₂ film. Then, as shown in FIG. 8, a reseal wall spacer 114 is formed by etching back. The material of the insulation緣膜layer 121, S ^ in addition to Si0 _2, such as _{A1 2 0 3, Ti0 2,} Ta 2 0 6, those capable of deposition by CVD is selected. Next, as shown in FIG. 9, the lower metal layer (115) is etched to form a lower metal electrode. At this time, the sidewall attachment film 113 adheres to the pattern vertical portion, but the sidewall of the hard mask 120 and the sidewall spacer 114 has a taper angle, so that the sidewall attachment film does not adhere. For example, when using cyclic Douorusu spacers 114 to Si0 ₂ using Pt as the lower metal eyebrows, the sputtering by Ar gas plasma, since Pt / Si0 ₂ etch rate ratio is about 1, Sa I Douorusu in the lower Pt etching The spacer 114 is also etched. If the side spacers 114 are etched by the height of the hard mask 120 during the lower Pt etching, as shown in FIG. 9, the side wall spacers _U4 are located beside the upper metal electrode 111 and the capacitor insulating film 109. Processing that can be formed only can be performed. Such processing involves controlling the height of the hard mask at the time of forming the sidewall spacer in FIG. 8 (this can be controlled by the deposited film thickness of the hard mask layer), and the Pt / Si0 ₂ can be formed by controlling the etch rate ratio. The conditions and film thickness for this addition differ depending on the material of the lower electrode, the material of the sidewall spacer, the etching gas and the etching equipment, but it is necessary to control the thickness of the hard mask layer and control the etch rate ratio. Changes Absent.

 The sidewall adhesion film 113 does not need to be removed because there is no short-circuit problem because of the presence of the sidewall spacer 114, but it does not need to be removed, but it increases the reliability of the process and suppresses variations in product characteristics. Therefore, it is desirable to remove them. Therefore, in this embodiment, as shown in FIG. 10, the side wall adhesion film was removed by wet treatment. As a treatment method, aqua regia is effective in the case of Pt deposits, and in the case of other substances, a solution treatment appropriate for the type may be performed. It is also effective depending on the type of the lower metal material, such as a downflow plasma treatment and a paper treatment. When Pt is used as in this embodiment, aqua regia is effective, and when a metal material such as W is used as a hard mask, the hard mask is also removed at the same time. Next, as shown in FIG. 11, the barrier layer 107 is etched. The order of this etching and the removal of the side wall adhesion film may be interchanged.

 Next, as shown in FIG. 12, an insulating film layer 122 is deposited. By using a riff film such as BPSG or S0G as the deposited film, a flat surface required for the following wiring process can be formed at this point. A flat surface can be created by using etch pack technology or CMP (chemical mechanical polishing) technology, etc., and a sputter insulating film or a CVD insulating film may be used. Next, as shown in FIG. 13, the insulating film layer 122 is processed by etching or CMP until the upper metal electrode 111 is exposed.

 Next, as shown in FIG. 14, a plate electrode 123 is formed. This plate electrode 123 is subjected to wiring processing as necessary. Further, by performing necessary wiring processing, a DRAM device is formed.

By using the manufacturing method described above, even if a material having low volatility of an etching reaction product is used as an electrode material, it is possible to form a multilayer capacitor having no short-circuit due to a sidewall adhesion film. And such A semiconductor memory having high integration and high reliability can be formed without deteriorating the characteristics of a high dielectric / ferroelectric insulator by the electrode material.

(Example 2)

 A second embodiment of the present invention will be described with reference to FIG.

 As shown in FIG. 15, a side wall spacer 114 is formed immediately after the etching of the upper metal electrode 111, and thereafter, the etching of the capacitor insulating film 109 and the lower metal electrode 108 is performed. However, it is possible to prevent short-circuit between the upper metal compressing electrode 1 and the lower metal electrode 108 due to the side wall adhesion film 113. In this case, since the capacitor insulating film 109 is in contact with the side wall adhering film 1, if the wet process is performed to remove the side wall adhering film 113, the electrical characteristics of the capacitor insulating film 109 may be deteriorated. A memory cell is formed with the sidewall adhesion film 1 13 left. If the sidewall adhesion film 113 can be removed without deteriorating the electrical characteristics, the treatment may be performed.

 According to this embodiment, the size of the capacitor insulating film 109 and the lower metal electrode 108 are substantially the same, and the length of the lower side of the upper metal electrode 111 is longer than the length of the upper side of the insulating film 109. It is characterized by being short. In other words, in FIG. 15, the condition is that Le <Li.

 (Example 3)

 A third embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 16, during the etching process of the capacitor insulating film 109, a sidewall spacer 114 is formed. In the method described in the third embodiment, when the in-plane uniformity of the etching is poor, the base metal film is shaved at the end of the etching of the capacitor insulating film 109, and the upper metal electrode is formed before forming the sidewall spacer. And the lower metal layer may be short-circuited by the sidewall adhesion film. According to the present embodiment, the length of the upper side of the insulating film 109 is shorter than the length of the lower side of the insulator 109. That is, in FIG. 16, there is a relationship of L bi> L ui.

 With the structure of the present embodiment, the problem of the short circuit can be prevented.

 (Example 4)

 A fourth embodiment of the present invention will be described with reference to FIG.

 FIG. 17 shows a structure formed by a method in which the step of removing the sidewall adhesion film 113 is omitted from the method described in the first embodiment. If the sidewall adhesion film 113 is made of a stable material such as Pt, it does not need to be removed, so that it can be manufactured at low cost by omitting the steps.

 (Example 5)

 A fifth embodiment of the present invention will be described with reference to FIGS. This embodiment is obtained by omitting some steps from the method of the first embodiment. The omitted step is the step of forming the capacitor by etching and then flattening it with a reflow film or CMP.

 The semiconductor memory shown in FIG. 18 is formed by the following steps.

 An element isolation region 102 is formed on a semiconductor substrate 101, and a gate electrode (omitted in this drawing) and a diffusion layer 103 are formed. Thereafter, an interlayer insulating film 105 and a plug 106 are formed, and then an upper metal electrode 111, a capacitor insulating film 109, a side spacer 114, and a lower metal electrode 108 are formed using a film deposition and etching process. After performing the sidewall adhesion film removing step, the barrier layer 107 is etched to form a capacitor. Up to this point, the method is the same as that described in the first embodiment.

After that, a CVD insulating film layer 121 is deposited. As shown in the figure, the deposited film thickness should be more than 1/2 of the distance between adjacent capacitors. As the material of the insulating film layer, the material described in Embodiment 3 may be used. Next, as shown in FIG. 19, the capacitor isolation portion 124 is formed by etching-packing the CVD insulating layer. By etching back the CVD insulating layer deposited more than half of the capacitor interval, the step between the capacitors is reduced. Next, as shown in FIG. 20, a plate electrode 123 is formed. Since the steps are alleviated by the capacitor separating portion 124, the plate electrode 123 can be formed as a highly reliable plate electrode which does not break even when the sputtering method is used. To alleviate the step, it is sufficient to increase the thickness of the CVD insulating film layer. However, if the thickness is increased, there is a problem that the processing time of the deposition and etching steps becomes longer and the throughput is reduced, but there is no problem in practical use. Also, if the CVD insulating film layer is thinner than 1/2, the effect of alleviating the step is reduced. However, in the case of a capacitor with a thin film thickness and a wide space, the capacitor separating portion 124 is formed by the side wall of the capacitor. This is effective because the vertical steps are inclined. The present embodiment is particularly effective when a fine and highly integrated memory is to be manufactured, when the height of the capacitors is almost equal to the interval between the capacitors and the step between the capacitors is steep. Even in such a case, since the processing can be performed without using a time-consuming process such as reflow or CMP, the throughput can be increased.

 (Example 6)

 FIG. 21 shows an embodiment of a planar layout of a memory cell according to the present invention.

This layout uses a two-intersection cell and a COB (Capacitor Over Bitline) structure that forms a capacitor on a bit line. The transistors (not explicitly shown) of each memory cell are connected to peripheral circuits (not shown) via bit lines 208. The connection between the transistor and bit line 208 is part of the active area 218 This is the portion of the formed bit line plug 207. The operation of the transistor is controlled by a word line (gate electrode) 203. This word line (gate electrode) 203 is connected to a peripheral circuit (not shown). The connection from the transistor to the capacitor section 220 is made via a capacitor plug 211. The capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.

 The first feature of this planar layout is that one plate electrode 216 is wired for two word lines 203. With such a layout, the capacity of the plate electrode 216 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 216 can be easily controlled by a peripheral circuit. Therefore, the operation of the nonvolatile memory using ferroelectricity becomes easy. In this embodiment, an example in which one plate electrode is provided for two word lines has been described. However, the number of plate electrodes may be one plate electrode for one word line. Alternatively, one plate may be used for three or more lead wires. However, if the number of plate electrodes increases, it becomes difficult to increase the degree of integration. If the number of plate electrodes decreases, the capacitance of the plate electrode increases, making control by peripheral circuits difficult. The optimal number of plate electrodes varies depending on the memory application.

 The second feature of this planar layout is that the blade electrode 216 is wired in the same direction as the lead wire (gate electrode) 203. Therefore, when the potential of the plate compressing electrode 216 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the lead wire 203.

 FIG. 22 shows a cross-sectional structure (cross-section A-A ′) of FIG. 21. This cross-sectional structure will be described below.

An S i 02 202 for element isolation is formed on an S i substrate 201. In the element area, A MISFET consisting of a gate oxide film (not shown), word lines (gate electrodes) 203 and diffusion layers 204 is formed. In this embodiment, Wa lead wire 203 is used Si02 222 Yes and re processed by the dry etching as a mask, and the insulating protective film as it leaves the word lines Si0 ₂ 222. The Si0 ₂ 222 need not to leave it, to delete the structure and to Re when removing step of the present embodiment, also acts as a protective film at the time of forming the gate electrode spacer 221. As the word line, doped poly Si, which is often used as a normal gate electrode, or a silicide such as WSi, oSi, or CoSi may be used. Alternatively, a metal material such as W or TiN, or a film thereof may be used.

 The word line (gate electrode) 203 has a gate electrode spacer 221 formed thereon. Although this gate electrode spacer is not essential, it has the effect of alleviating steps and the effect of preventing electrical shorts, so that a highly reliable C0B structure can be formed.

A word line insulating protective film 205 is formed on the word line (gate electrode) 203. Although this protective film is not always necessary, it has an effect of preventing an electrical short-circuit when performing dry etching for forming the bit line plug 207 and the capacitor plug 211. If the material is changed (for example, Si ₃ N, and Si 0 ₂ ) between the plug portion and the word line step flattening insulating film 206, the above-described plug portion can be self-aligned using high selective dry etching between insulating films. There is an effect that dry etching can also be performed.

The step formed by forming the word line (gate electrode) 203 is flattened by the word line step flattening insulating film 206. As a material for the insulating film, a fluid insulating film (such as BPSG) or a CVD insulating film may be used. Planarization methods include reflow of the fluid insulating film and dry etching. W

19 All-over etch back, polishing such as CMP, or a combination thereof may be used. In this embodiment, the BPSG reflow film is polished by CMP to form the word line step flattening insulating film 206. Since this film is easily removed by dry etching, in this embodiment, an insulating protective film 223 for a planarizing insulating film is formed. If this film is formed by a CVD-sputter deposition method, a denser film can be formed than a reflow film. As the material of the film may be those used in the S i 0 ₂ and S ₃ N <as any conventional S i LS I process.

 After the formation of the insulating protective film 223 for the planarizing insulating film, a bit line plug 207 is formed. In this embodiment, the bit line plug 207 is formed by forming a hole pattern by dry etching and then forming n + polySi by using a CVD method. The bit line plug 207 may be made of a material such as T i N in addition to 11 + poly S i. Also, with the formation of the bit line plug 207, the bit line 208 shown in FIG. 21 is also formed. As this material, a material such as n + polySi, silicide, or a laminated film thereof may be used.

In this embodiment, after the formation of the bit line plug 207 and the bit line 208 (shown in FIG. 21), the insulating protection film 209 for the bit line is formed. This film is not essential, but has the same effect as the word line insulating protective film 205. Further, a bit line step flattening insulating film 210 is formed thereon. The formation method and material of this film may be considered in the same manner as the word line step flattening insulating film 206. Further, on this film, an insulating protective film 224 for flattening insulating film is formed in this embodiment. Although this protective film is not essential, it has the same effect as the above-described green protective film 223 for a planarizing insulating film. Since Furthermore, the child of the film becomes the base film in the dry etching of the capacitor, when an insulating film containing A1 atoms such as A1 ₂ 0 _3, allows a high selective dry etching in the dry etching of the capacitor. In this embodiment, When Pt is used for the capacitor lower electrode 212, and Pt is dry-etched with an F-based gas, dry etching using an Ar or C1-based gas can be processed to a shape that is more vertical. By using a material containing an underlying layer and to A1 atoms at this time, in order volatile reaction products A1F ₃ was low, etching resistance can be high because high selective dry etching. In this process, if a material containing A1 atoms such as A1 is also used as the mask material, Pt dry etching with a high selectivity between the mask and the underlayer can be performed.

After the formation of the insulating protective film 224 for the planarizing insulating film, the capacitor plug 211 is formed. In this formation, after forming a hole pattern by dry etching, a conductive material is embedded in the hole pattern. As the material, n + poly Si used in the conventional Si LSI process may be used, or a material such as TiN, W, Ta, or Ti may be embedded by CVD. The strong誘鼋of absolute緣膜and good compatibility with Pt, Ru, Ir, Pd, Rh, 0s, Hf, Zr and those are electrically conductive and their oxides (for example Ru0 _2, Ir0 ₂₎ even by using a Good. Further, a stacked film thereof may be used. Ru0 be formed using a CVD process, such as ₂ or Ir0 _2, etc. are M0CVD method, can be formed without disconnection of the hole pattern, when the laminated and Ru or 〖r thereon, Ru Since materials such as Ir and Ir act as a barrier layer against oxygen, the oxidation resistance in subsequent steps can be improved.

After the capacitor plug 211 is formed, the capacitor upper electrode 214, the capacitor insulating film 213, the side electrode spacer 217, the capacitor lower electrode 212, and the barrier metal 219 are formed by the process described in the third embodiment. It is formed. As described in the third embodiment, the Pt etching may be performed by Ar sputtering, and the PZT etching may be performed by CF ₄ + Ar gas collective dry etching using a W hard mask as described in the third embodiment. Also By using an insulating material comprising A 1 atoms as I Douorusu spacers 217 (e.g., A 1 ₂ 0 ₃₎ dry etching Pt may be Doraietsuchin grayed by F-based gas. In addition, even if a C 1 -based or Br-based gas is used for PZT or Pt etching, it is possible to perform processing without any practical problems if the etching conditions are carefully examined. As the lower electrode of the capacitor, other than PI, Ru, Ir, Pd, Rh, Os, Hf, or an oxide thereof and having conductivity may be used. Also, ferroelectric insulators other than PZT (insulating films containing Bi, insulating films containing La or Y, insulating films containing Ba or Sr, insulating films containing Cu) may be used. As the capacitor upper electrode, in addition to the capacitor lower electrode material, W or A1, which can be used as a hard mask, TiN, Ta, Cu, Ag, Au, or the like may be used. It may be used, or a stacked film thereof may be used.

 After the formation of the capacitor portion, an insulating protective film 215 for a capacitor is formed in this embodiment. In this embodiment, this film is flattened by a combination of a reflow film and CMP. Although complete flattening is not essential, it is desirable to flatten as much as possible to improve the reliability of the wiring thereafter. The flattening method and material may be the same as the formation of the bit line step flattening insulating film and the formation of the word line step flattening insulating film. Furthermore, an oxide film such as Ti, Zr, or Pb, which is compatible with the material of the capacitor part, is formed using a CVD method as a protective insulating film of the capacitor part, and then a reflow insulating film is formed to form a laminated film. Good. In addition, the ferroelectric insulating film tends to deteriorate its characteristics in a reducing atmosphere or an atmosphere in which H atoms are generated.

And CVD-S i 0 ₂ film, it may be used an organic insulating material such as PI Q (Poryimi de I Seo India Loki mystery dione).

After the formation of the insulating protection film 215 for the capacitor, the plate electrode 216 is formed in this embodiment. Such materials include 11+ pol y Si and W What is necessary is just to use a material conventionally used in the Si LSI process. If the underlayer is sufficiently planarized, a conductive material deposited by sputtering may be used as the electrode material, and in the case of a stepped structure as shown in FIG. May be used to deposit a conductive material. By processing the deposited conductive material by dry etching, a structure shown in FIG. 22 can be formed.

 FIG. 22 shows a cross-sectional view of the memory cell section up to the formation of the plate electrode. Needless to say, in actual memory, it is necessary to form two or more eyebrows to connect the memory cell part and peripheral circuits, and also to perform packaging.

 (Example 7)

 FIG. 23 shows another embodiment of the planar layout of the memory cell according to the present invention. This layout uses a two-intersection cell and a COB (Capacitor Over Bit Line) structure that forms a capacitor on a bit line. The transistors (not explicitly shown) of each memory cell are connected to peripheral circuits (not shown) via bit lines 208. The connection between the transistor and the bit line 208 is a bit line plug 207 formed in a part of the active region 218. The operation of the transistor is controlled by a word line (gate / pole) 203. This word line (gate gate) 203 is connected to peripheral circuits (not shown). The transistor is connected to the capacitor section 220 via the capacitor plug 211. The capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.

The first feature of this planar layout is that one plate electrode 216 is wired for one bit line 208. With such a layout, the capacity of the plate electrode 216 is smaller than that of a normal DRAM. This makes it easier to control the potential of the plate electrode 216 by a peripheral circuit. Therefore, the operation of the nonvolatile memory using ferroelectricity becomes easy. In the present embodiment, an example in which one plate electrode is provided for one bit line is described. However, the number of plate electrodes is set to one plate electrode for two or more bit lines. Is also good. However, as the number of plate electrodes decreases, the capacitance of the plate electrode increases, making control by peripheral circuits difficult. The optimal number of plate electrodes depends on the application of the memory.

 The second feature of this planar layout is that the plate electrode 216 is wired in the same direction as the bit line 208. Therefore, when the potential of the plate electrode 216 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the bit line 208.

 (Example 8)

 FIG. 24 shows another embodiment of the planar layout of the memory cell according to the present invention. This layout uses a two-intersection cell and a COB (Capacitor Over Bitline) structure that forms a capacitor on a bit line. The transistor (not explicitly shown) of each memory cell is connected to a peripheral circuit (not shown) via a bit line 208. The connection between the transistor and the bit line 208 is a bit line plug 207 formed in a part of the active region 218. The operation of the transistor is controlled by a word line (gate electrode) 203. This word line (gate electrode) 203 is connected to a peripheral circuit (not shown). The transistor is connected to the capacitor section 220 via the capacitor plug 211. The capacitor section 220 is connected to a peripheral circuit (not shown) via a plate electrode 216.

The first feature of this planar layout is that the DRAM operation is considered That is, the capacitor is controlled by the plate electrode 216.

With such a layout, the reference potential required for DRAM operation can be applied to the capacitor. If the driving capability of the peripheral circuit is sufficiently increased, nonvolatile operation is possible. The number of capacitors controlled by one plate electrode 216 may be adjusted according to the application of the memory. FIG. 25 shows a cross-sectional structure (cross-section AA ′) in FIG. This cross-sectional structure is basically the same as FIG. 202 described in Embodiment 8 except for the plate electrode 216. The processing of the plate electrode 216 may be performed to a required size as in the eighth embodiment.

 According to the present invention, in a semiconductor memory using a dielectric / ferroelectric capacitor using an electrode material having a low volatility of an etching reaction product, a problem occurs when a capacitor is processed in only one lithography step. It is possible to prevent a short circuit between the poles. As a result, a margin for mask alignment is not required, and a highly integrated semiconductor memory using a fine capacitor can be added.

 Industrial applicability

 As described above, the present invention is useful as a highly reliable and highly integrated capacitor, and is suitable for use in large-capacity DRAMs of 1 gigabit or more.

Claims

The scope of the claims 1. A multilayer capacitor composed of a lower electrode, an insulating film, and an upper electrode is provided on the main surface of the semiconductor substrate, and charge is stored in the capacitor or the capacitor is inverted by polarization inversion of the insulating film. In a semiconductor memory device having a function of storing an electric signal, a side wall of the capacitor has a side wall spacer, and the upper electrode is located inside the side wall spacer. Semiconductor storage device.  2. The semiconductor memory device according to claim 1, wherein said side walls cover side portions of an upper electrode.  3. The semiconductor memory device according to claim 1, wherein said side wall spacer covers a side portion of an upper electrode and an insulating film. 4. The range of claim 2, wherein the size of the insulating film and the lower electrode is substantially the same, and the length of the lower side of the upper electrode is shorter than the length of the upper side of the absolutely green film. The semiconductor memory device described.  5. The semiconductor memory device according to claim 2, wherein a length of an upper side of the insulating film is shorter than a length of a lower side of the insulator. 6. The semiconductor memory device according to claim 3, wherein a length of a lower side of the insulating film is shorter than a length of an upper side of the lower metal electrode. 7. The upper耄極is Pt, 0s, Pd, Au, Ru, I r, Ru0 2 and claims, characterized in that it consists of at least one material which is selected from I r0 ₂ range as set forth in claim 1, wherein Semiconductor storage device. 8. The rhino Dowo one pulse spacer one is _{S i0 2, S i 3 N} 4, A1 2 0 3, Ti 0 _2, the semiconductor memory device as set forth in claim 1, wherein claims, characterized in that the Ta ₂ 0 ₅ is a CVD insulating film made of at least one material selected. 9. A semiconductor substrate, An MISFET having a plurality of semiconductor regions formed on a main surface of the semiconductor substrate and a gate electrode;  An interlayer insulating film formed on the main surface of the semiconductor substrate so as to cover the MISFET, and having a through hole on a selected main surface of the semiconductor region of the semiconductor region;  A plug provided in the through hole and electrically connected to the selected semiconductor region;  A multilayer capacitor electrically connected to the plug and patterned on a main surface of the inter-S insulating film, comprising a lower hail pole, an insulating film, and an upper electrode; and And a plate wiring electrically connected to the upper electrode.  A semiconductor memory device having a side wall spacer on a side portion of the capacitor, wherein the upper electrode is located inside the side wall spacer.  10. The semiconductor memory device according to claim 9, wherein said side wall spacer covers a side portion of an upper electrode.  11. The semiconductor memory device according to claim 9, wherein the side wall spacer covers a side portion of the upper electrode and the insulating film. 12. The semiconductor memory device according to claim 9, wherein said plug is made of tungsten.  13. A method of manufacturing a semiconductor memory device having a multilayer capacitor composed of a lower electrode, a dielectric film, and an upper electrode on a main surface of a semiconductor substrate, wherein a first metal is provided on the main surface of the semiconductor substrate. The stage of corkscrew layers,  Depositing a first insulating film on the first metal layer main surface,  Depositing a second gold-extended layer on the first insulating film layer main surface, Providing a mask of a predetermined pattern shape on the main surface of the second metal layer, O 97/35341 Etching the second metal layer using a 27 mask to form an upper electrode,  Depositing a second insulating film layer so as to cover the upper electrode,  Etching the second insulating film layer so as to form a side wall spacer composed of the second insulating film layer on the side of the upper electrode, and thereafter, the first insulating film layer Etching the first metal layer and the first metal layer to form a dielectric film and a lower electrode, A method for manufacturing a semiconductor memory device, comprising:  14. A method for manufacturing a semiconductor memory device having a stacked capacitor composed of a lower electrode, a dielectric film, and an upper electrode on a main surface of a semiconductor substrate, wherein a first metal is provided on the main surface of the semiconductor substrate. Depositing layers,  Depositing a first insulating layer on the main surface of the first metal layer,  Depositing a second metal layer on the main surface of the first insulating film layer;  Providing a mask of a predetermined pattern on the main surface of the second metal layer, and etching the second metal layer using the mask to form an upper electrode;  Etching halfway through the first insulating film layer,  Depositing a second insulating film layer on the upper electrode and the first insulating film layer;  Etching back the second insulating film layer;  Etching the remaining portion of the first insulating film layer and the first metal layer to form a dielectric film and a lower electrode; A method for manufacturing a semiconductor memory device, comprising: 15. A method for manufacturing a semiconductor memory device having a multilayer capacitor composed of a lower electrode, a dielectric film, and an upper compressing electrode on a main surface of a semiconductor substrate, wherein the first surface of the semiconductor substrate is Depositing metal exhibition, Depositing a first insulating film layer on the first metal eyebrow main surface,  Depositing a second metal layer on the main surface of the first insulating film,  A mask having a predetermined pattern is provided on the main surface of the second metal layer, and the second metal layer and the first insulating film layer are etched using the mask to form an upper electrode and a dielectric film. Stage to do  Depositing a second insulating film layer on the upper electrode and the dielectric film; etching back the second insulating film; and providing a side wall spacer on the upper electrode and a side of the dielectric film. Providing,  A method for manufacturing a semiconductor useful device, comprising:  16. A method for manufacturing a semiconductor memory device having a multilayer capacitor composed of a lower metal electrode, an insulating film, and an upper metal electrode, wherein a first metal JS is deposited and a first insulating film layer is formed. Depositing a second metal layer, forming a mask, etching the second metal layer using the mask to form an upper south pole, etching the first insulating film layer, Deposit two insulating layers and etch back this second insulating layer. Forming a capacitor by etching the first metal layer, removing deposits on a side wall of the capacitor, and thereafter forming a wiring connected to an upper electrode of the capacitor. Manufacturing method of storage device.  17. A method for manufacturing a laminated capacitor including a lower electrode, an insulating film, and a upper electrode, in which an upper electrode is patterned and a side wall sensor is provided on a side of the upper electrode. Forming a lower electrode by patterning the side wall spacer after forming the multilayer capacitor. 18. A method of manufacturing a β-type capacitor comprising a lower electrode, an insulating film, and an upper electrode, wherein the upper electrode is dry-etched, and A method for manufacturing a multilayer capacitor, comprising forming a side spacer prior to pole dry etching.