+

WO1997033309A1 - Method of forming a semiconductor device having trenches - Google Patents

Method of forming a semiconductor device having trenches Download PDF

Info

Publication number
WO1997033309A1
WO1997033309A1 PCT/GB1997/000615 GB9700615W WO9733309A1 WO 1997033309 A1 WO1997033309 A1 WO 1997033309A1 GB 9700615 W GB9700615 W GB 9700615W WO 9733309 A1 WO9733309 A1 WO 9733309A1
Authority
WO
WIPO (PCT)
Prior art keywords
trench
trenches
layer
wider
substrate
Prior art date
Application number
PCT/GB1997/000615
Other languages
French (fr)
Inventor
Jonathan Leslie Evans
Original Assignee
Totem Semiconductor Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Totem Semiconductor Ltd. filed Critical Totem Semiconductor Ltd.
Publication of WO1997033309A1 publication Critical patent/WO1997033309A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device (such as a trench gated semiconductor power device) .
  • the two trenches may comprise different parts of a single trench.
  • step (i) may comprise forming an array of interlinked trenches where one area of the device (for instance a trench contact area) has trench widths wider than in another area of the device (for instance an active area) .
  • the trenches may be connected for electrical continuity.
  • the two trenches may be separate and unconnected.
  • the width of the narrower trench needs to be less than twice the thickness of the layer of material.
  • An example of material which is "grown" is polysilicon.
  • the narrower trench could be filled with a layer of material which is thinner than half of the trench width.
  • the conformal deposition method comprises Chemical Vapour Deposition (CVD) , or spin-on deposition using material in a solvent or a flowed glass.
  • CVD Chemical Vapour Deposition
  • Conformal deposition results in the substrate being deposited in a fashion which attempts to maintain a constant thickness across the topology. Therefore the conformal deposition will tend to fill trenches with a dimension less than twice the thickness of the layer of material, but will cover with constant thickness surfaces of areas wider than this (i.e. the surfaces of the wider trench) .
  • the narrower trench may not be completely filled during the conformal deposition, but in general the level of material deposited in the narrow trench will be greater than the level in the wider trench.
  • the method of the present invention may be employed in one or more stages of the semiconductor device fabrication process.
  • the semiconductor device comprises a trench gated semiconductor power device such as a power MOSFET, power MESFET or power IGBT.
  • the device may comprise a logic transistor.
  • the wider trench typically comprises a gate contact trench which is subsequently filled with gate contact material, and the narrower trench comprises an active gate trench.
  • the device may comprise a memory cell. In this case the wider trench typically forms the contact to a buried cell (the narrower trench) .
  • step (ii) The type of material deposited in step (ii) will depend upon the type of device being fabricated, and the particular stage of the fabrication process.
  • the method may comprise conformal deposition followed by isotropic etching and selective etch back of the gate contact trench which results in a deeper gate contact trench. This allows a greater thickness of top ⁇ side contact deposition without the source contact (which contacts with the narrower trench) shorting out with the gate contact (which contacts with the gate contact trench) .
  • the substrate may be conformally deposited with a conductive gate electrode material such as polysilicon. The polysilicon can then be anisotropically etched back to below the silicon substrate surface, and removing the polysilicon from the bottom of the gate contact trench.
  • the method of the present invention may be employed in a planarization step in which material such as BPSG is conformally deposited and isotropically etched back to remove all of the glass in the gate contact trench.
  • the method of fabricating the semiconductor device only uses a single mask, the mask being used to form the at least two trenches in the substrate. Subsequent steps in the fabrication process do not require a conventional mask, the function of the conventional mask being carried out by the material which is left in the bottom of the narrower trench.
  • Figure 1 compares conformal deposition with non- conformal deposition
  • Figure 2 illustrates isotropic and anisotropic etches of the conformally deposited material
  • Figure 3a is a plan view of a substrate after the trenches have been etched, and before deposition;
  • Figure 3b is an enlarged plan view of part of the substrate shown in Figure 3a;
  • Figures 3c to 15 are schematic cross-sections along line A of the substrate after various stages in a method of manufacturing a device according to the present invention. in which:-
  • Figure 3c shows the substrate after trench etch
  • Figure 4 shows conformal deposition which fills the trenches
  • Figure 5 shows an optional selective etch back of the gate contact area followed by thick oxide deposition/growth.
  • Figure 6 shows conformal polysilicon deposition
  • Figure 7 shows an anisotropic etch back of polysilicon to below the silicon surface level
  • Figure 8 shows optional deposition of a silicide material (such as tantalum silicide) ;
  • Figure 9 shows the formation of the source/drain/emitter regions
  • Figure 10 shows planarization of the active trenches; (usually an oxide/glass material e.g. BPSG or spin on glass) ;
  • oxide/glass material e.g. BPSG or spin on glass
  • Figure 11 shows the trench planarisation which is completed with an etch back
  • Figure 12 shows final metallization
  • Figure 13 shows how the optional etching of the polysilicon after trench planarization (Fig. 11) allows a thicker top-side metallization to take place;
  • Figure 14 shows how a combination of the above polysilicon etch can be combined with the optional selective etch back and oxidation of Fig. 5;
  • Figure 15 shows the final stage of the processing being a passivation.
  • Figure 1 contrasts a method of conformal deposition (Figure la) with a process of non-conformal deposition ( Figure lb) .
  • a substrate 30 comprising a wider trench 31 and a narrower trench 32 are conformally coated with a layer of material 33.
  • the width of the trench 32 is less than twice the thickness of the layer 33, the narrower trench 32 is filled whilst larger areas (including the wider trench 31) are merely covered.
  • An example of a non-conformal deposition is evaporation of metal.
  • the layer of metal 34 does not coat the side walls of the trenches and fills the narrower trench 32 and wider trench 34 by equivalent amounts.
  • the invention can exploit the advantages of conformal deposition in two ways as illustrated in Figures 2a and 2b.
  • the isotropic etch of Figure 2a etches a given thickness away in all directions. In this case, the wider trench 31 is completely stripped of material 33 and the narrower trench 32 is still partially filled with the material 33.
  • the anisotropic etch of Figure 2b the anisotropic etch only etches vertically. In this case, the bottom of the wider trench 31 is stripped of material but is not fully etched away from the side walls of the wider trench 31.
  • the wider trench 31 may be etched away to give a deeper trench than the trench 32, which is effectively masked by the material 34 which remains.
  • the isotropic or anisotropic etch ( Figure 2a and Figure 2b) may be followed by another conformal or non-conformal deposition step.
  • the processing begins with a substrate which will be typically silicon or some other material.
  • silicon is a suitable substrate although the technique is not limited to silicon.
  • the substrate may be a bonded wafer in some applications.
  • the bulk of the substrate will usually be heavily doped - N or P-type depending on whether the device to be manufactured is a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) .
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • On top of this substrate will be two layers of epitaxially grown silicon of the opposite polarity. (In some cases these layers might be diffused and not grown) .
  • the next stage is to define a masking pattern.
  • this will be a thin silicon nitride or oxide layer that will have been etched according to a pattern printed by the first and only mask into a photoresist layer. This will characterise the device into two areas - the gate contact area (wide open areas) and the active area
  • the next stage will be to etch trenches into the silicon substrate. This will usually be done using a plasma etcher but can be performed using a wet etch technique.
  • Figure 3a is a plan view of a silicon substrate which is being processed according to the present invention to produce a power MOSFET.
  • the device can be separated into two distinct areas - the gate contact area 50 and the active area 5 (which are conceptually divided by a dotted line 6) .
  • Figure 3b is an enlarged view of a portion 51 of the substrate 1. As can be seen in Figure 3b, the substrate 1 has been masked and etched to leave a gate contact trench 4 to which a bond contact will eventually be attached.
  • Figure 3c is a cross-section along the line A in Figure 3b.
  • the active area 5 has a very large area of narrow trenches 7,8 which are interspersed with a hexagonal array of masked areas 52,53 etc.
  • Figures 3c to 15 are schematic cross-sections along line A in Figure 3b.
  • the upper p-type layer 2 and lower n- type layer 3 are grown or diffused on a silicon substrate (not shown) .
  • the active area 5 is distinguished by being a very large area of narrow trenches usually in the form of a hexagonal or square cellular array (although a stripe geometry can also be used) .
  • a small part of the active area containing only two active trenches 7,8 is shown in Figures 3c-15. These Figures are not to scale - the gate contact trench 4 is typically greater than 60 ⁇ m wide and the active trenches 7,8 are typically between 0.5 and 2 ⁇ m wide.
  • the technique described here allows very high cell density structures to be manufactured which gives better device performance.
  • the trenches are formed using a mask 9. The essence of a one mask process is however to reduce the processing cost and to increase yield through the use of robust "self-aligned techniques".
  • Fig. 4 we perform our first conformal process (Fig. 4) .
  • the substrate is conformally deposited with a material 10 which allows the selective removal of both silicon and silicon dioxide.
  • the material 10 are polymer based materials such as photoresist, and silicon nitride.
  • Fig. 4 When partially etched back isotropically by the thickness of the layer 10, this will expose the sides 11,12 and bottom 13 of the gate contact trench 4 whilst protecting the narrow active trenches 7,8. This is because the active trenches 7,8 are narrow enough to be filled with the material 10.
  • the next stage involves a conformal deposition of the gate electrode material 16 (Fig. 6) which typically will be doped polysilicon (although any conductive material could be used) . This is then anisotropically etched back to just below the silicon surface 17 (Fig. 7) . This means that the polysilicon 16 is removed by etching away vertically downwards and not sideways at all. This can be done using a plasma etcher. This will leave the polysilicon in the form shown.
  • Figure 8 shows the layer of non-conformally deposited silicide 18 deposited on the mask 9 and polysilicon 16.
  • n+ region 55 we now need to planarize the trenches in the active area so that the gate and source are not short circuited. Again this can be done with a conformal deposition of a dielectric material 20 (i.e. an insulator such as silicon dioxide) - Fig. 10. This can be isotropically (i.e. the same in all directions) etched back to complete the planarization and remove all of the glass in the gate contact trench 4. This results in the structure shown in Figure 11 where the active trenches 7,8 are covered in the dielectric 20 whilst the gate contact trench 4 is exposed.
  • a dielectric material 20 i.e. an insulator such as silicon dioxide
  • the original masking material 9 e.g. silicon nitride
  • contact material such as aluminium.
  • the back side of the wafer has a metal drain contact 25 deposited over the entire area of the silicon substrate 60.
  • the upper side (where all the processing has been done) has contact material 21 evaporated on so that the deposition is not conformal (see Figure 12) . This results in a physical break or discontinuity in the deposited film at the edge of the gate contact trench as indicated at 22.
  • the contact material 21 in the active area 5 constitutes a source contact
  • the contact material 21 in the gate contact trench 4 constitutes a gate contact.
  • Fig. 14 is an alternative to Figure 12 which shows how the optional two stage etch shown in Figures 4 and 5 is advantageous. If the gate contact trench is very deep, then we can deposit a larger amount of contact material 21 before reaching the surface level of the silicon, thus maintaining the break 22.
  • the thick oxide layer 15 also protects the gate contact. If the break 22 is not maintained it is likely that the material 21 in the active area and the gate contact area will meet and short circuit. For very high power devices, thick contacts will be necessary and the gate contact area will need to be correspondingly deep.
  • An alternative is to make the trench depths deep across the entire wafer. This has the disadvantage of compromising the breakdown voltage (if a two-thickness oxide process is not used) whilst also making the trench fill processes more difficult. This would however, be a good alternative in low voltage devices (-30V) .
  • the techniques described use a combination of processes which differ in their ability to fill or conformally cover trenches of varying widths. This means that a material is deposited in a fashion that the device is covered in a layer which attempts to maintain a constant thickness across the topology.
  • Such a technique (usually a chemical vapour deposition (CVD) , spin on material in a solvent or a flowed glass) will tend to fill gaps with a dimension less than twice the thickness of the film, but will cover with constant thickness, surfaces of areas wider than this.
  • CVD chemical vapour deposition
  • the resulting device structure is fully self aligned and exhibits potentially excellent performance.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A method of fabricating a semiconductor device, the method comprising (i) forming at least two trenches (4, 7, 8) in a substrate, one of the trenches being wider than the other trench; (ii) depositing a layer of material (10, 16, 20) on the substrate including the trenches by a method of conformal deposition; and (iii) etching away part of the layer of material. The widths of the trenches and the thickness of the layer of material are chosen such that the material is etched away from the bottom of the wider trench (4) but not from the bottom of the narrower trench (7, 8).

Description

METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING TRENCHES
The present invention relates to a method of manufacturing a semiconductor device (such as a trench gated semiconductor power device) .
Conventional manufacturing techniques for manufacturing trench gated semiconductor power devices typically use between four and eight mask steps and therefore the ability to perform this manufacture using less masking steps would present the opportunity to incorporate substantial savings in processing costs and time.
In accordance with the present invention there is provided a method of fabricating a semiconductor device, the method comprising
(i) forming at least two trenches in a substrate, one of the trenches being wider than the other trench;
(ii) depositing a layer of material on the substrate including the trenches by a method of conformal deposition; and
(iii) etching away part of the layer of material wherein the widths of the trenches and the thickness of the layer of material are chosen such that the material is etched away from the bottom of the wider trench but not from the bottom of the narrower trench.
The two trenches may comprise different parts of a single trench. For instance step (i) may comprise forming an array of interlinked trenches where one area of the device (for instance a trench contact area) has trench widths wider than in another area of the device (for instance an active area) . The trenches may be connected for electrical continuity. Alternatively the two trenches may be separate and unconnected.
It has been recognised that by the use of conformal deposition followed by etching in trenches of varying widths, an element of lateral control in the etching step can be achieved without the use of a mask. That is, due to the varying widths of the trenches, the conformal deposition will fill the narrower trench more quickly than the wider trench as the deposits of material on the sides of the narrower trench meet in the middle. As a result, the height of material before etching at the base of the narrower trench will be greater than the height at the base of the wider trench. During the subsequent etching operation (which may comprise an isotropic or anisotropic etch) the material at the bottom of the wider trench will be completely etched away, but material will be left at the bottom of the narrower trench.
In the case of a conformal deposition in which the layer of material is grown, the width of the narrower trench needs to be less than twice the thickness of the layer of material. An example of material which is "grown" is polysilicon. In the case where the material is deposited in liquid form, eg. as a flowed glass or spin on glass in a planarisation step, the narrower trench could be filled with a layer of material which is thinner than half of the trench width.
Typically the conformal deposition method comprises Chemical Vapour Deposition (CVD) , or spin-on deposition using material in a solvent or a flowed glass. Conformal deposition results in the substrate being deposited in a fashion which attempts to maintain a constant thickness across the topology. Therefore the conformal deposition will tend to fill trenches with a dimension less than twice the thickness of the layer of material, but will cover with constant thickness surfaces of areas wider than this (i.e. the surfaces of the wider trench) . The narrower trench may not be completely filled during the conformal deposition, but in general the level of material deposited in the narrow trench will be greater than the level in the wider trench. The method of the present invention may be employed in one or more stages of the semiconductor device fabrication process. The method of the present invention may be employed in a wide variety of semiconductor device fabrication processes. In one example the semiconductor device comprises a trench gated semiconductor power device such as a power MOSFET, power MESFET or power IGBT. Alternatively the device may comprise a logic transistor. In this case the wider trench typically comprises a gate contact trench which is subsequently filled with gate contact material, and the narrower trench comprises an active gate trench. Alternatively the device may comprise a memory cell. In this case the wider trench typically forms the contact to a buried cell (the narrower trench) .
The type of material deposited in step (ii) will depend upon the type of device being fabricated, and the particular stage of the fabrication process.
In the case of a trench gated semiconductor power device, the method may comprise conformal deposition followed by isotropic etching and selective etch back of the gate contact trench which results in a deeper gate contact trench. This allows a greater thickness of top¬ side contact deposition without the source contact (which contacts with the narrower trench) shorting out with the gate contact (which contacts with the gate contact trench) . Alternatively or in addition, the substrate may be conformally deposited with a conductive gate electrode material such as polysilicon. The polysilicon can then be anisotropically etched back to below the silicon substrate surface, and removing the polysilicon from the bottom of the gate contact trench. Alternatively or in addition the method of the present invention may be employed in a planarization step in which material such as BPSG is conformally deposited and isotropically etched back to remove all of the glass in the gate contact trench.
In a preferable embodiment, the method of fabricating the semiconductor device only uses a single mask, the mask being used to form the at least two trenches in the substrate. Subsequent steps in the fabrication process do not require a conventional mask, the function of the conventional mask being carried out by the material which is left in the bottom of the narrower trench.
An example of the invention will now be described with reference to .the accompanying drawings, in which:-
Figure 1 compares conformal deposition with non- conformal deposition;
Figure 2 illustrates isotropic and anisotropic etches of the conformally deposited material; Figure 3a is a plan view of a substrate after the trenches have been etched, and before deposition;
Figure 3b is an enlarged plan view of part of the substrate shown in Figure 3a;
Figures 3c to 15 are schematic cross-sections along line A of the substrate after various stages in a method of manufacturing a device according to the present invention; in which:-
Figure 3c shows the substrate after trench etch;
Figure 4 shows conformal deposition which fills the trenches;
Figure 5 shows an optional selective etch back of the gate contact area followed by thick oxide deposition/growth.
Figure 6 shows conformal polysilicon deposition; Figure 7 shows an anisotropic etch back of polysilicon to below the silicon surface level;
Figure 8 shows optional deposition of a silicide material (such as tantalum silicide) ;
Figure 9 shows the formation of the source/drain/emitter regions;
Figure 10 shows planarization of the active trenches; (usually an oxide/glass material e.g. BPSG or spin on glass) ;
Figure 11 shows the trench planarisation which is completed with an etch back;
Figure 12 shows final metallization; Figure 13 shows how the optional etching of the polysilicon after trench planarization (Fig. 11) allows a thicker top-side metallization to take place;
Figure 14 shows how a combination of the above polysilicon etch can be combined with the optional selective etch back and oxidation of Fig. 5; and,
Figure 15 shows the final stage of the processing being a passivation.
Figure 1 contrasts a method of conformal deposition (Figure la) with a process of non-conformal deposition (Figure lb) . In the process of conformal deposition (Figure la) , a substrate 30 comprising a wider trench 31 and a narrower trench 32 are conformally coated with a layer of material 33. As can be seen, since the width of the trench 32 is less than twice the thickness of the layer 33, the narrower trench 32 is filled whilst larger areas (including the wider trench 31) are merely covered. This can be contrasted to the non-conformal deposition illustrated in Figure lb. An example of a non-conformal deposition is evaporation of metal. In this case the layer of metal 34 does not coat the side walls of the trenches and fills the narrower trench 32 and wider trench 34 by equivalent amounts.
The invention can exploit the advantages of conformal deposition in two ways as illustrated in Figures 2a and 2b. The isotropic etch of Figure 2a etches a given thickness away in all directions. In this case, the wider trench 31 is completely stripped of material 33 and the narrower trench 32 is still partially filled with the material 33. In the anisotropic etch of Figure 2b, the anisotropic etch only etches vertically. In this case, the bottom of the wider trench 31 is stripped of material but is not fully etched away from the side walls of the wider trench 31.
After the isotropic etch shown in Figure 2a, the wider trench 31 may be etched away to give a deeper trench than the trench 32, which is effectively masked by the material 34 which remains. Alternatively, the isotropic or anisotropic etch (Figure 2a and Figure 2b) may be followed by another conformal or non-conformal deposition step.
The processing begins with a substrate which will be typically silicon or some other material. Given present technology, silicon is a suitable substrate although the technique is not limited to silicon. The substrate may be a bonded wafer in some applications. The bulk of the substrate will usually be heavily doped - N or P-type depending on whether the device to be manufactured is a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) . On top of this substrate will be two layers of epitaxially grown silicon of the opposite polarity. (In some cases these layers might be diffused and not grown) . The next stage is to define a masking pattern. Typically this will be a thin silicon nitride or oxide layer that will have been etched according to a pattern printed by the first and only mask into a photoresist layer. This will characterise the device into two areas - the gate contact area (wide open areas) and the active area
(an area of narrow features usually in a cellular pattern) .
The next stage will be to etch trenches into the silicon substrate. This will usually be done using a plasma etcher but can be performed using a wet etch technique.
Figure 3a is a plan view of a silicon substrate which is being processed according to the present invention to produce a power MOSFET. The device can be separated into two distinct areas - the gate contact area 50 and the active area 5 (which are conceptually divided by a dotted line 6) . Figure 3b is an enlarged view of a portion 51 of the substrate 1. As can be seen in Figure 3b, the substrate 1 has been masked and etched to leave a gate contact trench 4 to which a bond contact will eventually be attached. Figure 3c is a cross-section along the line A in Figure 3b. The active area 5 has a very large area of narrow trenches 7,8 which are interspersed with a hexagonal array of masked areas 52,53 etc.
Figures 3c to 15 are schematic cross-sections along line A in Figure 3b. The upper p-type layer 2 and lower n- type layer 3 are grown or diffused on a silicon substrate (not shown) .
The active area 5 is distinguished by being a very large area of narrow trenches usually in the form of a hexagonal or square cellular array (although a stripe geometry can also be used) . A small part of the active area containing only two active trenches 7,8 is shown in Figures 3c-15. These Figures are not to scale - the gate contact trench 4 is typically greater than 60 μm wide and the active trenches 7,8 are typically between 0.5 and 2 μm wide. The technique described here allows very high cell density structures to be manufactured which gives better device performance. The trenches are formed using a mask 9. The essence of a one mask process is however to reduce the processing cost and to increase yield through the use of robust "self-aligned techniques".
There is an optional step available here which complicates the process flow but will aid the final metallization step and be particularly suitable for high voltage or high current devices. Here we perform our first conformal process (Fig. 4) . In this step the substrate is conformally deposited with a material 10 which allows the selective removal of both silicon and silicon dioxide. Examples of the material 10 are polymer based materials such as photoresist, and silicon nitride. When partially etched back isotropically by the thickness of the layer 10, this will expose the sides 11,12 and bottom 13 of the gate contact trench 4 whilst protecting the narrow active trenches 7,8. This is because the active trenches 7,8 are narrow enough to be filled with the material 10. We now deepen the gate contact trench 4 by performing an anisotropic trench etch process to the level 14 shown in Figure 5. Another optional process at this stage is to oxidize the gate area with a thick oxide 15. This will reduce the gate capacitance whilst also providing a more protective and reliable interface for the gate contact than the actual thin oxide which will be used for the active area. If this process is undertaken at this stage then the protective deposition above will need to be performed with a material which will allow the selective removal of itself without the removal of the recently grown oxide. This material must be removed after the oxidation. After the stage of Figure 3 it is necessary to perform the gate oxidation. This may be done in two steps. Depending on the technique used, it may be necessary to remove the roughness on the surface of the trench by performing a sacrificial oxidation, where a thin oxide is grown and then removed to improve the electrical properties of the interface. Then the final gate oxide can be grown. This is shown as a dark line 56 in Figure 6.
The next stage (omitting Figures 4 and 5) involves a conformal deposition of the gate electrode material 16 (Fig. 6) which typically will be doped polysilicon (although any conductive material could be used) . This is then anisotropically etched back to just below the silicon surface 17 (Fig. 7) . This means that the polysilicon 16 is removed by etching away vertically downwards and not sideways at all. This can be done using a plasma etcher. This will leave the polysilicon in the form shown.
It would be possible to perform a metal evaporation at this stage to silicide the trench gate (which increases the speed of the device) whilst also protecting the base of the gate contact trench from the subsequent implant process in the absence of a two-thickness oxidation process. Figure 8 shows the layer of non-conformally deposited silicide 18 deposited on the mask 9 and polysilicon 16.
At this point we need to dope our n+ source regions. It would have been possible to perform an implant before the trench etch which could have been driven in to form the n+ regions. The following techniques however, result in narrower doping profiles and therefore allow higher cell density devices that perform better.
Using an angled implant method, it is possible to implant directly into the trench sidewalls as indicated at 19 in Figure 9 without removing the gate oxide. If we wish to diffuse the dopant into the device or use a solid source dopant, we might need to remove this oxide, in which case it will have been necessary to protect the base of the gate contact area as described above. Failure to do this will result in the gate and body of the device being short circuited.
Once the n+ region 55 has been formed (probably including a drive in/anneal) we now need to planarize the trenches in the active area so that the gate and source are not short circuited. Again this can be done with a conformal deposition of a dielectric material 20 (i.e. an insulator such as silicon dioxide) - Fig. 10. This can be isotropically (i.e. the same in all directions) etched back to complete the planarization and remove all of the glass in the gate contact trench 4. This results in the structure shown in Figure 11 where the active trenches 7,8 are covered in the dielectric 20 whilst the gate contact trench 4 is exposed.
After the trench planarization, it is necessary to remove the original masking material 9 (e.g. silicon nitride) . This must be done selectively (i.e. not removing any other material) by using a wet "strip" or plasma etch. This will expose the horizontal silicon surface between the trenches in the active area. It is now necessary to complete the device with the deposition of contact material such as aluminium. The back side of the wafer has a metal drain contact 25 deposited over the entire area of the silicon substrate 60. The upper side (where all the processing has been done) has contact material 21 evaporated on so that the deposition is not conformal (see Figure 12) . This results in a physical break or discontinuity in the deposited film at the edge of the gate contact trench as indicated at 22. The contact material 21 in the active area 5 constitutes a source contact, and the contact material 21 in the gate contact trench 4 constitutes a gate contact. Fig. 14 is an alternative to Figure 12 which shows how the optional two stage etch shown in Figures 4 and 5 is advantageous. If the gate contact trench is very deep, then we can deposit a larger amount of contact material 21 before reaching the surface level of the silicon, thus maintaining the break 22. The thick oxide layer 15 also protects the gate contact. If the break 22 is not maintained it is likely that the material 21 in the active area and the gate contact area will meet and short circuit. For very high power devices, thick contacts will be necessary and the gate contact area will need to be correspondingly deep. An alternative is to make the trench depths deep across the entire wafer. This has the disadvantage of compromising the breakdown voltage (if a two-thickness oxide process is not used) whilst also making the trench fill processes more difficult. This would however, be a good alternative in low voltage devices (-30V) .
Another option between the trench planarization (Figure 11) and the metal deposition (Figures 12,14) is another anisotropic etch of the polysilicon. This results in the polysilicon 16 in the gate contact trench 4 being etched down to the level indicated in Figure 13. The polysilicon 16 in active gate trenches 7,8 is not etched since it is masked by the dielectric material 20. This will lower the effective gate contact area depth at the walls 11,12 where the possibility of short circuit is greatest. As can be seen in Figure 13, this allows a thicker deposition of contact material 27 for a given depth of the gate contact trench 4 and active gate trenches 7,8. The final process to complete the device is a passivation (Fig 15) . This is performed by the conformal deposition of a thin layer of silicon nitride 28 or some other impervious film. This is then anisotropically etched back so that the film covers the vertical walls but is removed from the horizontal surfaces, opening up the contact areas for bonding. The techniques described use a combination of processes which differ in their ability to fill or conformally cover trenches of varying widths. This means that a material is deposited in a fashion that the device is covered in a layer which attempts to maintain a constant thickness across the topology. Such a technique (usually a chemical vapour deposition (CVD) , spin on material in a solvent or a flowed glass) will tend to fill gaps with a dimension less than twice the thickness of the film, but will cover with constant thickness, surfaces of areas wider than this.
The resulting device structure is fully self aligned and exhibits potentially excellent performance.

Claims

1. A method of fabricating a semiconductor device, the method comprising
(i) forming at least two trenches in a substrate, one of the trenches being wider than the other trench;
(ii) depositing a layer of material on the substrate including the trenches by a method of conformal deposition; and
(iii) etching away part of the layer of material wherein the widths of the trenches and the thickness of the layer of material are chosen such that the material is etched away from the bottom of the wider trench but not from the bottom of the narrower trench.
2. A method according to claim 1 wherein the widths of the trenches and the thickness of the layer of material are chosen such that the narrower trench is completely filled with the material in step (ii) and the wider trench is only partially filled in step (ii) .
3. A method according to claim 1 or 2 further comprising etching into the substrate after step (iii) whereby the remaining layer of material acts as a mask such that the depth of the wider trench is increased relative to the depth of the narrower trench.
4. A method according to any of the preceding claims wherein the method of conformal deposition comprises a chemical vapour deposition, spin-on deposition or re-flow process.
5. A method according to any of the preceding claims wherein step (iii) comprises etching the material by an isotropic technique.
6. A method according to any of claims 1 to 4 wherein step (iii) comprises etching the material by an anisotropic technique.
7. A method according to any of the preceding claims wherein the material comprises gate electrode material such as doped polysilicon.
8. A method according to any of claims l to 6 wherein the material comprises a dielectric material such as silicon dioxide, boron phosphor silicon glass or spun-on glass.
9. A method according to any of the preceding claims wherein the device comprises a trench gated power device, logic transistor or memory cell in which the wider trench comprises a gate contact trench and the narrower trench comprises an active gate trench or electrode trench.
10. A method according to any of the preceding claims further comprising (iv) depositing a second layer of material on the substrate including the trenches such that the layer is discontinuous between the trenches.
11. A method according to claim 10 wherein the second layer of material forms a contact layer.
PCT/GB1997/000615 1996-03-06 1997-03-05 Method of forming a semiconductor device having trenches WO1997033309A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9604764.2A GB9604764D0 (en) 1996-03-06 1996-03-06 Semiconductor device fabrication
GB9604764.2 1996-03-06

Publications (1)

Publication Number Publication Date
WO1997033309A1 true WO1997033309A1 (en) 1997-09-12

Family

ID=10789947

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1997/000615 WO1997033309A1 (en) 1996-03-06 1997-03-05 Method of forming a semiconductor device having trenches

Country Status (2)

Country Link
GB (1) GB9604764D0 (en)
WO (1) WO1997033309A1 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000042665A1 (en) * 1999-01-11 2000-07-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Power mos element and method for producing the same
EP1085577A3 (en) * 1999-09-13 2001-11-21 Shindengen Electric Manufacturing Company, Limited Power field-effect transistor having a trench gate electrode and method of making the same
EP1187193A3 (en) * 2000-09-07 2005-01-05 SANYO ELECTRIC Co., Ltd. Semiconductor integrated circuit device and method of manufacturing the same
WO2004102673A3 (en) * 2003-05-15 2005-01-20 Analog Power Ltd Trenched dmos devices and processes for making same
CN106449751A (en) * 2015-08-04 2017-02-22 株式会社东芝 Semiconductor device and method for manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4453305A (en) * 1981-07-31 1984-06-12 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Method for producing a MISFET
JPS62273750A (en) * 1986-05-21 1987-11-27 Toshiba Corp Semiconductor device and manufacture of the same
EP0463330A2 (en) * 1990-06-29 1992-01-02 Texas Instruments Incorporated Iterative self-aligned contact metallization process
US5086007A (en) * 1989-05-24 1992-02-04 Fuji Electric Co., Ltd. Method of manufacturing an insulated gate field effect transistor
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4256514A (en) * 1978-11-03 1981-03-17 International Business Machines Corporation Method for forming a narrow dimensioned region on a body
US4453305A (en) * 1981-07-31 1984-06-12 The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland Method for producing a MISFET
JPS62273750A (en) * 1986-05-21 1987-11-27 Toshiba Corp Semiconductor device and manufacture of the same
US5086007A (en) * 1989-05-24 1992-02-04 Fuji Electric Co., Ltd. Method of manufacturing an insulated gate field effect transistor
EP0463330A2 (en) * 1990-06-29 1992-01-02 Texas Instruments Incorporated Iterative self-aligned contact metallization process
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 012, no. 162 (E - 609) 17 May 1988 (1988-05-17) *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000042665A1 (en) * 1999-01-11 2000-07-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Power mos element and method for producing the same
US6462376B1 (en) 1999-01-11 2002-10-08 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Power MOS element and method for producing the same
EP1085577A3 (en) * 1999-09-13 2001-11-21 Shindengen Electric Manufacturing Company, Limited Power field-effect transistor having a trench gate electrode and method of making the same
US6737704B1 (en) 1999-09-13 2004-05-18 Shindengen Electric Manufacturing Co., Ltd. Transistor and method of manufacturing the same
US6872611B2 (en) 1999-09-13 2005-03-29 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing transistor
EP1187193A3 (en) * 2000-09-07 2005-01-05 SANYO ELECTRIC Co., Ltd. Semiconductor integrated circuit device and method of manufacturing the same
WO2004102673A3 (en) * 2003-05-15 2005-01-20 Analog Power Ltd Trenched dmos devices and processes for making same
CN106449751A (en) * 2015-08-04 2017-02-22 株式会社东芝 Semiconductor device and method for manufacturing the same

Also Published As

Publication number Publication date
GB9604764D0 (en) 1996-05-08

Similar Documents

Publication Publication Date Title
US11075297B2 (en) Semiconductor device and method of manufacturing semiconductor device
EP1314207B1 (en) Trench schottky rectifier
US6770539B2 (en) Vertical type MOSFET and manufacturing method thereof
JP4834228B2 (en) Method of manufacturing a trench semiconductor device with a gate oxide layer having a plurality of thicknesses
EP1281200B1 (en) Method of making a semiconductor device having a recessed insulating layer of varying thickness
US6717200B1 (en) Vertical field effect transistor with internal annular gate and method of production
US7842574B2 (en) Method of manufacturing a semiconductor power device
KR20000004472A (en) Power semiconductor device of trench gate structure and method for fabricating same
JP4382360B2 (en) Schottky rectifier and manufacturing method thereof
US9691864B1 (en) Semiconductor device having a cavity and method for manufacturing thereof
US6420768B1 (en) Trench schottky barrier rectifier and method of making the same
JPH11501769A (en) Improved semiconductor contact for thin conductive layers
EP4102545A1 (en) Charge coupled field effect rectifier diode and method of making
KR100401036B1 (en) A method of manufacturing a self-aligend vertical bipolar transistor on an soi
JP3198200B2 (en) Method of manufacturing vertical MOS transistor
CN213401190U (en) Semiconductor device with a plurality of transistors
WO1997033309A1 (en) Method of forming a semiconductor device having trenches
EP1080490B1 (en) Method of manufacturing a semiconductor device comprising a bipolar transistor and a capacitor
GB2296377A (en) Pillar bipolar transistors

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: JP

Ref document number: 97531576

Format of ref document f/p: F

122 Ep: pct application non-entry in european phase
点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载