WO1997032399A1

WO1997032399A1 - Semiconductor integrated circuit device

Info

Publication number: WO1997032399A1
Application number: PCT/JP1997/000608
Authority: WO
Inventors: Masahiro Kanai
Original assignee: Seiko Epson Corporation
Priority date: 1996-02-29
Filing date: 1997-02-28
Publication date: 1997-09-04

Abstract

A semiconductor integrated circuit device generates an output signal (Vpw) having a logical amplitude specified by a first power source (Vssl) and a third power source (Vss2) which is lower in potential than the first power source (Vssl) from a substrate bias control signal by means of a first signal voltage level converting circuit (A1) and a first logic circuit (A2) and impresses the output signal (Vpw) upon a P-well in an N-channel MOS transistor formed in a function module in the device. The device also generates another output signal (Vnw) having a logical amplitude specified by a second power source (Vdd1) and a fourth power source (Vdd2) which is higher in potential than the second power source (Vdd1) from the substrate bias control signal by means of a second signal voltage level converting circuit (B1) and a second logic circuit (B2) and impresses the signal (Vnw) upon an N-well in a P-channel MOS transistor formed in the functional module in the circuit device. When this semiconductor integrated circuit device is used, the power consumption of the device can be reduced in a standby mode by raising the threshold voltage by impressing a substrate bias, and the operating speed of the device can be increased in an operation mode by lowering the threshold voltage by releasing the device from the substrate bias. The increase of the operating speed at the operating time and the lowering of the power consumption at the standby time are simultaneously realized by securing a new power supply wiring area for controlling PMOS and NMOS back gate electrodes which are different in potential from power supply wiring and grounding wiring and providing a wiring rule which permits efficient wiring layout, and then, making the layout design of the power supply wiring and signal wiring easier.

Description

Description Semiconductor integrated circuit device

[Technical field]

The present invention relates to a semiconductor integrated circuit device including a substrate bias control circuit that controls a threshold voltage of a MOS transistor by applying a substrate bias.

[Background technology]

In general, there are various types of semiconductor integrated circuit devices such as a semiconductor memory device and a gate array. A semiconductor integrated circuit device is composed of a plurality of MOS transistors formed on one semiconductor substrate. . Normally, in such a semiconductor integrated circuit device, the potential of the semiconductor substrate is always maintained within a predetermined range.

FIG. 31 shows a schematic diagram of a chip layout of such a semiconductor integrated circuit device, for example, a gate array. This semiconductor integrated circuit device includes a functional module MO and a peripheral circuit I0 formed on a single semiconductor substrate, and the peripheral circuit 10 includes, for example, an input / output control circuit and the like. The function module M0 is a so-called internal circuit composed of a plurality of MOS transistors in order to realize necessary functions of the semiconductor integrated circuit device. Peripheral circuits including input / output control circuits and the like are also configured by MOS transistors.

For example, the layout pattern of the power supply wiring of the function block in the master slice type semiconductor integrated circuit device is shown in FIG. 33 and the inverting logic circuit shown in FIGS. 34 (a) and (b) (hereinafter referred to as the inverter circuit). Will be explained.

A master-slice type semiconductor integrated circuit device has a basic cell corresponding to logical gates such as an inverter circuit, an inverting AND circuit (hereinafter referred to as a NAND circuit), and an inverting OR circuit (hereinafter referred to as a NOR circuit). They are arranged in a shape. In other words, in this type of semiconductor integrated circuit device, a basic cell is formed on an LSI chip in advance, and only a wiring design between the basic cells is added to obtain a desired LSI. However, the layout method for power supply wiring and ground wiring is determined in advance so that all basic cells satisfy the specifications regarding electrical characteristics. The logic function block can be realized by using some basic cells, and a wiring pattern for realizing this is designed in advance in a layout and prepared as a library. FIG. 34 (a) shows a symbol of the inverter circuit I NV5, in which an output signal X is output in an inverted logic with respect to an input signal A. If this circuit is shown in a circuit diagram of a transistor level, it has a circuit configuration as shown in FIG. 34 (b).

In the inverter circuit I NV5 shown in FIG. 34 (b), the input terminal to which the input signal A is input is a gate terminal of a P-channel M〇S transistor (hereinafter referred to as PMOS) Q14 and an N-channel MO. S Transistor (hereinafter referred to as NMOS) Connected to the gate terminal of Q17. Further, the source terminal and the back gate terminal of the PMO SQ 14 are connected to the power supply line Vddl, the source terminal of the NMO SQ 17 and the back gate terminal are connected to the ground line Vss 1, and the PM0 SQ 14 In this configuration, the drain terminal and the drain terminal of NM〇SQ17 are connected by the output terminal from which the output signal X is output.

When this inverter circuit is laid out on one basic cell in a basic cell group arranged in a matrix, a wiring layout as shown in FIG. 33 is obtained.

Although the transistor configuration of this cell shown in FIG. 33 varies from company to company, here, the gate electrodes G 23, G 25 and the gate electrode G 27, which has a smaller channel width than the gate electrodes G 23, G 25, Lease 'NMO SQ 17 consisting of drain electrodes SD 33, SD 35, SD 37 and SD 39, gate electrodes G 18 and G 20, source Drain electrodes SD 28, SD 30, and SD 32 A wiring layout is performed using a basic cell having a basic unit (PM0 SQ14 or the like) composed of PM0 SQ14 and the like (2 PM〇S + 2 NMOS + 1 sub 'NMOS).

When the inverter circuits INVδ shown in FIGS. 34 (a) and 34 (b) are configured as the basic cells, the wiring layout shown in FIG. 33 is obtained. That is, the ground wiring layer Vss 1 is the first metal wiring extending in the channel length direction of the MOS transistor. Formed by layers. Through the connection hole! The ground wiring layer Vssl, the source electrode SD 35 of the MMOSQ 17, and the unused source 'drain electrode SD 33 and the gel electrode B 11 are each electrically connected.

The power supply wiring layer Vddl is formed of a first metal wiring layer extending in the channel width direction of the MOS transistor. The power supply wiring layer Vddl and the source electrode SD30 of the PMOS Q15, and the unused source / drain electrode SD28 and the well electrode B12 are electrically connected to each other through the connection holes.

The well electrode B11 extends in the channel width direction of the MOS transistor. The well electrode B11 is electrically connected to the ground wiring layer Vssl via a force connection hole C1. On the other hand, the well electrode B12 extends in the channel width direction of the MOS transistor. The well electrode B12 and the power supply wiring layer Vddl are electrically connected via the connection hole C2.

Further, an input signal A for controlling the inverter circuit I NV 5 is applied to the first metal wiring layer Ml A, and the gate electrode G 25 of NM 0 SQ 14 and the gate electrode G 20 of PM 0 SQ 17 are connected. The input signal A is applied to the gate electrodes G25 and G20 by being electrically connected to the first metal wiring layers M1A through the holes.

The output signal X is output to the first metal wiring layer M 1 X. At the output of the inverter I NV 5, the drain electrode SD 37 of the NMO SQ 14 and the drain electrode of the PMOS Q 17 The negative electrode SD32 is connected to the first metal wiring layer M1X via the connection hole. Therefore, the drain electrodes SD37 and SD32 of the NMOSQ14 and the PMOSQ17 are electrically connected in common to form an output signal. In both PM〇S and NMOS, the source electrode and the well electrode were each set to a common potential.

By the way, in recent years, there have been strong demands for higher speeds in the operation mode of microprocessors for information processing devices, such as microprocessors for personal computers and peripheral LSIs, and LSIs for portable information terminals, and low power consumption in the standby mode. It has come as required. For example, with the development of battery-powered information terminals, there has been a growing demand for compact and lightweight mobile phones and other devices that operate for long periods of time, including standby. Furthermore, with the development of digital information processing, processing of information such as voice, data, and images Since the volume is enormous and the high-speed clock is at the limit of heat generation, high-speed performance has been required. In addition, with the development of CMO SLSI branching techniques, the power consumption at the unit level has been reduced due to the improvement in the integration degree of deep submicron CMO SLSI, but the power consumption as an LSI has increased due to the increased number of elements. . For these reasons, the development of high-speed and low-power consumption CM0S technology has been promoted.

In addition, packages containing the LSI include a plastic package and a ceramic package, but an expensive ceramic package is used for the LSI with high power consumption. As described above, the power consumption is increasing due to the higher integration of semiconductor integrated circuit devices; it is considered that low power consumption is desirable from the viewpoint of cost.

Here, the power dissipation POWER is expressed by the following equation 1, where C is the load capacity, f is the clock frequency, and V is the m source voltage.

Equation 1: POWER = C · f · Vdd ^J

As can be seen from Equation 1, it is ideal to reduce the load capacitance C, clock frequency f, and power supply voltage Vdd to achieve low power consumption. It is extremely difficult to achieve both high speed in the operation mode and low power consumption in the standby mode by lowering things. In other words, since the load capacity C depends on the manufacturing process, it is necessary to provide a process step, and it is difficult to reduce the load capacity C. First, it is necessary to increase the clock frequency in order to increase the speed of operation of the conductor integrated circuit device ia. Therefore, it is desirable to reduce the clock frequency f even for low power consumption. Absent. Therefore, in order to reduce power consumption, it is most effective to reduce the power supply voltage Vdd from Equation 1.

By the way, the delay time is proportional to Equation 2 shown below. Here, in the equation 2, the coefficient is 5, the threshold voltage of the transistor is Vth, and the equation 2 is shown.

Equation 2: C · Vdd / 3 (Vdd- Vth)-'

However, as can be seen from Equation 2, lowering the power supply voltage Vdd increases the delay time and hinders speeding up. Therefore, in order to increase the speed of the semiconductor integrated circuit device without increasing the delay time, it is necessary to lower the threshold voltage Vth of the transistor. It is effective and can increase the speed without delay.

Furthermore, the leakage current during standby is proportional to Equation 3 shown below. Here, Equation 3 is shown assuming that the slope of the current Id with respect to the voltage Vg in the subthreshold region is S. Equation 3: e X p (-Vth / S)

As can be seen from Equation 3, lowering the reference voltage Vth increases the drain-source current of the transistor flowing during standby, thereby increasing the leakage current. Therefore, if the threshold voltage is changed between during operation and during standby, both operating speed and standby leakage are satisfied.

In other words, it is effective to actively utilize the substrate bias effect (or the substrate effect) as a step to satisfy both the high speed in the operation mode and the low power consumption in the standby mode.

This substrate bias effect is caused by changing the threshold voltage of the MOS transistor by applying a substrate bias to the back gate electrode of the MOS transistor, and the drain-source current with respect to the gate-source voltage in the subthreshold region. The characteristics change.

For example, the following describes the drain-source current characteristics with respect to the gate-source voltage in the subthreshold region of the NMOS transistor shown in FIG. 32 (a).

The state where the same potential as the source electrode is applied to the back gate electrode of NMOS is referred to as N 3 (threshold voltage-about +0.7 V), and the above state is obtained when a positive potential is applied to the back gate electrode with respect to the source electrode. The state changes from N 3 (threshold voltage-about +0.7 V) to state N2 (threshold voltage = about +0.5 V) or state N 1 (threshold voltage = about +0.3 V). Then, the off-state current increases as the threshold voltage of the NMOS decreases.

When a negative potential is applied to the back gate electrode with respect to the source electrode, the state N3 (threshold voltage-about +0.7 V) changes to the state N4 (threshold voltage = about +0.9 V) or Changes to N 5 (閩 value voltage-about +1.1 V). Then, the off-state current decreases as the threshold voltage of NMOS increases.

This shows the same characteristic change in the PM〇S transistor (hereinafter referred to as PMOS). For example, Fig. 32 (b) shows the drain-source current characteristics with respect to the gate-to-source voltage in the subthreshold region of the PMOS.

Is the source for the back gate electrode of PMSO? p 3

(Threshold voltage = approximately 0.7 V), and when a negative potential is applied to the back gate electrode with respect to the source electrode, contrary to NMOS, the state P 3 (閬 value voltage = approximately 1.0 .. V) to state P2 (threshold voltage = about -0.5 V) or state P1 (threshold voltage = about -0.3 V). Then, as the threshold voltage of the PMOS decreases in absolute value, the off-current increases in absolute value.

Also, contrary to the NMOS, when a positive potential is applied to the back gate electrode with respect to the base electrode, the PMOS changes from the state P 3 (threshold voltage = about 10.7 V) to the state P 4

(Threshold voltage-about-0.9V;) or to state P5 (threshold voltage = about 1.1V). Then, the wattage voltage rises in absolute value, and the off current decreases in absolute value.

Utilizing this characteristic, the sub-threshold region characteristics of the sub NMOS and PMOS can be changed to state N2 (threshold voltage = about +0.5 V), state P 2 (threshold voltage = about --0.5 V), or even more absolutely. The sub-threshold region characteristics are as follows: N1 (threshold voltage = approx. +0.3 V) and P1 (閟 value voltage = approx. -0.3 V). . Furthermore, in the operation mode, the threshold voltage of the M〇s transistor is made lower in absolute value by making the source electrode and the back gate electrode have the same potential, so that the drain current flows more in absolute value. . As a result, the speed of the switch control of the MOS transistors constituting the functional module is increased, the driving capability is improved, and the speed of the semiconductor integrated circuit device can be increased.

Conversely, in the standby mode, the threshold voltage of the MOS transistor is increased in absolute value by applying a substrate bias to the back gate electrode, and the off-state current is extremely small in absolute value N 3 (threshold voltage = Approximately +0.7 V) and state P3 (threshold voltage is approximately one-0.7 V). Alternatively, ^ indicates a state where the threshold voltage is high in absolute value N 4 (threshold voltage = about +0.9 V), state P4 (threshold voltage = about 0.9 V) or state N 5 (threshold voltage = about +1) IV), the characteristics are changed to state P5 (threshold voltage = about 1. 1. IV). Therefore, the standby current of the functional module must be extremely small. Thus, the power consumption of the semiconductor integrated circuit device can be reduced.

As described above, the application of the substrate bias effect to semiconductor integrated circuit devices has been researched and developed in recent years.However, in order to apply the substrate bias effect to semiconductor integrated circuits, the substrate potential or the jerk potential is adjusted. It is necessary to mount the substrate bias control circuit on the semiconductor integrated circuit device.

In other words, in order to apply the substrate bias effect to the above-mentioned CMOS circuit, the source electrode and the back gate electrode of the PMOS and NMOS are made independent, and the potential of the power supply wiring or the ground wiring supplied to the source electrode is A new power supply wiring for controlling different back gate electrodes is required. Furthermore, when this effect is applied to a master slice type semiconductor device, the wiring layout including power wiring, ground wiring, and signal wiring is newly designed because the layout is designed by software such as automatic placement and wiring. How to efficiently arrange the power supply lines for controlling the back gate electrodes of the provided PMOS and NM 0 S is required to secure a wiring area, and it is necessary to define a misalignment rule.

By the way, as a conventional technology for a substrate bias control circuit mounted on a semiconductor integrated circuit device using the substrate bias effect, Nikkei BP, Nikkei Micro Devices, March 1995, pp. 58-60. There is a substrate bias control circuit by Toshiba Semiconductor Device Engineering Laboratory, Tadahiro Kuroda and Takayasu Sakurai.

_C of the substrate bias control circuit 35, the evening I timing chart showing the signal waveforms shown in FIG. 36, FIG. 37

The substrate bias control circuit shown in Fig. 35 has a power supply voltage Vdd = + 2V and a ground voltage Vss = ± 0V from the outside of the conductor integrated circuit device, and a new voltage VPBB--2V for the NM 0 S P-well. The voltage VNBB = + 4 V is supplied to the N-well of PMOS. Then, the substrate bias is changed for each functional module in the semiconductor integrated circuit device, and the power and speed of all circuits are dynamically and optimally controlled.

Next, the operation of the substrate bias control circuit shown in FIG. 35 will be described with reference to FIGS.

When the chip enable signal CE is set to the high level, the inverted signal CE (bar) of the chip enable signal CE is set to the single level and the operation mode is set. Is set.

When the chip enable signal CE is set to the high level, the NMO SQ 47 is turned on, and the potential of the line VN1 is set to ± 0 V, so that the NMO SQ 49 is turned on.

When the NMO SQ 49 is turned on, the potential of the line VX2 is set to ± 0 V, and the potential of the line VN3 is set to the forwardly connected series D 1, D 2. Is approximately equal to the potential obtained by multiplying the number of connections by the threshold voltage FE of the diode. For example, when three diodes are connected in series and the threshold voltage of the diode is + 0.6V, the potential of the line VN3 is set to about + 1.8V. Note that PMO S Q 48 is always on.

By setting the ^ position of the line VN 3 to about +1.8 V, the PMO SQ 50 is turned on, the NMO SQ 57 is turned off, and the potential of the line VN 4 is set to +4 V. Then, when the potential of the line VN4 is set to +4 V, the PMO SQ 52 is turned off, the NMO SQ 59 is turned on, and the potential Vnw = + 2 V is applied to the N-well in the functional module. You.

On the other hand, when the inverted signal CE (bar) of the chip enable signal CE is set to a low level, the PMO SQ44 is turned on, and the potential of the line VP1 is set to + 2V. SQ 46 is turned on.

When the PMOSQ 46 is turned on, the potential of the line VP2 is set to +2 V. The potential of the line VP3 is almost equal to the potential obtained by multiplying the number of connected diodes D3 and D4 connected in series in the forward direction by the threshold voltage of the diode, and the potential L is the potential of the line VP2. Decreases to +2 V. For example, when three diodes are connected in series and the threshold voltage of the diode is +0.6 V, the potential of the line VP3 is about +0.2 V. NMOSG51 is always on.

By setting the potential of the line VP3 to about + 0.2V, the PMO SQ54 is turned off, the NMO SQ53 is turned on, and the potential of the line VP4 is set to 12V. When the potential of the line VP4 is set to 12 V, the PMO SQ 56 is turned on, the NMO SQ 55 is turned off, and the P-well in the functional module is connected. A voltage of Vpw = ± 0 V is applied.

Next, when the chip enable signal CE is set to a low level, the inverted signal "CE (bar) of the chip enable signal CE" is set to a high level and set to a standby mode.

When the chip enable signal CE is set to a single level, the NMO SQ 47 is turned off, and the potential of the line VN 1 is set to Vdd—Vth (Vth: threshold voltage of NM 0 SQ 49). Therefore, the NMO SQ 49 is turned off.

When the NMO SQ 49 is turned off, the potential of the line VN 2 is multiplied by the threshold voltage of the diode V 1, with respect to the voltage VNB B, by the number of connected diodes D 1 and D 2 connected in series in the forward direction. The potential drops by a potential substantially equal to the applied potential. For example, if three diodes are connected in series and the threshold voltage of the diode is +0.6 V, the level of the line V N2 is about +2.2 V. Since the PMO SQ48 is always on, the potential of the line VN3 is set to + 4V.

When the potential of the line VN3 is set to about + 4V, the PMOS Q50 is turned off, the NMOS Q57 is turned on, and the potential of the line VN4 is set to + 2V. When the potential of the line VN 4 is set to +2 V, the PM〇SQ 52 is turned on, the NMO SQ 59 is turned off, and a potential of voltage Vnw = + 4 V is applied to the N-well in the functional module. Is done. '

On the other hand, when the inverted signal CE (bar) of the chip enable signal CE is set to the high level, the PM〇SQ44 is turned off, and the potential of the line VP1 becomes Vss + Vth (Vth: PMO SQ46 PMO SQ 46 is turned off.

When the PMO SQ 46 is turned off, the potential of the line VP2 becomes equal to the number of diodes D3 and D4 connected in a row in the forward direction with respect to the voltage VPBB, and the threshold value of the diode ' It rises by a potential substantially equal to the potential multiplied by the top. For example, if two diodes are connected in series and the threshold voltage of the diode is +0.6 V, the potential of the line VP 2 will be about 10.8 V. Since NMOSQ 51 is always on, the potential of line VP 3 is set to 12 V.

When the potential of the line VP 3 is set to about −2 V, the PMO SQ 54 is turned on, NM 0 SQ 53 is turned off, and the potential of line VP 4 is set to 0 V. When the potential of the line VP4 is set to OV, the PMO SQ 5 e is turned off, the NMO SQ 55 is turned on, and the potential of the voltage Vpw = −2 V is applied to the P-well in the functional module. Applied.

Therefore, in the edict mode, the source electrode and the back gate electrode are set to the same potential, so that the threshold voltage of the MOS transistor is reduced in absolute value, and a large drain-source current flows in absolute value. As a result, the switch control of the MOS transistor that constitutes the functional module becomes faster, and the driving capability is improved.

In addition, in the standby mode, the substrate voltage is applied to the back gate electrode to reduce the absolute value of the threshold voltage, and the absolute value of the off-state current becomes extremely small. Is made very small. In other words, it realized both “¾; speeding up in the operation mode and low power consumption in the machine mode”.

However, in the conventional substrate bias control circuit shown in FIG. 35, although the standby current after switching from the operation mode to the standby mode is less than about 0.1〃Α, the standby mode changes from the standby mode to the operation mode. In the current path formed by the PMOS Q48, the diodes D1 and D2, the NMO SQ47 and Q49, there is no MOS transistor or diode element that is turned off in the current path formed by the switching to the standby current. In other words, the diode is a device that always has a voltage applied to its end, so it will not be completely turned off, but will be in equilibrium at a constant voltage. Therefore, in the substrate bias control circuit, a through current constantly flows between the voltage VNB and the ground voltage Vss. Similarly, in the current path formed by the PMO SQ44, Q46, the diodes D3, D4, and the NMO SQ51, there is no MOS transistor or diode element that is turned off. Current also flowed between voltage Vdd and voltage VP BB. However, the steady-state current in the standby mode as described above is especially important because measures to prevent leakage current in the standby mode have become indispensable due to the spread of mobile phones and the like. And the low power consumption of potential devices equipped with CM-SLSI. In order to form the diodes D l, D 2, D 3, and D 4, the NMO S Q47, Q 49, Q 57, and Q 59 are formed because the diode well region must be separated. A P-well region, a N-well region in which NMO SQ51, Qδ3, and Q55 are formed; a p-well region in which PMOS Q44, Q46, Q54, and Q56 are formed; In addition to the p-well separation of the p-well regions where 48, Q 50 and Q 52 are formed, it is necessary to perform the p-well separation by the number of diodes to be used.

However, the separation of each well requires a space of at least several m to provide a non-conductive state with the adjacent other well region, and also requires an anode electrode take-out part and a force source electrode take-out part of a diode. Therefore, the layout area has increased, which has hindered high integration of the semiconductor integrated circuit device.

Furthermore, in recent years, the LSI has adopted the form of an LSI with two power supplies, and the power supply is formed outside or inside the LSI chip, and the voltage supplied from the outside is internally switched. In particular, high voltage is often supplied from the outside, but the gate oxide film of the transistor is formed to be thicker as the applied voltage is higher.

However, as described above, the gate oxide film is becoming thinner due to the progress of high integration and miniaturization of LSIs. The thickness of the gate oxide film is adjusted according to the higher voltage of the power supply. For this reason, in the substrate bias control circuit, the thickness of the gate oxide film is formed to be large, and the long-term reliability of the gate oxide film of the transistor and the V, or the like, occur.

[Disclosure of the Invention]

An object of the present invention is to provide a semiconductor integrated circuit device having a substrate bias control circuit, which eliminates all current paths that constantly flow between power supplies, so that a standby current after switching from an operation mode to a standby mode and from a standby mode. The purpose of the present invention is to realize a high-speed and low power consumption by setting the standby current after switching to the operation mode to a very small current.

Still another object of the present invention is to provide a back bias of each of PM 0 S and NMOS having a potential different from a power supply wiring and a ground wiring when a substrate bias control circuit is applied to a master slice type semiconductor integrated circuit device. New power supply wiring area for electrode control An object of the present invention is to provide a wiring rule for efficiently laying out wiring, thereby simultaneously realizing high-speed operation and low power consumption during standby.

The semiconductor integrated circuit device of the present invention

In a semiconductor integrated circuit device having a functional module including a transistor of a first conductivity type and a transistor of a second conductivity type,

A control signal is applied to the gate electrode to control on / off, and the source electrode of the first first conductivity type is connected to a second power supply having a lower potential than the first power supply. When,

A gate electrode is controlled by an inverted signal of the control signal, ON / OFF is controlled exclusively with the transistor of the first first conductivity type, and a source electrode is connected to the second power supply. 2 first 1ΐΐ¾ transistors,

A source electrode is connected to a third power supply having a lower potential than the first power source, and based on the operation of the second transistor of the first conductivity type and the operation of the transistor of the first first conductivity type. A first second-conductivity-type transistor whose on / off is controlled by a transistor, a source electrode connected to the third power supply, and an operation of the first first-conductivity-type transistor and the second first-conductivity A second second conductivity type transistor whose on / off control is performed based on the operation of the type transistor,

The first first conductivity type transistor and the first second conductivity type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power supply. A third first conductivity type transistor having an electrode connected to the drain electrode of the first first conductivity type transistor,

The transistor is connected in series between the first first conductivity type transistor and the first second conductivity type transistor, and the gate electrode is connected to the first power supply. A third second conductivity type in which a source electrode is connected to a drain electrode of the first second conductivity type transistor, and a drain electrode is connected to a drain electrode of the third first conductivity type transistor Transistors and

The second first conductivity type transistor and the second second conductivity type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power source, and a source Electrode is connected to the drain electrode of the second first conductivity type transistor The fourth first conductivity type transistor,

The second first-conductivity-type transistor and the second second-conductivity-type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power supply, and a source A fourth second conductive S transistor having an electrode connected to the drain electrode of the second second conductive type transistor, and a drain negative electrode connected to the drain electrode of the fourth first conductive type transistor A first signal voltage level conversion circuit including:

A first logic circuit for buffering an output signal of the first signal voltage level conversion circuit to control a back gate electrode of a first conductivity type transistor constituting the functional module;

Including a substrate bias control circuit having

In the first signal voltage level conversion circuit, the drain electrode of the transistor of the first second conductivity type and the source electrode of the transistor of the third second conductivity type are connected to the second second conductivity type. The drain electrode of the second transistor of the second conductivity type and the source electrode of the transistor of the fourth second conductivity type are connected to the gate electrode of the transistor of the conductivity type. A transistor connected to a gate electrode of a transistor, wherein a flip-flop is formed by a flip-flop formed of the first second conductivity type transistor and the second second conductivity type transistor It is. Further, the semiconductor integrated circuit device of the present invention

A first second-conductivity-type transistor in which a control signal is applied to a gate electrode to control on / off and a source electrode is connected to a first power supply;

A gate electrode is controlled by an inversion signal of the control signal, and ON / OFF is controlled exclusively from the first second conductivity type transistor, and a source electrode is connected to the first power supply. A second second conductivity type transistor;

A source electrode connected to a fourth power supply, and a first electrode whose on / off is controlled based on the operation of the second second conductivity type transistor and the operation of the first second conductivity type transistor First conductivity type transistor, A source electrode is connected to the fourth power supply, and a second second transistor whose on / off is controlled based on the operation of the first second conductivity type transistor and the operation of the second second conductivity type transistor 1 conductivity type transistor,

The first second-conductivity-type transistor and the first first-conductivity-type transistor are connected in series and interposed, and a gate electrode has a higher potential than the first power supply; The third power supply of the third second conductivity type is connected to the second power supply having a lower potential than the fourth power supply, and the source electrode is connected to the drain 'of the first second conductivity type transistor. Transistors and

The transistor is connected in series between the transistor of the first second conductivity type and the transistor of the first first conductivity type, and the gate electrode is connected to the second power supply. A third first-conductivity-type transistor having a drain electrode connected to the drain electrode of the first first-conductivity-type transistor, and a drain electrode connected to the drain of the third second-conductivity-type transistor. When,

The second second conductivity type transistor and the second first conductivity type transistor are connected in series and interposed between the second second conductivity type transistor and the second first conductivity type transistor, and have a gate electrode connected to the second power supply and a source electrode. Is connected to the drain electrode of the second second conductivity type transistor, and a fourth second conductivity type transistor;

The second second conductivity type transistor and the second first conductivity type transistor are connected in series and interposed between the second second conductivity type transistor and the second first conductivity type transistor, and have a gate electrode connected to the second power supply and a source electrode. Is connected to the drain electrode of the second transistor of the first conductivity type, and the transistor of the fourth first conductivity type is connected to the drain electrode of the transistor of the fourth second conductivity type. A second signal voltage level conversion circuit including:

A second logic circuit for buffering an output signal of the second signal voltage level conversion circuit to control a back gate electrode of a second conductive transistor constituting the functional module;

Including a substrate bias control circuit having

In the second signal voltage level conversion circuit, a drain electrode of the first first conductivity type transistor and a source electrode of the third first conductivity type transistor are: The drain electrode of the second first conductivity type transistor and the source electrode of the fourth first conductivity type transistor are connected to the gate electrode of the second first conductivity type transistor. The transistor is connected to the gate electrode of a transistor of one conductivity type, and is flip-flopped by a feedback package comprising the transistor of the first first conductivity type and the transistor of the second first conductivity type. Is formed. Therefore, in the substrate bias control circuit that forms a signal to at least one of the first conductivity type and second conductivity type wells, both high speed in the operation mode and low power consumption in the standby mode are realized. In addition, in at least one of the first and second 電圧 voltage level conversion circuits constituting the substrate bias control circuit, there is eliminated a current path that constantly flows between the power supplies. The standby current after switching from the operation mode to the standby mode and from the operation mode to the operation mode can be extremely reduced, and the diode area separation becomes unnecessary, thereby reducing the layout area. be able to.

Preferred semiconductor integrated circuit devices are described below.

(1) The substrate bias control circuit, wherein the first, second, third, and fourth transistors of the first conductivity type are formed in the same region of the second conductivity type well region, A well electrode in the well region of the mold is connected to the second power source or the fourth power source having a higher potential than the second power source, and the first, second, third, and fourth second power sources are connected to each other; A transistor of a conductivity type is formed in a first conductivity type peg region in the same region, and the first signal type gage electrode has the first signal voltage level conversion circuit connected to the third power supply.

(2) The substrate bias control circuit, wherein the first and second transistors of the second conductivity type are formed in the same first region of the first conductivity type in the same region, and the first first conductivity type And a third electrode of the second conductivity type is formed in the second first conductivity type transistor region, and a second first conductivity type transistor is formed in the second first conductivity type transistor. The fourth second conductivity type transistor is formed in the third first conductivity type transistor region, and the third second conductivity type transistor is formed in the third first conductivity type transistor region. The first signal voltage level change in which the first electrode of the first conductivity type is connected to the source electrode of the fourth second conductivity type transistor. It has a conversion circuit.

(3) The substrate bias control circuit, wherein the first, second, third, and fourth transistors of the first conductivity type are formed in the same region of the second conductivity type well region, and A second electrode of the first conductive type is formed in the first conductive type plug region of the same region; The second electrode has a second signal voltage level conversion circuit connected to the first power supply or a third power supply having a lower potential than the first power supply. .

(4) The substrate bias control circuit, wherein the first and second transistors of the first conductivity type are formed in a first second conductivity type well region in the same region, and the first second conductivity type A second electrode of a second conductive type; a third electrode of a second conductive type; a third transistor of a first conductive type formed in the second conductive type; And a source electrode of the third first conductivity type transistor, and a fourth one conductivity type transistor is formed in the third second conductivity type transistor region. And the second signal voltage level conversion circuit connected to the source electrode of the fourth first conductivity type transistor in the third second conductivity type plug region.

Therefore, in the present invention, by controlling the back gate electrodes of the transistors of the first conductivity type and the second conductivity type formed in each of the well regions, it is possible to change the value voltage of the transistor. By reducing the off-current, low power consumption in the standby mode can be achieved, and a large drain-source current flows so that the second signal voltage level conversion circuit can operate at high speed. Operation and drive capability can be improved.

Further, in order to properly use the operation of the semiconductor integrated circuit device in the operation mode and the operation in the standby mode, the following semiconductor integrated circuit device is preferable.

(5) The first signal voltage level conversion circuit, wherein at least one of the third and fourth second conductivity type transistors has a channel length of the first and second second conductivity type transistors. And at least one channel width of the third and fourth transistors of the second conductivity type is The transistor is formed to be larger than the channel width of the first and second transistors of the second conductivity type, and at least one threshold voltage of the third and fourth transistors of the second conductivity type is: One of the first and second transistors of the second conductivity type, which is formed to have an absolute value lower than the threshold voltage.

(6) The substrate bias control circuit, wherein the first power supply and the third power supply, wherein the output signal of the first logic a path whose logic amplitude is defined is the first signal voltage level conversion circuit The back gate of the transistor of the second conductivity type, which is connected to the first conductive type p-type region of the other function module forming region, not to the region where the first logic circuit is formed, and constitutes the functional module The potential of the gate electrode is controlled.

(7) The substrate bias control circuit is a back gate of the first conductivity type transistor constituting the first logic circuit having a logic amplitude defined by the first power source and the third power source. The second electrode is connected to the second power supply or a fourth power supply having a higher potential than the second power supply.

(8) The board bias control circuit includes a back gate of the first conductivity type transistor that constitutes the first logic circuit whose logic amplitude is defined by the first power source and the third power source. A single electrode is connected to the first power supply having the same potential as the source electrode of the first conductivity type transistor.

(9) The second iS voltage level conversion circuit may be configured such that at least one of the third and fourth first conductivity type transistors has a channel length of the first and second first conductivity types. And the channel width of at least one of the third and fourth first conductivity type transistors is smaller than the channel length of the first and second first conductivity type transistors. And the threshold voltage of at least one of the third and fourth transistors of the first conductivity type is greater than the channel width of the first and second first conductivity types. It satisfies one of the following conditions: it is formed in absolute value lower than the threshold voltage of the transistor.

(10) The substrate bias control circuit comprises: a fourth power supply; and a second power supply, wherein the output signal of the second logic circuit whose logical amplitude is defined is the second signal. Voltage level Back-gate of the first conductivity type transistor that is connected to the second conductivity type peg region of the other function module formation region instead of the region where the second conversion circuit and the second logic circuit are formed, The potential of the electrode is controlled.

(11) The substrate bias control circuit includes a transistor of the second conductivity type that constitutes the second logic circuit having a logical amplitude defined by the fourth power supply and the second power supply. The back gate electrode is connected to the first power supply or a third power supply having an absolute value lower than that of the first power supply.

(12) The substrate bias control circuit is configured by the fourth power supply and the second power supply before a logic width is defined ^ the second conductivity type transistor constituting a second logic circuit. The battery terminal is connected to the second power source having the same potential as the source electrode of the second conductivity type transistor.

Therefore, the back gate electrode of the transistor can be controlled in the operation mode / standby mode by the output signal of the basic bias control circuit, and in the operation mode, the switching control of the transistor in the functional module can be performed at high speed. In addition, the drive capability can be improved, and the function module can be operated at high speed. In the standby mode, the off-state current of the transistor in the functional module can be reduced, so that the power consumption of the semiconductor integrated circuit device can be reduced.

Further, it is desirable that the semiconductor integrated circuit device of the present invention further has a circuit exemplified below.

(13) The substrate bias control circuit includes a first inversion logic circuit for waveform shaping, and the first signal output terminal or the second output terminal of the first signal voltage level conversion circuit has the waveform shaping control circuit. A human input terminal of the first inversion logic circuit is connected, an output terminal is connected to an input terminal of the first logic circuit, and a logic amplitude is defined by the first power supply and the third power supply; And a transistor of the first conductivity type formed under any one of a longer channel length, a smaller channel width, and a higher threshold voltage than the first conductivity type transistor constituting the first logic circuit. Including a first inversion logic circuit for waveform shaping.

(14) The first output terminal or the second output terminal of the second signal voltage level conversion circuit. An input terminal is connected to an input terminal, an output terminal is connected to an input terminal of the second logic circuit, a logic amplitude is defined by the fourth power supply and the second power supply, and the second logic circuit The second conductive type transistor formed under any of the following conditions: a longer channel length, a smaller channel width, and a higher threshold voltage than the second conductive type transistor. It has an inversion logic circuit.

Therefore, the output signal of the first signal voltage level conversion circuit can be once shaped and then buffered by the first logic circuit, so that the signal of the input signal to the first logic circuit can be The amplitude can be set to the first power supply and the third power supply, and the output signal of the second signal voltage level conversion circuit is once shaped and then buffered by the second logic circuit. Since the signal amplitude of the input signal to the second logic circuit can be used as the second power supply and the fourth power supply, it is possible to reduce the leak current in the device mode. it can.

Further, it is desirable that the first logic circuit and the second logic circuit are configured as follows.

(15) The first logic circuit or the second logic circuit is formed by connecting a logic circuit having a small driving ability formed on the input side and a logic circuit having a large driving ability formed on the output side. It is formed.

(16) The semiconductor integrated circuit device is formed on a substrate of a second conductivity type, and the first signal voltage level conversion circuit, the first logic circuit, or the first signal voltage level conversion circuit is provided. The first logic 冋 ¾, the first inversion logic circuit, the first signal voltage level conversion circuit, the first logic circuit, or the first signal voltage level conversion circuit, the first Logic circuit, not the area where the first inverted logic circuit is formed, but only the back gate electrode of the second conductivity type transistor formed in the first conductivity type pail area which is another functional module formation area Is controlled in potential.

(17) The semiconductor integrated circuit device is formed on a substrate of a first conductivity type, and the second signal voltage level conversion circuit, the second logic circuit, or the second signal voltage level conversion circuit, The second logic circuit, the second inverted logic circuit, the second signal voltage level conversion circuit, the second logic circuit or the second signal voltage level conversion circuit, the second logic Circuit, in the area where the second inverted logic circuit is formed However, only the back gate electrode of the first conductivity type transistor formed in the second conductivity type well region, which is another functional module formation region, is controlled in potential.

Therefore, waveform shaping is performed by the logic circuit formed on the input side, and the second conductivity type or the first conductivity type constituting the functional module is formed by the logic circuit formed on the output side and having a high driving power. A signal for controlling the back bias control voltage of the transistor can be formed with a large driving capability, and the charge / discharge current when switching between the operation mode and the standby mode can be reduced. Further, the outputs of the first logic circuit and the second logic circuit are the same as the output of the substrate bias control circuit, respectively, and the output signal of the substrate bias control circuit is the same as the output signal of the functional module. A two-conductivity-type transistor is formed and applied to the first-conductivity-type well that is electrically separated from the second-conductivity S1 substrate. The voltage of 2 can be applied to the back gate electrode of the transistor of the second conductivity type.

Further, the output iS ^ of the substrate bias control circuit is connected to a second conductivity type transistor in which a first conductivity type transistor constituting a functional module is formed and which is electrically separated from the first conductivity type substrate. In the operation mode / standby mode, the voltage of the second / fourth power supply can be applied to the second conduction type transistor.

It is desirable that the functional module of the present invention be configured as follows.

(18) A semiconductor integrated circuit device having a peripheral circuit including a function module forming area constituting a predetermined function module, and an input / output circuit forming area which interfaces input / output signals of the function module with an external device. A threshold voltage of a transistor provided in the peripheral circuit forming region is formed at a first threshold voltage, and a threshold voltage of a transistor provided in the functional module forming region is A second threshold voltage that is lower in absolute value than the first threshold voltage of the transistor provided in the region, and is provided in the functional module formation region by setting the functional module in a standby state. The potential of the back gate electrode of the selected transistor is controlled to be set to a third threshold voltage that is higher in absolute value than the second threshold voltage. (19) In a semiconductor integrated circuit device having a peripheral module including a functional module forming area constituting a predetermined functional module and an input / output circuit forming area for interfacing the input / output g of the functional module with an external device. The threshold voltage of a transistor provided in the functional module area and the input / output circuit forming area is formed at a first threshold voltage, and the functional module is set in a standby state, thereby achieving the function described above. The potential of the back gate electrode of the transistor provided in the module formation region is controlled and set to a second threshold voltage that is higher in absolute value than the first threshold voltage. Therefore, when the functional module is set in the standby state, the potential of the back gate electrode of the transistor formed in the functional module forming region is controlled, so that the speed of the functional module can be increased and the function can be achieved. Low power consumption of the module can be achieved.

The functional module of the present invention is laid out in the configuration exemplified below.

A semiconductor integrated circuit device according to the present invention includes a basic cell including a transistor of a first conductivity type and a transistor of a second conductivity type, and a matrix for configuring a predetermined functional circuit by changing wiring. Function module constituted by a plurality of the basic cell groups arranged in a matrix, and input / output cells for interfacing input / output signals with external devices arranged around the function module constituted by the basic cell group In a semiconductor integrated circuit device having a peripheral circuit including a group,

The power supplied to the plurality of basic cell groups is supplied by a first metal wiring layer and a second metal wiring layer that is higher than the first metal wiring layer,

In the first metal wiring layer extended in a channel length direction of the first and second conductive transistors, the second power supply and a first power supply having a lower potential than the second power supply. Supplying power to the basic cell group,

In the second metal wiring layer extended in the channel width direction of the first and second conductivity type transistors, a fourth power supply having the same or higher potential as the second power supply; A third power supply having the same potential or a low potential is supplied to the basic cell group.

Therefore, power can be efficiently supplied by using the first metal wiring layer and the second metal wiring layer. Further, the layout of the semiconductor integrated circuit of the present invention is desirably performed as exemplified below.

(20) Supplying the third power supply and the fourth power supply formed by the second metal wiring layer extending in the channel width direction of the first and second conductivity type transistors The power supply wiring is arranged and wired on the wiring grid in the channel width direction of the first and second conductivity type transistors and on the jewel electrode.

Therefore, the second metal wiring layer supplied with the third power supply and the fourth power supply is arranged and wired on the well electrode, so that the well electrode and the second metal wiring layer are connected to each other. Can be easily connected.

Further, the arrangement of the connection holes of the semiconductor integrated circuit device of the present invention is preferably performed as exemplified below.

Further, it is desirable that the semiconductor circuit device of the present invention further has the circuits listed below.

(21) The power supply of the fourth power from the second metal wiring layer to the second-conductivity-type well electrode of the first-conductivity-type transistor is performed using a connection hole or the connection hole and the first metal. The power supply of the third power supply to the first conductive type galvanic electrode of the second conductive type transistor by the second metal wiring layer is performed through a wiring layer, and the second power supply is performed through a connection hole or a connection hole and the first hole. This is performed via a metal wiring layer.

(22) The connection hole connected to the well electrode on which the first and second conductivity type transistors are formed is formed by the first metal wiring layer connected to and connected to the basic cell. And between the first power supply wiring and the second power supply wiring, and on a wiring grid adjacent to the first and second conductivity type transistors in the channel width direction. A connection hole for connecting a first electrode of the first conductivity type transistor to the first power supply line is disposed, and a connection hole is provided adjacent to the first and second conductivity type transistors in a channel width direction. A connection hole for connecting the jewel electrode of the transistor of the second conductivity type to the second power supply wiring is arranged on the wiring grid.

Therefore, by providing the connection hole, the third power supply and the fourth power supply supplied to the second metal wiring layer are connected to the connection hole or the connection hole and the third power supply. (1) The transistor of the first conductivity type and the second conductivity type can be supplied via the metal wiring layer to the well of the first conductivity type transistor and the first conductivity type transistor with respect to the first power supply wiring. The source potential of each of the second conductivity type transistors with respect to the second power supply wiring can be stabilized.

Further, in the semiconductor integrated circuit device of the present invention, it is desirable to control the jewel potential as exemplified below.

(23) In the case where the semiconductor integrated circuit device is formed on a substrate of the first conductivity type, the first power supply and the second power supply are used for the transistors of the first and second conductivity types. Only the power supply wiring supplied by the first metal wiring layer extended in the channel length direction and supplying the third power supply is extended in the channel width direction of the first and second conductivity type transistors. The first power supply and the second power supply are formed by the second metal wiring layer, or when the semiconductor integrated circuit device is formed on a substrate of a second conductivity type, Only the power supply wiring supplied by the first metal wiring layer extended in the channel length direction of the two-conductivity type transistor and supplying the fourth power supply is the channel of the first and second conductivity type transistors. Due to the second metal wiring layer extended in the width direction The first conductive type well on which the second conductive type transistor is formed or the second conductive type well on which the first conductive type transistor is formed is separated from the substrate of the semiconductor integrated circuit. You.

(24) Equipped with a basic cell composed of the first torsion-type transistor and the second torsion-type transistor, and arranged in a matrix to form a predetermined functional circuit by X-ray transformation. A semiconductor integrated circuit device comprising: a plurality of the basic cell groups; and a peripheral circuit including an input / output cell group arranged around the basic cell group and interfacing an external device and an input / output signal. The power supplied to the basic cell group is obtained by extending a second power and a first power having a lower potential than the second power in a channel length direction of the first and second conductive type transistors. And a fourth power supply having the same potential as the second power supply or a higher potential than the second power supply, and a fourth power supply having the same potential as the first power supply or having a higher potential than the second power supply. And a third power supply having a low potential, and a third power supply for assisting the first power supply. (1) an auxiliary power source and a second auxiliary power source for assisting the second power source are extended in a channel width direction of the first and second conductivity type transistors. A third auxiliary S source that is supplied in a second metal wiring layer above the first metal wiring layer and further assists the third power supply, and a fourth auxiliary power supply that assists the fourth power supply. Is extended in the channel length direction of the first and second conductivity type transistors, and is supplied in a third metal wiring layer that is more dusty than the second metal wiring layer.

(25) The first auxiliary power and the second auxiliary supplied by the second metal wiring layer formed to extend in the channel width direction of the first and second conductivity type transistors. The power source is connected to the first metal wiring layer to which the first power source and the second power source are supplied through a connection hole, and is connected to the first and second conductivity type transistors. The third auxiliary power supply and the fourth auxiliary power supply supplied by the third metal wiring layer extending in the channel i が direction are supplied by the third power supply and the fourth power supply through connection holes. Connected to the second metal wiring layer to be formed.

Therefore, the first and second voltages are applied to the source / drain electrodes of the transistors of the first conductivity type and the second conductivity type in the first metal distribution layer, and the substrate is The field of the first conductivity type electrically separates the well of the first conductivity type from the substrate of the first conductivity type, and connects the well of the first conductivity type to the well of the first conductivity type via the second metal wiring layer. Supplying the third power, and when the substrate is of the second conductivity type, electrically separates the second conductivity type substrate from the second conductivity type substrate; By supplying the fourth power supply to the cell via the second metal wiring layer, the potential of the cell as a back bias electrode of the PS transistor is changed in each case. Can be controlled. Further, using the first auxiliary power source, the second auxiliary power source, the third auxiliary power source, and the fourth auxiliary power source, each of the first conductivity type transistor and the second conductivity type transistor is used. The first power source, the second power source, the third power source, and the fourth power source in the electrodes of the first auxiliary power source, the second auxiliary power source, and the third auxiliary power source. The power supply and the fourth auxiliary power supply can be electrically connected to the basic cell group via a connection hole.

Further, it is desirable that the semiconductor integrated circuit device of the present invention is laid out as exemplified below.

(26) The third power supply, the fourth power supply, the first auxiliary power supply, and the second auxiliary power supply are extended in a channel width direction of the first and second conductivity type transistors. The power supply wiring and the auxiliary power supply wiring formed in the second metal wiring layer are supplied to the basic cell group, and the power supply wiring is provided in the channel width direction of the first and second conductivity type transistors. Wired and wired on the wiring grid and the well electrode.

Therefore, the first power source, the second power source, the third power source, and the fourth power source can be connected to the first and second conductors in the basic cell group without changing a library of arrangement and wiring. It is possible to lay out wiring to be supplied to the well of the type transistor, and to prevent a voltage drop at the center of the semiconductor integrated circuit device.

Furthermore, it is desirable that the semiconductor integrated circuit device of the present invention is configured to have a device structure as exemplified below.

(27) The semiconductor integrated circuit device is formed on a first conductive substrate, and the first power supply and the second power supply extend in a channel length direction of the first and second conductive type transistors. And only the fourth power source, the first auxiliary power source, and the second auxiliary power source extend in the channel width direction of the first and second conductivity type transistors. It is supplied by the feared second metal wiring layer, and only the fourth auxiliary power is supplied by the third metal wiring layer extending in the channel length direction of the first and second conductivity type transistors. Or the semiconductor integrated circuit device is formed on a substrate of a second conductivity type, and wherein the first power supply and the second power supply are channels of the transistors of the first and second conductivity types. The first metal wiring layer extended in the direction Only a third power supply, the first auxiliary power supply, and the second auxiliary power supply are supplied by the second metal wiring layer extending in a channel width direction of the first and second conductivity type transistors; Only the third auxiliary power is supplied by the third metal wiring layer extending in the channel length direction of the first and second conductivity type transistors, and the second conductivity type transistor is formed. The first conductive type well or the second conductive type well on which the first conductive type transistor is formed is electrically separated from the substrate of the semiconductor integrated circuit device.

Therefore, the first metal wiring layer supplies the first and second voltages to be applied to the source electrode / drain electrode of the transistors of the first conductivity type and the second conductivity type. In the case of the conductivity type, the first conductivity type well and the first conductivity type Electrically separating the substrate from the substrate, supplying the third power to the first conductivity type via the second metal wiring layer, and the second power supply when the substrate is the second conductivity type. The two-conductivity-type well and the second-conductivity-type substrate are physically separated from each other, and the second-conductivity-type well is separated from the second-conductivity-type well via the second metal wiring layer. In this case, it is possible to control the potential of the well as the back-bias electrode of the transistor of each conductivity type, and to prevent a voltage drop.

Further, the semiconductor integrated circuit device of the present invention preferably has the following functions.

(28) The third power supply and the fourth power supply, which are supplied by the second metal wiring layer extended in the channel width direction of the first and second conductivity type transistors, or The third power supply and the fourth power supply supplied by the second metal wiring layer, and a third metal wiring layer extending in a channel length direction of the first and second conductive type transistors The third auxiliary power supply and the fourth auxiliary power supply are provided by a chip which is manually operated by an external device, an enable signal, or a sleeve mode formed inside the external device or the semiconductor integrated circuit device. The control signal controls the potential of the functional module.

(29) The third power supply and the fourth power supply, which are supplied through the second metal wiring layer extending in the channel width direction of the first and second conductivity type transistors, or The third auxiliary power supply supplied in the third metal wiring layer extended in the channel length direction of the first and second conductivity type transistors, and the fourth auxiliary power supply are: Each power supply line or each auxiliary power supply line is separated for each functional module in the circuit device; the chip enable signal input from the external device, or the sleeve formed inside the external device or the semiconductor integrated circuit device · The mode control signal is input to one selector circuit.

Therefore, the potential control of all function modules or the unique potential control of each function module can be selected, and the chip enable signal and the sleep mode control signal can be used to select the potential in the operating state / standby state. The supply of the third power supply and the fourth power supply to the basic cell group can be controlled.

[Brief description of drawings]

FIG. 1 shows the substrate bias of the Νchannel M〇S transistor according to the first embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a control circuit.

FIG. 2 is a timing chart showing signal waveforms of various parts in the substrate bias control circuit of the N-channel MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a substrate bias control circuit of a P-channel MOS transistor according to the second embodiment of the present invention.

FIG. 4 is a timing chart showing a signal waveform of each part in the substrate bias control circuit of the P-channel MOS transistor according to the second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a substrate bias control circuit of an N-channel M〇S transistor according to a third embodiment of the present invention.

6 is a timing chart showing signal waveforms of various parts in the substrate bias control circuit of the N-channel MOS transistor according to the third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a substrate bias control circuit of a P-channel MOS transistor according to the fourth embodiment of the present invention.

FIG. 8 is a timing chart showing the fg signal waveform of each part in the substrate bias control circuit of the P-channel MOS transistor according to the fourth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a substrate bias control circuit of an N-channel MS transistor according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart showing signal waveforms of various parts in the substrate bias control circuit of the N-channel MOS transistor according to the fifth embodiment of the present invention.

FIG. 11 is a timing chart showing signal waveforms at various parts in the substrate bias control circuit of the P-channel MOS transistor according to the sixth embodiment of the present invention.

FIG. 12 is a timing chart showing signal waveforms at various parts in the substrate bias control circuit of the P-channel MOS transistor according to the sixth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a substrate bias control circuit for an N-channel MOS transistor according to a seventh embodiment of the present invention.

FIG. 14 is a timing chart showing a signal waveform of each part in the substrate bias control circuit of the N-channel MOS transistor according to the seventh embodiment of the present invention.

FIG. 15 is a timing chart showing signal waveforms at various parts in the substrate bias control circuit of the eight-channel MOS transistor according to the eighth embodiment of the present invention. FIG. 16 is a timing chart showing a signal waveform of each part in the substrate bias control circuit of the P-channel MOS transistor according to the eighth embodiment of the present invention.

FIG. 17 is a diagram schematically showing a chip layout of the ^ conductor integrated circuit device of the present invention.

FIG. 18 is a diagram showing a wiring layout of an inverter circuit according to a ninth embodiment of the present invention.

FIG. 19 is a diagram showing an inverter circuit according to the first embodiment and the ninth embodiment of the present invention.

FIG. 20 is a diagram showing the wiring layout of the NAND circuit of the tenth embodiment of the present invention.

FIG. 21 is a diagram showing a circuit of the NAND circuit of the tenth embodiment of the present invention. FIG. 22 is a diagram showing a wiring layout of the NOR circuit in the first column of the eleventh embodiment of the present invention.

FIG. 23 is a diagram showing a circuit of the NOR circuit according to the eleventh embodiment of the present invention.

FIG. 24 is a diagram showing the wiring layout of the RAM circuit according to the 12th embodiment of the present invention.

FIG. 25 is a diagram schematically showing a RAM circuit according to the 12th embodiment of the present invention.

FIG. 26 is a diagram for explaining a method of controlling all functional modules by the substrate bias control circuit in the semiconductor integrated circuit device according to the thirteenth embodiment of the present invention.

FIG. 27 is a cross-sectional view of a MOS transistor constituting a functional module when controlling all functional modules by the substrate bias control circuit in the semiconductor integrated circuit device of the thirteenth embodiment of the present invention.

FIG. 28 is a diagram for explaining a method of controlling some functional modules by the substrate bias control circuit in the semiconductor integrated circuit device according to the fourteenth embodiment of the present invention, and an M〇S transistor constituting the functional module. FIG.

FIG. 29 is a diagram showing a layout of power supply wiring and ground wiring in the semiconductor integrated circuit device according to the fifteenth embodiment of the present invention.

FIG. 30 is a diagram schematically showing a chip layout of the semiconductor integrated circuit device according to the sixteenth and fifteenth embodiments of the present invention. FIG. 31 is a diagram schematically showing a chip layout of a conventional semiconductor integrated circuit device.

FIG. 32 shows the subthreshold region characteristics of the drain-source current with respect to the gate voltage in the MOS transistor for explaining the present invention, and (a) shows the characteristics of the N-channel MOS transistor. It is a characteristic diagram, and (b) is a characteristic diagram which shows the characteristic of a P-channel M0S transistor.

FIG. 33 is a diagram showing a wiring layout of an inverter circuit in a conventional semiconductor integrated circuit device.

FIG. 34 is a diagram showing a circuit of an inverter circuit in a conventional semiconductor integrated circuit device.

FIG. 35 is a circuit diagram showing a conventional substrate bias control circuit.

FIG. 36 is a timing chart showing signal waveforms of various parts of the substrate bias control section of the N-channel MOS transistor in the conventional board bias control circuit.

FIG. 37 is a timing chart showing signal waveforms of various parts of the substrate bias control unit of the P-channel MOS transistor in the conventional substrate bias control circuit.

[Best Mode for Carrying Out the Invention]

Embodiments of a substrate bias control circuit and a semiconductor integrated circuit device having the substrate bias control circuit according to the present invention will be described with reference to the accompanying drawings.

FIG. 17 is a schematic diagram of a chip layout showing one embodiment of the semiconductor integrated circuit device according to the present invention. The semiconductor integrated circuit shown in FIG. 17 will be described as, for example, a master slice type semiconductor integrated circuit device. The semiconductor integrated circuit device of the present invention includes a functional module MO, a peripheral circuit 10, and the like formed on a single silicon substrate. In the functional module M0 in the figure, a basic cell row composed of the basic units described above is formed, and although not particularly shown, wiring connection between the basic cells is performed in the second metal wiring layer. It is what is done. The peripheral circuit 10 includes an input / output control circuit and the like, and a substrate bias control circuit BB and the like for performing a back bias control on the function block are also mounted on the chip. The substrate bias control circuit BB is not arranged in the functional module forming area M0, but is arranged in the peripheral circuit forming area 10 at, for example, a corner of a chip. That is, the substrate bias control circuit By arranging the paths BB at the corners of the chip, in a semiconductor integrated circuit device such as a gate array, the chip layout can be efficiently configured by using the empty area of the chip.

Next, the substrate bias control circuit of the present embodiment will be described. FIG. 1 shows a substrate bias control circuit for NMOS according to a first embodiment of the present invention, and FIG. 2 shows a timing chart showing signal waveforms of various parts. Hereinafter, the substrate bias control circuit for NMOS according to the present invention will be described with reference to FIGS.

The S-plate bias control circuit shown in FIG. 1 includes a first signal voltage level conversion circuit (block A 1) and a first buffer logic circuit (block A 2). If the power supply voltage is low from the outside of the circuit device, the power supply voltage Vddl + 2 V, the ground voltage Vss1 = ± 0 V, and the ground voltage Vss2 =-2 V is newly supplied to the NMOS P-well. Have been. The switching between the operation mode and the standby mode is performed, for example, by a chip enable signal CE, a sleeve mode control signal SM, whose logic amplitude is defined by the power supply voltage Vd 1 = + 2 V and the ground voltage Vss 1 = ± 0 V. This is done by one of the power down signals PD. The power-down signal PD, the sleeve 'mode control signal SM is an i signal for instructing whether or not to activate the functional module, and is provided in advance for each product to which the substrate bias control circuit of the present invention is applied. Using the signal, any of the chip enable signal CE, the no-down signal ^ PD, the sleep mode control signal SM, and the signal having the above function can be used.

Next, the operation of the substrate bias control circuit shown in FIG. 1 will be described using the timing chart of FIG. When the chip enable signal CE is set to the high level, the function module in the semiconductor integrated circuit device is set to the operation mode, and the inverted signal CE (bar) is set to the single level. Therefore, the PMO SQ 18 of the first signal voltage level conversion circuit (block A 1) is turned on, and the potential of the line V 2 changes to +2 V, so that the PMC SQ 22 is also turned on. The potential of the line V4 also changes to + 2V. The potential of the line V 6 rises through the NMO SQ 25 and the above-mentioned PM〇 SQ 18 and Q 22 in the on state, and the potential of the line V 6 becomes 0 V—Vth (Vth: MO NMO SQ25 is turned off when the threshold voltage (SQ25 threshold voltage) is reached.

When the potential of the line V 6 reaches 0 V−Vth (Vth: threshold voltage of the NMO SQ 25), the NMO SQ 19 is turned on, and the potential of the line V 5 changes to 12 V. . When the potential of the line V5 changes to 12 V, the NMOS Q21 is turned off and the NMO SQ 23 is turned on, so that the potential of the line V3 changes to 12V.

Further, since the chip enable signal CE is set to the high level, the PMO SQ 16 is turned off, and the potential of the line V 1 is ± 0 V + Vth (Vth: PM 0 SQ 20 Ii iifl ti pressure), the PMO SQ 2◦ is turned off. Further, the potential from the output terminal of the first voltage level conversion circuit (block A 1), that is, the potential of the line V6, is used to control the PMO SQ 24 which constitutes the first buffer logic circuit (block A 2). And input to the respective gate electrodes of the inverter circuit composed of NMOSQ27. Here, the first buffer logic circuit (block A 2) is an interface circuit between the first signal voltage level conversion circuit (block A 1) and the P-well in all functional modules, and the entire chip It becomes a driving circuit for charging and discharging performed on the P-well. Therefore, since the load capacity of the driving current becomes large, the channel width of the first-stage inverter circuit is formed small to perform waveform shaping, and the channel width of the next-stage inverter circuit is formed large to shorten the charge / discharge time. It is desirable to make it shorter.

Then, the PMO S Q 24 is turned off and the NMO S Q 27 is turned on, so that the potential of the line V 7 changes to 12 V. The output signal of this inverter circuit, that is, the potential of the line V7 is input to each gate electrode of the inverter circuit consisting of PMO SQ26 and NM〇SQ29, whereby the PMO SQ 26 is turned on, and the NI OSQ 29 is turned off. In this way, a potential of voltage Vpw = ± 0 V is applied to the P-well of the NMOS formed in the functional module in the semiconductor integrated circuit device.

V is applied to the PMO of the NMOS formed in the functional module in the semiconductor integrated circuit device. _When a potential of _pw = ± 0 V is applied, for example, in the NM SQ 1 constituting the inverter circuit INV 1 in the functional module shown in FIGS. 19 (a) and 19 (b), the source electrode The ground voltage Vss 1 (± 0 V) and the voltage Vpw (0 V earth) to the back gate electrode. Therefore, the gate electrode and the source electrode are set to the same potential, and the state N 1 (threshold voltage = about +0.3 V) and the state N 2 (threshold voltage = about + 0.5 V) and state N 3 (threshold voltage = about +0.7 V), so that the threshold voltage is lowered and the drain-source current is increased. You. This shows similar characteristics for other logic circuits, latch circuits, multipliers, and other circuits constituting the functional module in the semiconductor integrated circuit device.

Next, by setting the chip enable signal CE to a low level, the function module in the semiconductor integrated circuit concealment is set to the standby mode.

Then, as shown in FIGS. 1 and 2, the PMO SQ 16 of the first signal voltage level conversion circuit (block A 1) is turned on, and the potential of the line V 1 changes to +2 V. Therefore, PM〇SQ 20 is also turned on, and the potential of the line V 3 also changes to +2 V.

Regarding the potential of the line V5, the potential is increased via the PMO SQ23 and the above-mentioned ON state PM0SQ16, Q20! : When the potential of line V5 reaches ± 0 V—Vth (Vth: threshold voltage of NMOS Q23), NMOSQ23 is turned off. When the it position of the line V5 reaches 0 V—Vth (Vth: threshold voltage of NM0SQ23), the NMO SQ21 is turned on, and the potential of the line V6 changes to 12V. I do. When the potential of the line V6 changes to 12 V, the NM0 SQ19 is turned off and the NMOS Q25 is turned on, so that the potential of the line V4 changes to -2V. .

Further, since the inverted signal CE (bar) of the chip enable signal CE is set to a high level, the PMO SQ 18 is turned off, and the potential of the line V 2 is changed to V + Vth (Vth: PMO (The threshold voltage of SQ22), the PMO SQ22 is turned off.

The potential of the output terminal of this first signal voltage level conversion circuit (block A 1) That is, when the potential of the line V6 is input to each gate electrode of the inverter circuit comprising the PMOSQ 24 and the NMOSQ 27 constituting the first buffer logic circuit (block A2), the PM〇SQ Since 24 is turned on and NMOS Q27 is turned off, the potential of line V7 changes to 0V.

When the potential of the line V7 is input to each gate electrode of the inverter circuit composed of the PMOS Q26 and the NMO SQ29, the PMO SQ26 is turned off and the NMO SQ29 is turned on. As a result, the potential Vpw 2 V is applied to the P-well of the NMOS formed in the functional module in the semiconductor integrated circuit device. When a potential of Vpw = −2 V is applied to the P-well of the NMOS formed in the functional module in the semiconductor integrated circuit device, for example, as shown in FIGS. 19 (a) and 19 (b). In the NMO SQ 1 that constitutes the inverter circuit I NV 1 in the functional module, the ground voltage Vss 1 (± 0 V) is applied to the source electrode, and the voltage Vpw (-2 V) is applied to the back gate electrode. You. As a result, the potential of the back gate electrode becomes lower than the potential of the source electrode, and is shifted by NA as shown in Fig. 32 ^ a) N 3 (threshold voltage = about +0.7 V) and shifted by NB State N 4 (threshold voltage = approx. +0.9 V), and only NC shifts to N 5 (threshold voltage-approx. + 1. IV). Therefore, the threshold voltage of the MOS transistor is increased, and the off-state current is extremely reduced. This shows the same characteristics for other logic circuits, such as a lasing circuit and a multiplier, which constitute the functional modules in the conductor integrated circuit device.

Therefore, in the operation mode, the back gate electrode and the source electrode of the NMOS constituting the functional module in the semiconductor integrated circuit device are set to the same potential, so that the threshold voltage of the NMOS is lowered. In the operation mode by controlling the potential of the back gate electrode of the NMOS, more drain-source current flows, and the speed of the switch control of the MOS transistor constituting the functional module can be increased, and the drive can be performed at the same time. Ability can be improved.

In the standby mode, the potential of the back gate electrode of the NMOS constituting the functional module in the semiconductor integrated circuit device is set lower than the potential of the source electrode, and the threshold voltage is set higher. And the potential of the back gate electrode of the NMOS In the standby mode, the off-state current is further reduced in the standby mode, so that the standby current of the active module can be reduced significantly.

As described above, the substrate bias control circuit of the first embodiment makes it possible to realize both high speed in the operation mode and low power consumption in the standby mode. In the first signal-voltage level conversion circuit (block A 1), the current path that constantly flows between the power supplies can be eliminated, and the mode is switched from the operation mode to the standby mode and from the standby mode to the operation mode. The subsequent standby current can be made very small.

Further, the substrate bias control circuit of the first embodiment enables high-speed charging and discharging of the function module from the substrate bias control circuit, and the mode from the operation mode to the standby mode or from the standby mode to the operation mode. Changes can be made at high speed. FIG. 1 shows an example in which the first buffer logic circuit (block A 2) is formed by two inverters. However, the present invention is not limited to this. It can be configured by In FIG. 1, the first buffer logic circuit (block A 2) is described as an interface between the first signal voltage level conversion circuit and the functional module. According to the specifications described above, the first buffer logic circuit (block A 2) need not be provided unless it is necessary to particularly consider the speed in the mode change as described above. Incidentally, the first buffer logic circuit (block A2) can be constituted by another logic circuit such as an inverter circuit, a NAND circuit, a NOR circuit and the like.

Further, the substrate bias control circuit of the first embodiment is designed so that a high-voltage stress is not applied to each MOS transistor constituting the circuit. That is, the operating voltage is 3 V, the voltage is designed to be 3.3 V between the gate and the source, and the voltage margin is ± 10%. Therefore, the voltage between the gate source, the gate drain, and the voltage between the gate and the well are formed to be 3.6 V or less, respectively, so that the gate oxide film of each MOS transistor constituting the substrate bias control circuit is particularly required. It can be formed without thickening. Therefore, in the substrate bias control circuit of the present embodiment, all the MOS transistors can be formed by the gate oxide film having the same thickness, and thus can be formed by an easy process. The long-term reliability of the gate oxide film of the MOS transistor can be improved, the reliability of the semiconductor integrated circuit device can be improved, and the thickness of the gate oxide film corresponding to high integration can be reduced. Can respond.

Further, in the first embodiment, the first plate voltage control circuit (block A 1) uses the PMO SQ 16, Q 18, Q 20, and Q 22 within the N-level of the same area. The N-well may be supplied to the power supply voltage Vdd2 (for example, +4 V) of the second embodiment described later. Therefore, the ethics circuit (block B 2) of PMO SQ 30, Q 32, Q 34, Q 36, and 2 constituting the second signal voltage level conversion circuit (block B 1) of the second embodiment described later is used. The layout area can be reduced because it can be formed in the same N-level region as the PMO SQ 38 and Q 40 constituting the second inverter circuit (block B3) of the fourth embodiment and the PM〇SQ 42 constituting the fourth embodiment. You can do it. By forming the NMO SQ23, Q25 of the first signal voltage level conversion circuit (block A1) in an independent P-well region, in particular, the potential of the back gate electrode can be controlled. Since the gate electrode and the source electrode have the same potential, the threshold voltage is reduced, and a large drain-source current flows, so that the first signal voltage level conversion circuit (block A 1) can operate at high speed. At the same time, the drive capacity can be improved.

The substrate bias control circuit for NM〇S according to the first embodiment includes a new NM〇S separately from the power supply voltage Vddl (for example, +2 V) and the ground voltage Vssl (for example, ± 0 V) from outside the semiconductor integrated circuit device. Although the ground voltage Vss2 (for example, 12 V) is supplied for the P-well, it is also possible to configure a charge pump circuit based on a ring oscillator in the semiconductor integrated circuit device to generate a negative potential instead. it can. However, in this case, the voltage supply is unstable, and the power consumption is inferior to the substrate bias control circuit shown in FIG.

Further, by using the substrate bias control circuit, it is possible to self-correct the variation of the threshold voltage of the semiconductor integrated circuit device. As described above, the threshold voltage of a MOS transistor has an error of about 10% in manufacturing. However, in order to reduce the power supply voltage in recent years, the charge pump, the leakage current detection circuit, and the Using the substrate bias control circuit of the embodiment, the power supply wiring connected to the back gate electrode during operation is By controlling, the threshold pressure can be compensated.

FIG. 3 shows a substrate bias control circuit for a PMOS according to a second embodiment of the present invention, and FIG. 4 shows a timing chart showing signal waveforms of various parts.

The substrate bias control circuit shown in FIG. 3 includes a second signal voltage level conversion circuit (block B 1) and a second buffer logic circuit (block B 2). Then, the power supply voltage Vdd 1 = +2 V, the ground voltage Vssl = ± 0 V, and the power supply voltage Vdd2 = +4 V, for example, are newly supplied to the PMOS N-level from outside the conductor integrated circuit device. You. The switching of the tjl between the operation mode and the standby mode is performed, for example, by using a chip される enable signal C whose logic width is defined by the power supply voltage V dd 1 = 12 V and the ground voltage V ss 1 = ± 0 V. ,, sleep 'mode control signal SΜ, power down signal ΡD. Power down signal PD, sleeve-mode control signal SM is a signal that instructs whether to activate a functional module or not, and is a signal that is provided in advance for each product to which the described substrate bias control circuit is applied. , The chip enable signal CE, the power down signal PD, the sleep mode control signal SM, or any of the signals having the above functions can be used.

Next, the operation of the substrate bias control circuit shown in FIG. 3 will be described using a timing chart shown in FIG.

When the chip enable signal CE is set to the high level, the functional module of the semiconductor integrated circuit device is set to the operation mode. Then, the NMO SQ 33 of the second signal voltage level conversion circuit (block B 1) is turned on, and since the potential of the line V1 changes to 0 V, the NMO SQ 37 is also turned on. The potential of line V3 also changes to 0V.

Then, the potential of the line V5 decreases through the PMO SQ34 and the NMO SQ33 and Q37 which are in the above-mentioned ON state, and the potential of the line V5 becomes +2 V + Vth (Vth: PMO SQ 34, the PMO SQ 34 is turned off. When the potential of the line V5 reaches + 2V + Vth (Vth: threshold voltage of the PMO SQ34), the PMO SQ32 is turned on, and the potential of the line V6 changes to + 4V. Since the potential of the line V6 changes to +4 V, the PMOS Q30 is turned off, and the PM0SQ36 is turned on. Changes to

Further, since the inverted signal CE (bar) of the chip enable signal CE is set to low level, the NMO SQ 35 is turned off, and the potential of the line V 2 becomes +2 V−Vth ( Vth: threshold voltage of NMO SQ 39), so that NMO SQ 39 is turned off.

Then, the potential of the output terminal of the second signal voltage level conversion circuit (block B 1), that is, the potential of the line V 5, is connected to the PMO SQ 38 constituting the second buffer logic circuit (block B 2). Input to each gate terminal of the inverter circuit composed of NMO S Q41. Here, the second buffer logic circuit (block B 2) is an interface circuit between the second signal voltage level conversion circuit (block B 1) and the N-level in all functional modules, It is a drive circuit for charging and discharging the N-well of the entire chip. Therefore, since the load capacity of the drive current becomes large, the channel width of the first-stage inverter circuit is made small to perform waveform shaping, and the channel width of the next-stage inverter circuit is made large to charge and discharge. It is desirable to shorten the time.

Then, since the PMO S Q 38 is turned on and the NM〇S Q 41 is turned off, the potential of the line V 7 changes to +4 V. When the potential of the output signal, that is, the potential of the line V7 is input to each gate electrode of the inverter circuit composed of the PMO SQ40 and the NMO SQ43, the PMO SQ40 is turned off, and the NMO SQ43 is turned off. It is turned on. Therefore, the potential Vnw = + 2 V is applied to the N-well of the PMOS formed in the functional module in the semiconductor integrated circuit device.

When a potential of Vnw = + 2 V is applied to the N-well of a PMOS formed in a functional module in a semiconductor integrated circuit device, for example, as shown in FIGS. 19 (a) and 19 (b) In the PMO SQ 2 that constitutes the inverter circuit INV 1 in the function module, the power supply voltage Vdd 1 (+ 2 V) is applied to the source electrode, and the voltage V is applied to the back gate electrode. n (+2 V) is applied. For this reason, the back gate electrode and the source electrode are set to the same potential, and the state P 1 (threshold voltage = about --0.3 V) and the state P 2 (threshold voltage-about 0.5 V) shown in FIG. ), State P 3 (threshold voltage is about 0.7 V), so the threshold voltage is low in absolute value and the drain current is large in absolute value. Flows. This shows similar characteristics for other logic circuits, latch circuits, multipliers, and other circuits that constitute functional modules in the semiconductor integrated circuit device.

Next, as shown in FIGS. 3 and 4, when the chip enable signal CE is set to the low level, the functional module in the semiconductor integrated circuit device is set to the standby mode. The inverted signal CE (bar) of the chip enable signal CE is set to high level. Accordingly, the NM〇SQ 35 of the second signal voltage level conversion circuit (block # 1) is turned on, and the potential of the line V2 changes to ± 0 V, so that the NMOS Q39 is also turned on and the line The potential of V4 also changes to ± 0V. The potential of the line V 6 drops through the PMO SQ 36 and the above-mentioned ON state Ν 0 SQ 35 and Q 39, and the potential of the line V 6 becomes +2 V + Vth (Vth: PM OSQ When the potential of the line V 6 reaches +2 V + Vth (Vth: threshold voltage of the PMO SQ 36), the PMO SQ 30 is turned off. The transistor is turned on, and the potential of the line V5 changes to + 4V. When the potential at the line V5 changes to + 4V, the PMOS Q32 is turned off and the PMOS Q34 is turned on, so that the potential of the line V3 changes to + 4V.

Further, since the chip enable signal CE is set to the mouth level, the NMO SQ 33 is turned off, and the potential of the line V 1 is +2 V—Vth (Vth: NM OS Q 37 NMO Q 37 is turned off. The potential of the output terminal of the second signal voltage level conversion circuit (block B 1), that is, the potential of the line V 5 is equal to the potential of the PMO SQ 38 and the NMOS constituting the second buffer logic circuit (block B 2). PMO SQ 38 is turned off and NMOS Q41 is turned on by input to each gate electrode of the inverter circuit consisting of Q41. Therefore, the potential of the line V7 changes to +2 V.

When the output signal potential, that is, the potential of the line V7, is input to each gate electrode of the inverter circuit composed of the PMO SQ 40 and the NMO SQ 43, the PMOS Q 40 is turned on and the NMO SQ 43 is turned off. You. Therefore, a potential of voltage Vnw = + 4 V is applied to the N-well of PM0S formed in the functional module in the semiconductor integrated circuit device.

When a potential of Vnw = + 4 V is applied to the N-well of the PMOS formed in the functional module in the semiconductor integrated circuit device, for example, as shown in FIGS. 19 (a) and 19 (b) In the PMO SQ 2 configuring the inverter circuit INV 1 in the functional module, the power supply voltage Vdd 1 (+2 V) is applied to the source electrode, and the voltage Vn (+4 V) is applied to the back gate electrode. For this reason, the potential of the back gate electrode becomes higher than the potential of the source electrode, and only the PA shown in FIG. 32 (b) is shifted by P3 (reference value: pressure-about -0.7 V), PB The threshold value changes to either P4 (threshold voltage = approx.0.9V) or PC5 (threshold voltage = approx. 1.IV). The voltage is made high in absolute value, and the off-current is made very small in absolute value. This shows similar characteristics for other logic circuits, latch circuits, multipliers, and other circuits that constitute functional modules in the semiconductor integrated circuit device.

Therefore, in the operation mode, since the back gate electrode and the source electrode of the PMOS constituting the functional module in the semiconductor integrated circuit device are set to the same potential, the threshold voltage of the PMOS is reduced in absolute value, and The drain and source currents are made to flow in absolute values. Further, by controlling the potential of the back gate electrode of the PMOS, the switching control of the MOS transistor constituting the functional module in the operation mode can be speeded up, and the driving capability can be improved.

In the standby mode, the potential of the back gate electrode of the PMOS constituting the functional module in the semiconductor integrated circuit device is higher than the potential of the source electrode, the threshold voltage is increased in absolute value, and The off current is made very small in absolute value. By controlling the potential of the back gate electrode of the PMOS, the standby current of the functional module in the standby mode can be extremely reduced. As described above, the substrate bias control circuit of the second embodiment can realize both high speed operation in the operation mode and low power consumption in the standby mode, and also constitutes the substrate bias control circuit. In the second signal voltage level conversion circuit (block B 1), there is no current path flowing constantly between the power supply, so after switching from the operation mode to the standby mode and from the The standby current after switching to the operation mode can be made very small.

Furthermore, the substrate bias control circuit of the second embodiment enables high-speed charging and discharging of the function module from the substrate bias control circuit, and changes the mode from the operation mode to the standby mode or from the standby mode to the operation mode. It can be performed at high speed. Ai, Fig. 3 shows an example in which the second buffer logic circuit (block B 2) is formed by two invertors. Self-loaded force. It is not limited to this, and is composed of a desired number of inverters. be able to. Ai, FIG. 3 describes the second buffer logic circuit (block B 2) as an interface between the second f-voltage level conversion circuit and the functional module. A product to which this substrate bias control circuit is applied According to the above specification, the second buffer logic circuit (block B 2) need not be provided unless it is necessary to particularly consider the speed in the mode change as described above. Incidentally, the second buffer logic circuit (block B2) can be constituted by another logic circuit such as an inverter circuit, a NAND circuit, a NOR circuit and the like.

Further, the substrate bias control circuit of the second embodiment is designed so that a high-voltage stress is not applied to each MOS transistor constituting the circuit. That is, the operating voltage is 3 V, the voltage is designed to be 3.3 V between the gate sources, and the voltage margin is ± 10%. Therefore, the voltage between the gate and the source, the voltage between the gate and the drain, and the voltage between the gate and the well are formed to be 3.6 V or less, respectively, so that the gate of each MOS transistor constituting the substrate bias control circuit is formed. The oxide film can be formed without particularly increasing the thickness. Therefore, according to the substrate bias control circuit of the present embodiment, the MOS transistors forming the functional module and the MOS transistors forming the peripheral circuit can be formed on the chip with the gate oxide films having the same thickness. Therefore, it can be formed by an easy process and improves the long-term reliability of the gate oxide film of the MOS transistor. Therefore, the reliability of the semiconductor integrated circuit device can be improved, and the thickness of the gate oxide film corresponding to high integration can be reduced.

Further, the second signal voltage level conversion circuit forms NMO SQ33, Q35, Q37, and Q39 in the P-well of the same area, and connects this N-well to the ground voltage Vss2 of the first embodiment. (For example, −2 V), the N MO SQ 19, Q 21, Q 23, Q 25 and the first signal voltage level conversion circuit (block A 1) of the first embodiment constitute a first signal voltage level conversion circuit (block A 1). NMO SQ27, Q29 constituting the first buffer logic circuit (block A2) or PMO SQ31 constituting the first receiver circuit (block A3) of the third embodiment described later. Since they can be formed in the same P-well region, the layout area can be reduced. In particular, by forming the PMO SQ 34 and Q 36 in the second signal voltage level conversion circuit (block B 1) in independent N-well regions, the back gate electrode and the source electrode can have the same potential. As a result, the threshold voltage can be reduced in absolute value, and the drain-source current can flow in absolute value, so that the second signal voltage level conversion circuit (block B 1) can operate at high speed and have the driving capability. Can be improved. The substrate bias control circuit for the PMOS according to the second embodiment is newly provided with a NPM of the PMOS separately from the external power supply voltage Vddl (for example, +2 V) and the ground voltage Vssl (for example, ± 0 V) from the outside of the semiconductor integrated circuit device. Although the power supply voltage Vdd2 (for example, + 4V) is supplied to the well, a charge pump circuit based on a ring oscillator may be formed in the semiconductor integrated circuit device instead to generate a positive potential. However, in this case, the voltage supply is unstable, and the power consumption is inferior to that of the substrate bias control circuit shown in FIG.

Further, by using the substrate bias control circuit, it is possible to self-correct the variation of the threshold voltage of the semiconductor integrated circuit device. As described above, the threshold voltage of the MOS transistor has an error of about 10% in manufacturing. However, in order to reduce the power supply voltage in recent years, the charge pump, the leak current detection circuit, and the The threshold voltage can be compensated by controlling the power supply wiring connected to the back gate electrode during operation by using the substrate bias control circuit of the present embodiment. <Third embodiment>

FIG. 5 shows a substrate bias control circuit for NMOS according to a third embodiment of the present invention. The substrate bias control circuit according to the present embodiment includes a first buffer logic circuit between the first signal voltage level conversion circuit (block A 1) and the first buffer logic circuit (block A 2) shown in FIG. The first circuit for waveform shaping configured using a PMOS formed by any one of a longer channel length, a smaller channel width, and a higher threshold voltage than the PMOS constituting the circuit (block A2) The configuration is the same as that of the above-mentioned circuit (block A3). The circuit operation in the substrate bias control circuit of the third embodiment is shown in the timing chart of the signal waveforms of each part in FIG. 6, but the circuit operation is the same as that of the substrate bias control circuit of the first embodiment. The same reference numerals are given, and the description of the contents described in the first embodiment and the corresponding effects will not be repeated. In addition, by adding the first inverter circuit (block A3), the output terminal of the first signal voltage level conversion circuit (block A1) is an inverted signal of the potential of the line V6. The connection is changed to line V5.

The substrate bias control S path of the third embodiment is a circuit for further reducing the power consumption of the substrate bias control path for NMOS described in the first embodiment. That is, in the substrate bias control circuit shown in FIG. 1, the high potential of the line V5, which is the potential of the output terminal of the first signal voltage level conversion circuit (block A1), is ± 0 V—Vth (Vth: MO Therefore, the PMO SQ 24 that configures the buffer logic circuit (block A 2) is not completely turned off. Here, the first buffer logic circuit (block A 2) is an interface circuit between the first signal voltage level conversion circuit (block A 1) and a P-well in all functional modules, and the entire chip This is a driving circuit for charging and discharging performed on the P-well. Therefore, since the load capacity of the drive current becomes large, the channel width of the first-stage inverter circuit is made small to perform waveform shaping, and the channel width of the next-stage inverter circuit is made large to fill. Make the discharge time shorter.

However, in the substrate bias control circuit of the present embodiment, the first waveform shaping for minimizing the leak current flowing from the ground wiring layer Vssl to the ground wiring layer Vss2 is performed. The inverter circuit (block A3) has been added. That is, the potential of the output signal from the first signal voltage level conversion circuit (block A 1), that is, the potential of the line V5 also drops by the threshold value of NMOS. The first inverter circuit (block A3) for waveform shaping for full amplitude is configured between the first voltage level conversion circuit (block A1) and the first buffer logic circuit (block A2). Things. The PMOS constituting the first inverter circuit (block A3) has a longer channel より, a smaller channel width, and a higher | より than the PMOS constituting the first buffer logic circuit (block A2). Since the PM〇S formed by either of the voltage methods is used, the leakage current is extremely small.

Also, the change of the channel length and channel width of the PMOS can be easily changed by mask design, and the PMOS having a high threshold value does not need to change the channel and the dose S: in the semiconductor process. In other words, the back gate electrode of PMO SQ 26 constituting the first buffer logic circuit (block A 2) is connected to the power supply voltage Vddl (+2 V) higher than the source potential of PMO SQ 26 or shown in FIG. By connecting to the power supply voltage Vdd2 (+4 V), the threshold voltage can be easily increased.

Further, the substrate by-mass control circuit of the third embodiment enables high-speed charging and discharging of the function module from the substrate bias control circuit, and the mode from the operation mode to the standby mode or from the standby mode to the operation mode. The transition can be performed at high speed. FIG. 5 shows an example in which the first buffer logic circuit (block A2) is formed by two invars. However, the present invention is not limited to this. Can be configured. In FIG. 5, the first buffer logic circuit (block A2) is described as an interface between the first signal voltage level conversion circuit and the functional module, but this substrate bias control circuit is applied. If it is not necessary to particularly consider the speed in the mode change described above depending on the specifications of the product to be used, the first buffer logic circuit (block A2) may not be provided. Note that the first buffer logic circuit (block A2) can be constituted by another logic circuit such as an inverter circuit, a NAND circuit, and a NOR circuit. Further, the substrate bias control circuit of the third embodiment is designed so that a high-voltage stress is not applied to each MOS transistor constituting the circuit. In other words, the operating voltage is 3V, the design is such that a 3.3V voltage is applied between the gate and the source, and the voltage margin is ± 10%. Therefore, since the voltage between the gate and the source, between the gate and the drain, and between the gate and the well are formed to be 3.6 V or less, respectively, the gate oxidation of each M〇S transistor constituting the substrate bias control circuit is performed. It can be formed without making the film particularly thick. Therefore, according to the substrate bias control circuit of the present embodiment, on the chip, the MOS transistor forming the functional module and the MOS transistor forming the peripheral circuit are formed of gate oxide films having the same thickness. Therefore, it can be formed by an easy process, the long-term reliability of the gate oxide film of the MOS transistor can be improved, and the reliability of the semiconductor integrated circuit device can be improved. In addition, it is possible to cope with the increase in the thickness of the gate oxide film corresponding to high integration.

The substrate bias control circuit for the NMOS according to the third embodiment includes a new PMOS of the NMOS separately from the power supply voltage Vddl (for example, +2 V) and the ground voltage Vssl (for example, ± 0 V) from outside the semiconductor integrated circuit device. The ground voltage Vss2 (for example, 12 V) is supplied for the gel, but a charge pump based on a ring oscillator can be configured in the semiconductor integrated circuit device instead, and a negative potential can be generated. . However, in this case, the voltage supply is unstable, and the power consumption is inferior to the substrate bias control circuit shown in FIG.

Further, by using the substrate bias control circuit, it is possible to self-correct the variation of the threshold voltage of the semiconductor integrated circuit device. As described above, the threshold voltage of the MOS transistor has an error of about 10% in manufacturing. However, in recent years, the problem of lowering the power supply voltage has been solved. By controlling the power supply wiring connected to the bus and the sockgate electrode during operation using the substrate bias control circuit of the embodiment, the threshold pressure can be compensated.

Fourth embodiment>

FIG. 7 shows a substrate bias control circuit for PM 0 S according to the fourth embodiment of the present invention. Is shown. The substrate bias control circuit of the present embodiment includes a second buffer between the second signal voltage level conversion circuit (block B1) and the second buffer logic circuit (block B2) shown in FIG. The second for waveform shaping configured using the NMOS formed by any one of a longer channel length, a smaller channel width, and a higher threshold voltage than the NMOS constituting the logic circuit (block B2) In this configuration, an inverter circuit (block B3) is added.

The circuit operation of the substrate bias control circuit of the fourth embodiment is shown in the timing chart of the signal waveforms of each part in FIG. 8, but the circuit operation is the same as that of the substrate bias control circuit of the second embodiment. The same reference numerals are given, and the description of the contents described in the second embodiment and the operation and effect corresponding thereto will not be repeated. By adding the second inverter circuit (block B 3), the output terminal of the second signal voltage level conversion circuit (block B 1) is connected to the potential of the line Vδ in the second embodiment. The connection is changed to the potential of line V6, which is the inverted signal.

The substrate bias control circuit of the fourth embodiment is obtained by further reducing the power consumption of the substrate bias control circuit for PMOS described in the second embodiment. In other words, in the substrate bias control circuit of FIG. 3, the low potential of run V5, which is the potential of the output terminal of the second signal voltage level conversion circuit (block # 1), is +2 V + Vth (Vth: PM OS Q Therefore, the NMO SQ41 that constitutes the buffer logic circuit is not completely turned off. Here, the second buffer logic circuit (block B 2) is the N-type interface circuit of the second signal voltage level conversion circuit (block B 1) and all functional modules, It is a drive circuit for charging and discharging performed on the N-well of the entire chip. Therefore, since the load capacity becomes large, the channel width of the first-stage inverter circuit is formed small so as to perform waveform shaping, and the channel width of the next-stage inverter circuit is formed large so that the charging and discharging time is increased. Try to be shorter.

However, in the substrate bias control circuit of the fourth embodiment, a second inverter circuit (block B3) for waveform shaping for minimizing a leak current flowing from the power supply wiring Vdd2 to the power supply wiring Vddl is added. It has a configuration. That is, the potential of the output signal from the second signal voltage level conversion circuit (block B 1), that is, the potential of the line V 6 Since the potential also drops by the threshold value of PMSQSQ36, the NMOS that constitutes the second inverter circuit (block B3) for shaping the waveform to fully swing the voltage in the range of 2 V is The NMOS is formed by any one of a longer channel length, a smaller channel width, and a higher threshold voltage than the NMOS constituting the second buffer logic circuit (block B 2). Therefore, the leakage current is very small. Also, the change of the channel length and channel width of the NMOS can be easily changed by mask design, and the NMOS with a high threshold voltage does not need to change the channel 'dose in the semiconductor process. That is, the back gate electrode of the NMO SQ45 that constitutes the second inverter circuit (block B3) is connected to the ground voltage Vssl (± 0V), which is lower than the source potential of the MMOSQ45, or the ground voltage indicated by ¾1. By connecting to Vss2 (-2V), the threshold voltage can be easily increased.

Further, the substrate bias control circuit of the fourth embodiment enables the high-speed charging and discharging of the functional module from the substrate bias control circuit, and the switching from the operation mode to the standby mode or from the standby mode to the operation mode. Mode change can be performed at high speed. FIG. 7 shows an example in which the second buffer logic circuit (block B 2) is formed with two inverters each time. However, the present invention is not limited to this, and a desired number of inverters can be formed. Can be configured. In ¾ and ^ 7, the second buffer logic circuit (block B 2) is described as an interface between the second signal voltage level conversion circuit and the functional module. According to the above specification, the second buffer logic circuit (block B2) need not be provided unless it is necessary to particularly consider the speed in the mode change as described above. Note that the second buffer logic circuit (block B 2) can be constituted by another logic circuit such as an inverter circuit, a NAND circuit, and a NOR circuit.

Further, the substrate bias control circuit of the fourth embodiment is designed so that a high-voltage stress is not applied to each MOS transistor constituting the circuit. That is, the operating voltage is 3 V, the voltage is designed to be 3.3 V between the gate and the source, and the voltage margin is set to ± 10%. Therefore, the voltage between the gate and the source, between the gate and the drain, and between the gate and the drain are 3.6 V, respectively. Since it is formed as described below, it can be formed without particularly thickening the gate oxide film of each MOS transistor constituting the substrate bias control circuit. Therefore, in the substrate bias control circuit of the present embodiment, all the MOS transistors can be formed by a gate oxide film having the same thickness. The long-term reliability of the gate oxide film can be improved, and the reliability of the semiconductor integrated circuit device can be improved. In addition, it is possible to cope with thinning of a gate oxide film corresponding to high integration.

The substrate bias control circuit for the PMOS according to the fourth embodiment is newly provided with a PMOS separately from the power supply voltage Vddl (for example, +2 V) and the ground voltage Vssl (for example, ± 0 V) from the outside of the semiconductor integrated circuit device. Although the power supply voltage Vdd2 (for example, + 4V) has been supplied to the N-well, instead, a charge pump circuit based on a ring oscillator may be configured in the semiconductor integrated circuit device to generate power. However, in this case, the voltage supply is unstable and is inferior in power consumption as compared with the substrate bias control circuit shown in FIG.

X. Using this substrate bias control circuit, it is also possible to self-correct the variation in the threshold voltage of the semiconductor integrated circuit device. As described above, the threshold voltage of a MOS transistor has an error of about 10% in manufacturing. However, in order to reduce the power supply voltage in recent years, the charge pump, the leakage current detection circuit, and the By controlling the power supply wiring connected to the back gate electrode during operation using the substrate bias control circuit of the embodiment, the low voltage can be compensated.

K Fifth Embodiment>

FIG. 9 shows a substrate bias control circuit for NMOS according to a fifth embodiment of the present invention. In the substrate bias control circuit of the present embodiment, the back gate electrode of each PMO SQ 24 and Q 26 constituting the first buffer logic circuit (block A 2) is connected to the ground voltage Vssl (eg ± 0V). The circuit operation of the substrate bias control circuit of the fifth embodiment is shown in the timing chart of the signal waveforms of each part in FIG. 10. The reference numeral is attached, and the first embodiment The description of the contents described in and the operation and effect corresponding thereto will not be repeated.

The substrate bias control circuit of the fifth embodiment improves the driving capability of the first buffer logic circuit (P ch: Q 24, Q 26) in the substrate bias control circuit for NMOS described in the first embodiment. It is intended to increase the speed. In other words, in the substrate bias control circuit shown in FIG. 9, the back gate electrode of each PMOS Q 24 and Q 26 constituting the first buffer logic circuit (block A 2) is the source potential of each PM〇S The ground voltage Vssl (for example, ± 0 V; connected to the same potential as the back gate electrode and the source electrode) eliminates the substrate bias effect and sets the threshold voltage of the PMOS in absolute value. It is configured so that the drain-source current flows in absolute value.

The P-well capacitance of a large functional module formed in a semiconductor integrated circuit device has a heavy load capacity of several hundred pF or more. An S transistor is required. This first buffer logic

To connect the back gate potential of each PMOS that constitutes (Block A 2) to the source potential of each PMOS and the common ground voltage Vssl (for example, ± 0 V), the N for PM0SQ24 and Q26 A buffer region is required, which depends on the capacitance of the P-well region of the functional module.

The circuit configuration is determined by the correlation between the layout area of each PMOS that constitutes (block A 2) and the increase in layout area due to the provision of a dedicated N-well region.

FIG. 11 shows a substrate bias control circuit for PMOS according to a sixth embodiment of the present invention. The back bias electrode of each NMO SQ41, Q43 constituting the second buffer logic circuit (block B2) shown in FIG. It is configured to be connected to a certain power supply voltage Vdd 1 (for example, + 2V). The circuit operation in the substrate bias control circuit of the sixth embodiment is shown in the timing chart of the signal waveforms of each part in FIG. Although the circuit operation is the same as that of the substrate bias control circuit of FIG. 3, the same reference numerals are given and the description thereof is omitted.

The substrate bias control circuit of the sixth embodiment is configured to control the driving capability of the second buffer logic circuit (Nch: Q41, Q43) in the PMOS substrate bias control circuit described in the second embodiment. It is intended to improve and speed up. In other words, the back gate electrode of each NMO SQ ^ l, Q43 that constitutes the second buffer logic circuit (block B2) in the substrate bias control circuit shown in FIG. Power supply voltage Vddl (for example, + 2V). By setting the back gate electrode and the lease electrode to the same potential, the substrate bias effect is eliminated, the threshold voltage of NM 0 S is reduced, and a large drain-source current is formed. Things.

Since the N ゥ L capacitance of a large functional module formed in a semiconductor integrated circuit device has a K load capacitance of several hundred pF or more, a high driving capability of M〇S is necessary to control the N ゥ L potential at high speed. A transistor is required. This second buffer logic

To connect the back gate potential of each NMOS that constitutes (block B 2) to the source potential of each NMOS and a common power supply voltage Vddl d + 2V, use NM0S Q4

1, the force that requires a P-well region for Q43; this is the second buffer logic when there is a body bias effect, depending on the capacitance of the N-well region of the functional module.

The circuit configuration is determined based on the correlation between the layout area of each NMOS that constitutes (block B2) and the increase in layout area due to the provision of a dedicated P-well area.

Seventh embodiment>

FIG. 13 shows a substrate bias control circuit for NMOS according to a seventh embodiment of the present invention. The back bias electrode of each of the PMO SQ 24 and Q 26 constituting the first buffer logic circuit (block A 2) of the third embodiment is similar to the fifth embodiment. However, the configuration is such that it is connected to the ground voltage Vss1 (for example, ± 0 V), which is the source potential of each PMOS. The circuit operation of the substrate bias control circuit of the seventh embodiment is shown in the timing chart of the signal waveforms of each part in FIG. 14, and the circuit operation is the same as that of the substrate bias control circuit of the first embodiment. The parts are denoted by the same reference numerals and the description thereof will be omitted.

The substrate bias control circuit of the seventh embodiment improves the driving capability of the first buffer logic circuit (P ch: Q 24, Q 26) in the substrate bias control circuit for NMOS shown in FIG. It is intended to be. In other words, the back gate electrode of each PMO SQ24, Q26 constituting the first buffer logic circuit (block A2) in the substrate bias control circuit shown in FIG. 13 is the source potential of each PMOS. It is connected to the ground voltage Vssl (for example, ± 0V). By setting the back gate electrode and the source electrode to the same potential, the substrate bias effect is eliminated, the threshold voltage of PMOS is reduced in absolute value, and the drain-source current flows in absolute value. It is composed. This is because the P-well capacity of a large functional module formed in a semiconductor integrated circuit device has a heavy load capacity of several hundred pF or more. This is because an M〇S transistor with the required capacity is required.

However, the first inverter circuit (block A3) for waveform shaping provided between the first signal voltage level conversion circuit (block A1) and the first buffer logic circuit (block A2). The back gate electrode of the PMO SQ 28 is connected to the power supply voltage Vddl (for example, +2 V) or the power supply voltage Vdd2 (for example, +4 V) shown in FIG. 3, and the ground voltage Vssl (for example, ± 0 V) to the ground voltage Vss2 (for example, For example, it is better to minimize the leakage current flowing to 1 V).

In order to connect the back gate potential of each PMOS constituting the first buffer logic circuit (block A 2) to the source potential of each PMOS and the common ground voltage Vss 1 (for example, earth 0 V), PMOSQ 24 , An N-level region for Q26 is required. This is based on the load capacity of the P-well region of the functional module, the layout area of each PMOS constituting the first buffer logic circuit (block A2) when there is a substrate bias effect, and the N-well region for The circuit configuration is determined in correlation with the increase in the layout area due to the provision of the circuit.

FIG. 15 shows a substrate bias control circuit for PMOS according to the eighth embodiment of the present invention. Is shown. The substrate bias control circuit of the present embodiment is similar to the sixth embodiment, except that the back gate electrodes of the NM0 SQ41 and Q43 constituting the second buffer logic circuit (block B2) of the fourth embodiment. , And is connected to the source potential Vdd 1 (for example, +2 V) of each NMOS. The circuit operation of the substrate bias control circuit of the eighth embodiment is shown in the timing chart of the signal waveforms of each part in FIG. 16. The circuit operation is the same as that of the substrate bias control circuit of the second embodiment. Are denoted by the same reference numerals and description thereof will be omitted.

The substrate bias control circuit of the eighth embodiment is a circuit for controlling the driving capability of the second buffer logic circuit (Nch: Q41, Q43) in the substrate bias control circuit for PM0S described in the fourth embodiment. It is intended to improve and speed up. In other words, the substrate bias control circuit of the present embodiment is a back gate of each of the NMO SQ41 and Q43 forming the second buffer logic circuit (block B2) in the substrate bias control circuit shown in FIG. The electrode is connected to Vddl (for example, + 2V), which is the source potential of each NMOS. By setting the potential of the knock gate electrode and the source electrode to the same potential, the substrate bias effect is eliminated, the threshold voltage of NMOS is reduced, and a large amount of drain-source current flows. is there. This is because the N-type capacitance of a large functional module formed in a semiconductor integrated circuit device has a heavy load capacity of several hundred pF or more. This is because a MOS transistor is required.

However, a second inverting circuit for waveform shaping (block B 3) provided between the second signal voltage level conversion circuit (block B 1) and the second buffer logic circuit (block B 2) The back gate electrode of the NMO SQ 45 is connected to the ground voltage Vssl (for example, ± 0 V) or the ground voltage Vss2 (for example, −2 V) shown in FIG. 1 and is connected to the power supply voltage Vdd2 (for example, +4 V). It is better to minimize the leakage current flowing to Vdd 1 (eg + 2V). In addition, the back gate potential of each NM〇S constituting the second sofa logic circuit (block B 2) is connected to the power supply voltage Vdd 1 (for example, +2 V) common to the source potential of each NMOS. Requires a P-well region for NMO SQ41 and Q43. However, this is due to the second buffer logic circuit when there is a body bias effect, depending on the load capacitance of the N-well region of the functional module. The circuit configuration is determined by the correlation between the layout area of each NMS that constitutes (block B2) and the increase in the layout area due to the provision of a dedicated P-well area.

The variations of the substrate bias control circuit have been described above. However, these circuits are not limited to being used as the substrate bias control circuit, and can be applied to, for example, a flash memory. It can be used as a level shifter as an interface between parts having different voltage levels such as input / output circuits.

Next, a description will be given of an example of a wiring layout of a MOS transistor constituting a functional module, in which a gate potential is controlled by a substrate bias control circuit.

Ninth embodiment>

Next, a function block layout of a master slice type semiconductor integrated circuit device in which a semiconductor integrated circuit device having a substrate bias control circuit according to an embodiment of the present invention is formed by a master slice method will be described.

FIG. 18 shows a ninth embodiment of the present invention! ! Inverter circuit I NV1 shown in FIGS. 19 (a) and 19 (b) is laid out on a basic cell in a master-slice type semiconductor integrated circuit device. Things.

FIG. 19A shows a symbol of the inverter circuit I NV 1, in which an output signal X is output in an inverted logic with respect to an input signal A. If this inverter circuit INV1 is shown in a transistor level circuit diagram, it will have a circuit configuration as shown in FIG. 19 (b). In Fig. 19 (b), the input terminal to which input signal A is input is commonly connected to the gate terminal of PM0SQ2 and the gate terminal of NMO SQ1, and the source terminal of PM〇SQ2. Are connected to the power supply wiring layer Vddl, and the back gate terminal is connected to the power supply wiring layer Vdd2 via the N-well. Similarly, the source terminal of NMO SQ 1 is electrically connected to the ground wiring layer Vssl, the back gate terminal is electrically connected to the ground wiring layer Vss2 via the P-well, and the drain terminal of PMOS Q 2 and the NMOS Q 1 The output terminal is connected to the drain terminal at the output terminal from which the output signal X is output. Inverter circuits I NV 1 in a basic cell group in which a plurality of When a wiring layout is formed on one basic cell, a wiring layout as shown in FIG. 18 is obtained.

Although the transistor configuration of the basic cell shown in FIG. 18 is different for each company, here, the gate electrodes G 1 and 03 and the gate electrode G 5 having a smaller channel width than the gate electrodes 01 and G 3, and the source and drain electrodes NM 0 SQ 1 consisting of SD 1, SD 3, SD 5 and SD 7, PMOSQ 2 consisting of gate electrodes G 2 and G 4, source / drain electrodes SD 2, SD 4 and SD 6 are the basic unit (two PMOS + 2 The wiring layout is performed using a basic cell of NMO S + 1 sub-NMO S).

When the inverter circuit I NV1 shown in FIGS. 19 (a) and (b) is formed on this basic cell, the wiring layout shown in FIG. 18 is obtained. That is, the ground wiring layer V ss 1 is formed by the first metal wiring layer extending in the channel length direction of the MOS transistor. The ground wiring layer Vssl, the source electrode SD3 of the NMOS Q1, and the unused source / drain electrode SD1 are electrically connected to each other through the connection holes.

The well electrode B1 extends in the channel width direction of the MOS transistor, and is connected to the well electrode B1, the first metal wiring layer M13, and the second metal wiring layer above the first metal wiring layer. The ground wiring layer Vss2 thus formed and the first metal wiring layer M13 are electrically connected to each other via the connection hole H1 and the connection hole C1. The power supply wiring layer Vddl is formed by a first metal wiring layer extended in the channel length direction of the MOS transistor, and the power supply wiring layer Vddl is connected to the source electrode SD of the PMO SQ 2 through a connection hole. 4 _c also are each connected to the source-drain electrode SD 2 where and are not used, Ueru electrode B2 is extended in the channel width direction of the MOS transistor. The source electrode layer B2 and the first metal wiring layer Ml4, and the power source wiring layer Vdd2 and the first metal wiring layer M14 formed by the second metal wiring layer form connection holes H2 and connection holes. Each is connected via C 2.

Further, an input signal / M for controlling the inverter circuit I NV1 is applied to the first metal wiring layer M11, and the gate electrode G3 of the NMO SQ1 and the gate electrode G4 of the PMOSQ2 are connected to the connection hole. The input signal A is applied to the gate electrodes G3 and G4 by being electrically connected to the first metal wiring layer M11 through the gate electrodes G3 and G4, respectively. —On the other hand, the output signal X is output to the first metal wiring layer M 1 2, but the output signal X is output from the NMO SQ 1 drain electrode SD 5 and the PMO SQ 2 The drain electrodes SD6 are connected to the first metal wiring layers M12 via the connection holes. Therefore, the drain electrodes SD5 and SD6 of the NMO SQ1 and the PMO SQ2 are electrically connected in common to form an output signal X.

The power supply wiring layer Vdd2 and the ground wiring layer Vss2 formed by the second metal wiring layer are arranged on the wiring grids GX1 and GX5 of the NMOS electrodes 1 and B2h of the NMOS Q1 and PMO SQ2. The wiring grids GX 2, GX 3, and GX 4 are set as the area where the power supply wiring layer V dd 2 and the ground wiring layer V ss 2 formed by the second metal wiring layer are not arranged. The connection holes C1, C2, H1, H2 and the first metal wiring layer M13, which connect the power supply wiring layer Vdd2 and the ground K-line layer Vss2 to the NMO SQ1 and PMO SQ2 well electrodes, respectively. According to the wiring rule, Ml4 is a wiring grid GN5, GN6, GN7 between the power wiring layer Vddl and the ground wiring layer Vss1 formed by the first metal wiring layer, and a wiring grid GP1, It is placed on GP2, GP3 and on wiring grid GX1 or GX5.

Further, according to the above wiring rules, the connection hole C2 directly connected to the gauge electrodes Bl, B2 of the NMO SQ1 and the PMO SQ2 is formed by the first metal wiring layer and has one potential. It is arranged on the grid GP3 adjacent to the power supply wiring layer Vddl to be supplied and on the wiring grid GX1. The connection hole C1 is further disposed on the grid GN5 adjacent to the ground wiring layer Vss1 supplying the other potential and on the wiring grid GX5.

These wiring rules are to secure the layout wiring area such as the signal wiring inside the functional circuit by the other second metal wiring layer or the signal wiring between the functional blocks on the wiring grids GX2, GX3, GX4. Yes, the wiring grids GN1, GN2, GN3 and the wiring grids GP5, GP6, GP7 are also functional circuit internal signal wiring with other first metal wiring layers, or signal wiring between function blocks, etc. This secures the placement and routing area. By allocating this arrangement and wiring area, a new power supply wiring area for controlling each back gate electrode of PM0 SQ 2, which is different from the electric potential of the power supply wiring and the ground wiring, and Μ 0 SQ 1 is secured, and wiring layout is performed efficiently. I can do it. In addition, the arrangement of the connection holes C 1 and C 2 directly connected to the NMO SQ 1 and PMO SQ 2 plug electrodes depends on the power supply formed by the first metal wiring layer extending in the channel length direction of the MOS transistor. The wiring layer Vddl and the ground wiring layer Vss1 are placed and routed in the wiring grid at or near the center of the channel width of the MOS transistor, and a potential is applied to the center of the source electrode of the MOS transistor. This has the effect of stabilizing the source potential at the MOS transistor. In other words, since the contact hole can take only one place due to the wiring pitch, in order to avoid bias of the wiring resistance in the power supply wiring layer Vddl and the ground wiring layer Vss1, the contact hole is formed to have the above-mentioned channel width. By arranging them on the central part or on the wiring grid close to the central part, the distance between the contact hole and each power supply wiring can be made uniform, and uniform resistance can be formed.

That is, the arrangement of the connection holes C1 and C2 directly connected to the gate electrode of the M〇S transistor also depends on the power supply wiring layer Vdd, which is a wiring grid at or near the center with respect to the channel width of the MOS transistor. By arranging it on GP3 or GN5 on wiring grid GX1 or GX5, which is the grid adjacent to 1 and the ground wiring layer Vss1, it is possible to stabilize the gate potential of the MOS transistor. .

The first metal wiring layers M 13, M 14 and the power supply wiring are connected to the plug electrodes B 1, B 2 of the NMO SQ 1 and the PMO SQ 2 via the connection holes C 1, C 2, HI, H 2. Instead of the method of electrically connecting each of the layer Vdd 2 and the ground wiring layer Vss2, the NM 0 SQ 1 is directly connected to the power supply wiring layer Vdd 2 and the ground wiring layer Vss 2 formed by the second metal wiring layer. , And PMO SQ 2 can be connected to the well electrodes B 1 and B 2 via connection holes.

In the present embodiment, since one contact hole is provided for one MOS, latch-up can be prevented.

Further, in the present embodiment, the basic cell constituting the inverter circuit is taken up and its wiring layout is described. However, in a plurality of basic cells formed on a chip, each basic cell is provided on the basic cell. You can select whether to form the power supply wiring layer Vdd2 and the ground wiring layer Vss2. Also, power supply wiring layer Vdd 2, ground wiring In the basic cell that does not require the function of the layer Vss2, the second metal wiring layer formed as the power supply wiring layer Vdd2 and the ground wiring layer Vss2 is replaced with an auxiliary power supply of the power supply wiring layer Vddl and the ground wiring layer Vss1. It can also be used as

10th embodiment>

FIG. 20 is a wiring layout diagram according to the tenth embodiment of the present invention. The NAND circuit shown in FIGS. 21 (a) and 21 (b) is a basic layout in a master slice type semiconductor integrated circuit device. This is a wiring layout on a cell. 20, members that are the same as those in FIG. 18 are indicated by the same reference numerals.

FIG. 21 (a) shows a symbol of a NAND circuit, in which an output signal X is output in an inverted logic with respect to a product of an input signal A and an input signal B. If this NAND circuit is represented by a transistor-level circuit diagram, the circuit configuration is as shown in FIG. 21 (b). In FIG. 21 (b), one input terminal to which input signal A is input is commonly connected to the gate terminal of PM◦SQ4 and the gate terminal of NM0SQ3, and the other input terminal to which input signal B is input. Is commonly connected to the gate terminal of the PMOS Q6 and the gate terminal of the NMOS SQ5.

The source terminals of PMOS Q 4 and Q 6 are connected to the power supply wiring Vddl, and the back gate terminal is connected to the power supply wiring layer Vdd2 via an N-well. Then, the source terminal of the NMOS Q5 is connected to the ground wiring layer Vss1, and the backgate terminals of the NMO SQ3 and Q5 are connected to the ground wiring layer Vss2 via the P-well.

Further, the NMO SQ 3 and Q 5 are connected in series, and the drain terminals of the PMOS Q 4 and Q 6 and the drain terminal of the NMO SQ 3 are commonly connected at the output terminal from which the output signal X is output. It has a configuration.

When a wiring layout is formed on one basic cell in a basic cell group in which a plurality of the NAND circuits are arranged in a matrix, a wiring layout as indicated by 320 is obtained. Although the transistor configuration of the basic cell shown in FIG. 20 varies from company to company, as in the basic cell shown in FIG. 18, the gate electrodes G 7, G 9 and the channel are higher than the gate electrodes G 7, G 9. NMO SQ3, Q5 consisting of gate electrode G11 with small width, source 'drain electrode SD9, SD11, SD13 and SD15, and gate electrode G6 and And G 8, and PMOS Q 4, Q 6 consisting of source and drain electrodes SD 8, SD 10 and SD 12 as a basic unit (2 PM0 S + 2 NM0S + 1 sub · NM〇S) The wiring layout is performed using the basic cells to be performed.

When the NAND circuits shown in Figs. 21 (a) and 21 (b) are configured on this basic cell, the wiring layout shown in Fig. 20 is obtained. That is, the ground wiring layer Vssl is formed by the first metal wiring layer extending in the channel length direction of the MOS transistor. The ground wiring layer Vss 1 is electrically connected to the source electrode SD 13 of the NMOS 3 via the connection hole.

The well electrode B3 extends in the channel width direction of the MOS transistor, and is formed by the well electrode B1, the first metal wiring layer 15, and the second metal wiring layer above the first metal wiring layer. The ground wiring layer Vss2 to be connected and the first metal wiring layer M15 are connected via the connection hole H1 and the connection hole C1, respectively.

In addition, the power supply wiring layer Vdd 1 is formed by a first metal wiring layer extending in the channel length direction of the M〇S transistor, and the self power supply wiring layer Vdd 1 is connected to the source electrode SD of the PM 0 SQ 5 through the connection hole. 8 and SD 12 respectively.

Then, the well electrode B4 is extended in the channel width direction of the MOS transistor, and the power electrode wiring layer Vdd2 formed by the above-mentioned well electrode B4, the first metal wiring layer M17, the second metal wiring layer, and the second One metal wiring layer M 17 is connected to each other via a connection hole H 2 and a connection hole C 2.

Further, an input signal A for controlling the NAND circuit is applied to the first metal wiring layer M 15, and the gate electrode G 9 of the NMO SQ 3 and the gate electrode G 8 of the PMO SQ 4 are connected through the connection hole. Each is electrically connected to first metal wiring layer M 15. Further, the input signal B is applied to the first metal wiring layer M 16, and the gate electrode G 7 of NMO SQ 5 and the gate electrode G 6 of PMO SQ 6 are connected to the first metal wiring layer M 1 through the connection hole. 6 are electrically connected to each other. Thus, the input signal A is applied to the gate electrodes G 8 and G 9, and the input signal B is applied to the gate electrodes G 6 and G 7.

On the other hand, although the output signal X is output to the first metal wiring layer M 19, at the output of the NAND circuit NAND, the drain electrode SD 9 of NMO SQ 5 and the drain electrode of PM 0 SQ 6 The electrode SD10 is connected to the first metal wiring layer M19 via the connection hole. Connected. Therefore, the drain electrodes SD 9 and SD 10 of the NMO SQ 5 and the PMO SQ 6 are electrically connected in common to form an output signal X.

The power supply wiring layer Vdd2 and the ground wiring layer Vss2 formed by the second metal wiring layer are connected to the wiring grids GX 1 on the NMO SQ 3, Q 5 and the PMOS electrodes Q 4, Q 5 on the electrode B 3, B 4. , GX 5 and the wiring grids GX 2, GX 3, and GX 4 are formed by the second metal wiring layer. The power wiring layer Vdd 2 and the ground wiring layer Vss 2 are arranged and prohibited. I do. Also, connection holes C 1, C 2, H 1, H 2 and the first metal wiring layer for connecting the power supply wiring layer Vdd2 and the ground wiring layer Vss2 to the NMO SQ 3, Q 5 and the PMOS Q 4, Q 6 gage electrodes. According to the wiring rules, M 18 and M 19 are formed on the wiring grids GN 5, GN 6, GN 7 and between the power wiring layer Vddl and the ground wiring layer Vss 1 formed by the first metal wiring layer. On GP1, GP2 and GP3 and on wiring grid GX1 or GX5. Further, according to the wiring rule, the connection holes C1 and C2 directly connected to the well electrodes B3 and B4 of the NMO SQ5 and the PMO SQ4 are formed by the first metal wiring layer and are formed on one side. It is arranged on the grid GP3 adjacent to the power supply wiring layer Vddl supplying the potential and on the wiring grid GX1 or GX5. Furthermore, it is arranged on the adjacent grid G N5 of the ground wiring layer V ss1 that supplies the other potential, and on the wiring grid G X1 or G X5.

These wiring rules ensure that the wiring grids GX2, GX3, and GX4 have a wiring area for signal wiring inside the functional circuit with other second metal wiring layers or signal wiring between functional blocks. Similarly, the wiring grids GN 1, GN 2, GN 3 and the wiring grids GP 5, GP 6, GP 7 are also connected to the functional circuit using other first metal wiring layers. This is to secure a layout wiring area for signal wiring and the like. By securing this arrangement and wiring area, a new power supply wiring area for controlling each back gate electrode of PMO SQ4, Q6, NMO SQ3, and Q5, which is different from the potential of the power supply wiring and ground wiring, is secured, and the Wiring layout is possible. The arrangement of contact holes C 1 and C 2 directly connected to the well electrodes B 3 and B 4 of NMO SQ 3 and Q 5 and PMO SQ 4 and Q 6 extends in the direction of the channel length of the MOS transistor. Power supply wiring layer Vddl and ground wiring formed by the formed first metal wiring layer The layer Vssl is arranged and wired in the wiring grid at or near the center with respect to the channel width of the MOS transistor, and by applying a potential to the center of the source electrode of the MOS transistor, the source potential of the MOS transistor is stabilized. There is an effect.

Similarly, the arrangement of the connection holes C 1 and C 2 that are directly connected to the MOS transistor's well electrode is also a wiring grid at or near the center with respect to the channel width of the MOS transistor. By arranging it on GP3 or GN5 on the wiring grid GX1 or GX5, which is the adjacent grid of the power supply wiring layer Vddl and the ground wiring layer Vss1, the jewel potential of the MOS transistor is stabilized. In other words, since the contact hole can take only one place due to the wiring pitch, in order to avoid bias of the wiring resistance in the power supply wiring layer Vddl and the ground wiring layer Vss1, the contact hole is formed in the channel width. It is arranged on the wiring grid at or near the center, so that the distance between the contact hole and each power supply wiring can be made uniform, and uniform resistance can be formed.

The first metal wiring layers M 18, M 5 are connected to the NMOS, Q 3, Q 5, and PM electrodes SQ 4, Q 5 via the connection holes C 1, C 2, HI, H 2. 19, the power wiring layer Vdd2, and the ground wiring layer Vss2 are electrically connected to each other by directly connecting the NM 0 from the power wiring layer Vdd2 and the ground wiring layer Vss2 formed by the second metal wiring layer. The connection can also be made by connecting through the connection holes to the well electrodes B3, B4 of SQ3, Q5 and PMOS Q4, Q6.

In the present embodiment, since one contact hole is provided for one element, latch-up can be prevented.

Further, in the present embodiment, the basic cell constituting the inverter circuit is taken up and its wiring layout is described. However, in a plurality of basic cells formed on a chip, a basic cell is provided for each basic cell. It is possible to select whether or not to form the power supply wiring layer Vdd2 and the ground wiring layer Vss2 thereon. Further, in a basic cell which does not require the functions of the power supply wiring layer Vdd2 and the ground wiring layer Vss2, the second metal wiring layer formed as the power supply wiring layer Vdd2 and the ground wiring layer Vss2 may be replaced with a currently used one. It can also be used as an auxiliary power supply for the power supply wiring layer Vddl and the ground wiring layer Vssl. Example 11>

FIG. 22 is a wiring layout diagram according to the eleventh embodiment of the present invention, in which the NOR circuits shown in FIGS. 23 (a) and 23 (b) are mounted on a basic cell in a master slice type semiconductor integrated circuit device. This is the wiring layout. In FIG. 22, members that are the same as those in FIGS. 18 and 20 are denoted by the same reference numerals.

NOR in FIG. 23 (a) indicates a symbol of the NOR circuit, and the output signal X is output in an inverted logic with respect to the sum of the input signal A and the input signal B. When this NOR circuit is shown in a transistor level circuit diagram, it has a circuit configuration as shown in FIG. 23 (b). In Fig. 23 (b), one input terminal to which input signal A is input is commonly connected to the gate terminal of PMO SQ8 and the gate terminal of NMO SQ9, and input signal B is input. The other input terminal is commonly connected to the gate terminal of PMOS Q10 and the gate terminal of NMO SQ7.

Also, the source terminal of PMO SQ 8 is connected to the power supply wiring layer Vddl, the back gate terminals of PMO SQ8 and Q10 are connected to the power supply wiring layer Vdd 2 through N-wells, and the NMO SQ 7 and Q 9 Are connected to the ground wiring layer Vss1, respectively, and the back gate terminals are connected to the ground wiring layer Vss2 via the P-well.

PMO SQ 8 and Q 10 are connected in series, and the drain terminal of PMOS Q 10 and the drain terminal of NM 0 SQ 7 and Q 9 are connected to the output terminal from which output signal X is output. (And:

When a wiring layout of this NOR circuit is formed on one basic cell in a basic cell group arranged in a matrix, a wiring layout as shown in FIG. 22 is obtained. Although the transistor configuration of the basic cell shown in FIG. 22 is different for each company, as in the basic cell shown in FIG. 18, the gate electrodes G 13, G 15 and the gate electrodes G 13, G 1 NMOS Q7, Q9 comprising gate electrode G17, source'drain electrodes SD17, SD19, SD21, and SD23 having a channel width smaller than 5, gate electrodes G10 and G PMO SQ 8, Q 10 consisting of the source and drain electrodes SD 14, SD 16, and SD 18 as basic units (two PM 0 S + two NM A wiring layout is performed by using a basic cell of 0 S + 1 sub-NM (N S). When the NOR circuits NOR shown in FIGS. 23 (a) and 23 (b) are formed on this basic cell, the wiring layout shown in FIG. 22 is obtained. That is, the ground wiring layer V ss1 is formed by the first metal wiring layer extending in the channel length direction of the MOS transistor, and the ground wiring layer Vssl and the NMOS Q 7 and Q 9 are connected via the connection hole. The electrodes SD 17 and SD 21 are electrically connected to each other.

The well electrode B5 extends in the channel width direction of the MOS transistor, and the well electrode B5, the first metal wiring layer M23, and the second metal wiring layer above the first metal wiring layer M23. The ground wiring layer Vss2 and the first metal wiring layer M23 are electrically connected to each other via the connection hole H1 and the connection hole C1, respectively. The power supply wiring layer Vddl is formed by a first metal wiring layer extending in the channel length direction of the MOS transistor, and the power supply wiring layer Vdd1 is connected to the source electrode SD18 of the PMO SQ 8 through a connection hole. You.

The well electrode B6 extends in the channel width direction of the MOS transistor. The well electrode B6 and the first metal wiring layer M24, the power supply wiring layer Vdd2 formed by the second metal wiring layer, and the first The metal wiring layer M24 is respectively connected via the connection hole H2 and the connection hole C2.

Further, the input signal A for controlling the NOR circuit is applied to the first metal wiring layer M20, and the gate electrode G15 of NMOS 9 and the gate electrode G12 of PMO SQ8 are connected via the connection hole. By being electrically connected to the first metal wiring layer M20, the input signal A is applied to the gate electrodes G15 and G12. Then, the input signal B is applied to the first metal wiring layer M 21, and the gate electrode G 13 of NMOS 7 and the gate electrode G 10 of PMOSQ 10 are connected to the first metal wiring layer M 2 via the connection hole. The input signal B is applied to the gate electrodes G13 and G10 by being electrically connected to the gate electrodes G13 and G10, respectively.

On the other hand, the output signal X is output to the first metal wiring layer M22. At the output of the NOR circuit NOR, the drain electrode SD 19 of NM〇SQ 9 and the drain electrode SD of PMO SQ 10 14 are respectively connected to the first metal wiring layer M22 via the connection holes. Therefore, each drain of NM0S Q7, Q9 and PM0SQ8, Q10 The output electrodes X are formed by electrically connecting the pin electrodes SD 19 and SD 14 electrically. The power supply wiring layer Vdd 2 and the ground wiring layer V ss 2 formed by the second metal wiring layer are NM 0 SQ 7, <39 and? -03 <28, wiring on Q10's well electrodes B5, B6 Arranged and wired on grids GX1, GX5, and second metal wiring on wiring grids GX2, GX3, GX4 This is the area where the power wiring layer Vdd 2 and the ground wiring layer Vss 2 are formed.

In addition, connection holes C 1, C 2, H 1, which connect the power supply wiring layer Vdd 2 and the ground wiring layer Vss 2 to the NMO SQ 7, 09 and 1 電極 0 SQ 8, Q 10 H2 and the first metal wiring layer are M23 and 24, wiring grids between the power wiring layer Vddl and the ground wiring layer Vss1 formed by the first metal wiring layer are defined by wiring rules GN5, GN6, GN 7 and on wiring grids GP1, GP2, GP3 and on wiring grid GX1 or GX5.

Furthermore, according to the above wiring rules, the connection holes C 1 and C 2 directly connected to the GMO electrodes B 5 and B 6 of the NMO SQ 7 and Q 9 and the PMO SQ 8 and Q 10 are formed by the first metal wiring. The adjacent grid GP3 of the power supply wiring layer Vddl that is formed by the layer and supplies one potential, and is disposed on the wiring grid GX1 or GX5. Further, it is disposed on the adjacent grid GN5 of the ground wiring layer Vss1 for supplying the other potential and on the wiring grid GX1 or GX5.

These wiring rules ensure that the wiring grids GX2, GX3, GX4-have a wiring area for signal wiring inside the functional circuit by another second metal wiring layer, or signal wiring between functional blocks. Similarly, the wiring grids GN1, GN2, GN3 and the wiring grids GP5, GP6, and GP7 are also functional circuit internal signal wiring by other first metal wiring layers, or signals between function blocks. This is to secure a layout area for wiring and the like. By securing this placement and wiring area, a new power supply wiring area for controlling the back gate electrodes of each of the PMO SQ8, Q10, NMOS Q7 and Q9, which is different from the potential of the power supply wiring and the ground wiring, is secured. Good wiring layout can be achieved. The arrangement of the connection holes C 1 and C 2 that are directly connected to the N-electrodes B 5 and B 6 of the NMO SQ 7 and Q 9 and the PMO SQ 8 and Q 10 Power wiring layer Vddl and ground formed by extended first metal wiring layer The wiring layer Vssl is arranged and wired in the wiring portion at or near the center with respect to the channel width of the MOS transistor, and by applying a potential to the center of the source electrode of the MOS transistor, the potential of the MOS transistor is reduced. This has the effect of stabilizing the source potential. In other words, since the contact hole can take only one place due to the wiring pitch, the contact hole is connected to the above-mentioned channel in order to avoid bias of the wiring resistance in the power wiring layer Vddl and the ground wiring layer Vss1. By arranging them on the wiring grid or at the center of the width or near the center of the width, the distance between the contact hole and each power wiring can be made uniform, and uniform resistance can be formed. Similarly, the arrangement of the connection holes C 1 and C 2 directly connected to the MOS transistor's well electrode is also a wiring grid close to the center or the center with respect to the channel width of the MOS transistor. By arranging it on GP3 or GN5 on the wiring grid GX1 or GX5, which is the adjacent grid of the power supply wiring layer Vddl and the ground wiring layer Vssl, stabilizes the gate potential of the MOS transistor.

The first metal wiring layer M 23, N 9 is connected to the NMO SQ 7, Q 9, and the p-type electrodes B 5, B 6 of the PMOS Q 8, Q 10 via the connection holes C 1, C 2, HI, H 2. The method of electrically connecting the M24 and the power supply wiring layer Vdd2 and the ground wiring layer Vss2 is performed by directly connecting the power supply wiring layer Vdd2 and the ground wiring layer Vss2 formed by the second metal wiring layer to N MO SQ 7 and Q 9 and PMOS Q 8, Q 10 can also be connected by connecting to the well electrodes E 5, B 6 via connection holes.

Further, in this embodiment, the basic cell constituting the inverter circuit is taken up and its wiring layout is described. However, in a plurality of basic cells formed on a chip, each basic cell is placed on the basic cell. It is possible to select whether to form the power supply wiring layer Vdd2 and the ground wiring layer Vss2. Further, in a basic cell which does not require the functions of the power supply wiring layer Vdd2 and the ground wiring layer Vss2, the second metal wiring layer formed as the power supply wiring layer Vdd2 and the ground wiring layer Vss2 may be replaced with a currently used one. It can also be used as an auxiliary power supply for the power supply wiring layer Vddl and the ground wiring layer Vss1. Example 12)

The functional module in the semiconductor integrated circuit device of the present invention has various functions, and can be configured by a semiconductor integrated circuit device such as a logic circuit, a ROM, a RAM, an MP, and a standard cell. In this case as well, a substrate bias control circuit is provided on the chip, the back gate electrode is controlled by an external power supply, the operation of the MOS transistor is controlled using the substrate bias effect, and the high-performance function described above is achieved. It implements a block. In the present embodiment, a semiconductor integrated circuit device in which the function block of the semiconductor integrated circuit device of the present invention is applied to a RAM circuit will be described.

FIG. 24 is a wiring layout diagram according to the 12th embodiment of the present invention. The RAM circuit (random access memory) shown in FIG. 25 is mounted on a basic cell of a function block in a master slice type semiconductor integrated circuit device. This is the wiring layout. 24, the same members as those in FIGS. 18, 20, and 22 are denoted by the same reference numerals. Figure 25 shows a RAM circuit. An NMOS transmission in which one of the source and drain electrodes is connected to the write bus, and the write signal W switches between the write bus and the memory cell. -Gate Q11 and this NMOS transmission. One of the source and drain electrodes is connected to gate Q11, and an inverter circuit that forms a memory cell by write signal W and inverted signal XW of write signal W. It includes a transmission gate consisting of PMO SQ12 and NMO SQ13 for switching control between INV2 and INV3. Further, the RAM circuit amplifies the signal in the memory cell, connects an inverter circuit I NV4 for driving the read bus, and one of the source and drain electrodes to the read path, and resets the read signal by the read signal R. This includes an NMOS transmission 'gate Q15 for performing switch control between the gate and the memory cell.

When the wiring layout of this RAM circuit is made using two basic cells in a basic cell group arranged in a matrix, a wiring layout shown in FIG. 24 is obtained. Although the transistor configuration of the basic cell shown in Fig. 24 varies from company to company, the same basic unit as the basic cell shown in Fig. 18 (2 PMO S + 2 NMO S + 1 Sub. NMO S). When the RAM circuit shown in FIG. 25 is formed on this basic cell, the wiring layout shown in FIG. 24 is obtained.

In other words, the NMOS Gaussian electrode B7 in the RAM circuit extends in the channel width direction of the MOS transistor, and the Gaussian electrode B7, the first metal wiring layer M25, and the second metal layer above the first metal wiring layer. The ground wiring layer Vss2 formed by the wiring layer and the first metal wiring layer M25 are electrically connected to each other via the connection hole H1 and the connection hole C1. Then, the PMOS gate electrode B8 in the RAM circuit is extended in the channel width direction of the MOS transistor, and the PEL electrode B8, the first metal wiring layer M26, and the upper layer above the first metal wiring layer. The power supply wiring layer Vdd2 formed by the second metal wiring layer and the first metal wiring layer M26 are electrically connected to each other through the connection hole H2 and the connection hole C2. Therefore, the transmission gates Q11, 15 and the inverter circuits I NV2 to INV2 to form the RAM circuit shown in FIG. 25: [NMOS of NV4 The back gate electrode is connected to the ground wiring layer Vss2. The PMOS back gate electrode is connected to the power supply wiring layer Vdd 2.

The power supply wiring layer Vdd 2 and the ground wiring layer Vss 2 supplied by the second metal wiring layer are wiring grids GX 1, GX 5 on the NM〇S and PMOS peg electrodes B 7, B 8 in the RAM circuit. The power supply wiring layer Vdd2 and the ground wiring layer Vss are formed on the wiring grids GX2, GX3, 0A4, and 0A6, GX7, and GX8 and are formed by the second metal wiring layer. Let 2 be a placement and routing prohibited area.

Also, connection holes C 1, C 2, H 1, H 2, and H 3 for connecting the power supply wiring layer Vdd 2 and the ground wiring layer Vss 2 to the NMOS and PM〇S peg electrodes B 7, B 8 in the RAM circuit. (1) The metal wiring layers M25 and M26 are formed on the wiring grids GN5, GN6 and GN7 between the power supply wiring layer Vdd1 and the ground wiring layer Vss1 supplied by the first metal wiring layer according to the wiring rules. It is placed on grid GP1, GP2, GP3 and on wiring grid GX1 or GX5. Further, according to the wiring rules, the connection holes CI and C2 directly connected to the NMOS and the PM electrodes S7 and B8 in the RAM circuit are formed by the first metal wiring layer. The power supply wiring layer Vdd1 that supplies one potential or the ground wiring layer Vss1 that supplies the other potential is placed on the wiring grid as close as possible. These wiring rules are based on wiring grids GX 2, GX 3, 04 and 06, GX 7, GX 8, function signal internal signal wiring by other second metal wiring layer or signal wiring between function pro, For example, a layout area for the read / write control signals R, W, and XW shown in FIG. 24 is secured. Similarly, the wiring grids GN 1, GN 2, GN 3 and the wiring grids GP 5, GP 6, GP 7 are also connected to the signal wiring inside the functional circuit or the signal wiring between the function blocks by the other first additional wiring layers, for example. This is to secure the arrangement and wiring area of the light bus and lead bus shown in FIG. Therefore, a new power supply wiring area for controlling the back gate electrodes of the PMOS and NMOS in the RAM circuit which is different from the potentials of the power supply wiring layer and the ground wiring layer can be secured, and the wiring layout can be performed efficiently.

The arrangement of the connection holes C1 and C2 that are directly connected to the NMOS and PMOS peg electrodes is based on the power supply wiring layer formed by the first metal wiring layer extending in the channel length direction of the MOS transistor. Vddl and the ground wiring layer Vss 1 are arranged and wired in the central portion or a wiring grid close to the central portion with the width W of the channel width of the MOS transistor, and by applying a potential to the central portion of the source electrode of the MOS transistor, This has the effect of stabilizing the source potential of the OS transistor. In other words, the contact hole can take only one place due to the wiring pitch. By arranging them on the wiring grid at or near the center of the width, the distance between the contact holes and the power supply wiring can be made uniform, and uniform resistance can be formed.

Similarly, the arrangement of the connection holes C 1 and C 2 that are directly connected to the MOS transistor's jewel electrode should be made as close as possible to the center part or the wiring grid with respect to the channel width of the MOS transistor. By arranging the MOS transistors, the well potential of the MOS transistor can be stabilized. Incidentally, the first metal wiring layers M 25 and M 26 and the power supply wiring layer Vdd2 and the ground are connected to the NMOS and PM〇S in the RAM circuit through the connection holes CI, C 2, HI and H 2. The method of electrically connecting the wiring layers Vss2 is performed by directly connecting the NMOS and PMOS in the RAM circuit directly from the power supply wiring layer Vdd2 and the ground wiring layer Vss2 formed by the second metal wiring layer. Via a connection hole in the electrode It is also possible to connect by connecting.

Further, in the present embodiment, the basic cell constituting the inverter circuit has been taken up and the wiring layout has been described. However, in a plurality of basic cells formed on a chip, each basic cell has its own basic cell. It is possible to select whether to form the power supply wiring layer Vdd2 and the ground wiring layer Vss2. In a basic cell that does not require the functions of the power supply wiring layer Vdd2 and the ground wiring layer Vss2, the second metal wiring layer formed as the power supply wiring layer Vdd2 and the ground wiring layer Vss2 may be replaced with a power supply such as that currently used. It can also be used as an auxiliary power supply for the wiring layer Vddl and the ground wiring layer Vssl.

Next, an application example of the substrate bias control circuit and the function module in the semiconductor integrated circuit device of the present invention, and the power supply to the function module by the power supply formed by the substrate bias control circuit will be described. An example will be described. The configuration of these substrate bias control circuits dynamically optimizes power consumption and speed for all functional modules in a semiconductor integrated circuit using both the NM〇S and PMOS substrate bias control circuits. It is.

FIG. 26 shows a block diagram of a substrate bias control circuit according to the thirteenth embodiment of the present invention, and FIG. 27 shows a cross-sectional structure of a MOS transistor constituting a functional module. The semiconductor integrated circuit device of the present embodiment uses both the NMOS and the PMOS substrate via control circuits described in the first to eighth embodiments described above, for all functional modules in the semiconductor integrated circuit device. It dynamically and optimally controls power consumption and speed. In other words, in the operation mode, the operation is performed using the high-drive MOS transistor characteristics, and in the standby mode, the low-power MOS transistor characteristics are used. It is a feature. In the substrate bias control circuit, as described in the first to 12th embodiments, the 1-system power supply Vddl supplied to a part of the first metal wiring layer (the power supply wiring layer Vddl and the ground wiring layer Vss 1) and The same or different potential as Vssl, and the second metal wiring The two-system power supplies Vdd2 and Vss2 supplied to the layers (power supply wiring layer Vdd2 and ground wiring layer Vss2) are formed. In other words, in the substrate bias control circuit, the secondary power supply Vss2 is supplied to the P-well of the NM〇S in all the functional modules, and the secondary power supply Vdd2 is supplied to the N-well of the PMOS. The second power supply Vss2 formed by the substrate bias control circuit for NMOS is supplied not only to all functional modules but also to the substrate bias control circuit for PMOS. Similarly, the secondary power supply Vdd2 formed by the substrate bias control circuit for PMOS is supplied not only to all functional modules but also to the substrate bias control circuit for NMOS.

Hereinafter, power supply from the substrate bias control circuit to the functional module in FIG. 26A will be described.

In the substrate bias control circuit of the present embodiment, a chip enable signal CE input from an external device is input to a signal voltage level conversion circuit LV 0 N in the substrate bias control circuit for NM〇S, The first power supply voltage Vdd2 and Vss2 by the first buffer logic circuit connected to the first signal voltage level conversion circuit LV0N or the first buffer logic circuit and the first waveform shaping inverter circuit L0G0N. Is controlled.

Here, the signal voltage level conversion circuit LV0 corresponds to the blocks A1 and B1 of the first to eighth embodiments, and although not separately illustrated in the drawings, the substrate bias control for NMOS and PMOS is not particularly described. A description will be given of the thirteenth to fourteenth embodiments assuming that both the first and second signal voltage level conversion circuits provided in the circuit are provided. Note that, in the specification, the first signal voltage level conversion circuit in the substrate bias control circuit for NMOS is denoted by "LV0N" with N appended thereto, and when it is used for PMOS, Append P to indicate “: LVO Pj”.

Further, the first buffer logic circuit, or the first buffer logic circuit and the first waveform shaping inverter circuit LOGO are the blocks A 2, B 2 and A 3 of the first to eighth embodiments. The first and second signal level conversion circuits respectively provided in the substrate bias control circuits for the NMOS and the PMOS, although not separately illustrated in the figure, correspond to the block B3. Each connected to a circuit The first to second buffer logic circuits, or the first and second buffer logic circuits and the first and second waveform shaping circuit overnight circuits, are implemented as the thirteenth to fourteenth embodiments. An example will be described.

In the specification, the first buffer logic circuit, or the first buffer logic circuit and the first waveform shaping inverter circuit in the NMOS substrate bias control circuit are denoted by N. It is indicated as “L〇G 0N”, and if it is for PMOS, it is indicated with “P” and indicated as “LOG0 Pj”.

When the chip enable signal CE is set to the high level, the semiconductor integrated circuit device is set to the operation mode, and the chip enable signal CE is input to the signal voltage level conversion circuit LV0N for NM〇S. The output signal is input to a first buffer logic circuit (or a first buffer logic circuit and a first waveform shaping inverter) LOGON. Then, by the LOG ON, a voltage Vpw for controlling the potential of the P-well, which is the back gate electrode of the NM0S formed in all the functional modules in the semiconductor integrated circuit device, is formed and input to the functional modules. . Further, the voltage Vpw (power supply voltage Vdd2) for controlling the potential of the P-well is also input to the second signal voltage level conversion circuit LV 0 P for PMOS via the P-well.

At the same time, the chip enable signal CE is input to a second signal voltage level conversion circuit LV 0 P for PMOS, and its output signal is output to a second buffer logic circuit (or a second buffer logic circuit and a second buffer logic circuit). Second waveform shaping circuit overnight circuit) Input to L0 GOP. Then, the voltage Vnw for controlling the potential of the N-well, which is the back gate electrode of the PMOS formed in all the function modules in the semiconductor integrated circuit device, is formed by the LOG OP and is input to the function module. Further, the voltage Vnw (ground voltage Vss2) for controlling the potential of the N-well is also input to the first signal voltage level conversion circuit LV 0 N for NMOS via the N-well. In other words, Vdd2 (3 V), which has the same potential as system 1 power supply Vddl (for example, 3 V), is applied to the N-well of PMOS, and the same as system 1 power supply Vss 1 (for example, 0 V) to the P-well of NMOS. The potential Vss 2 (0 V) is applied.

Thus, the source electrode and the back gate electrode of the MOS transistor have the same potential. When a voltage is applied, the sub-threshold characteristics of the MOS transistor become states P 1 and N 1 shown in FIGS. 32 (a) and 32 (b), and in this state, the threshold voltage of the MOS transistor becomes lower. The characteristics are low in absolute value and large in drain current.

On the other hand, when the chip enable signal CE is at the mouth level, the semiconductor integrated circuit device is set to the standby mode, and the first and second signal voltage level conversion circuits and the first and second logic circuits or The first and second logic circuits and the first and second waveform shaping inverter circuits form the i-th signal as described above, and reduce the potentials of the voltages Vnw and P-well for controlling the potential of the N-well. A control voltage Vpw is formed. The voltage Vnw for controlling the potential of the N-well and the voltage Vpw for controlling the potential of the P-well are respectively input to the functional module, and the substrate bias control circuits for the NM〇S and the PM〇S are provided. To be human-powered.

In other words, a second system power supply Vdd2 (for example, 5 V) having a higher potential than the first system power supply Vdd1 (for example, 3 V) is applied to the N-well of the PMOS, and a first system power supply Vssl is applied to the NMOS P-well. A second system power supply Vss 2 (for example, 12 V) having a lower potential than (for example, 0 V) is applied.

As described above, when a high potential voltage is applied to the back gate electrode with respect to the source electrode of PMOS and a low potential voltage is applied to the back gate electrode with respect to the source electrode of NMOS, Mサブ The sub-threshold characteristics of the S transistor are the states P 2, P 3 and N 2, N 3 shown in Fig. 32 (a) and Fig. 32 (b). In this state, the threshold voltage of the MOS transistor is Is high in absolute value and the off current is very small.

Therefore, when the semiconductor integrated circuit device is in the operation mode, it has a high drive type MOS transistor characteristic, and when the semiconductor integrated circuit device is in the standby mode, it has low power consumption type MOS transistor characteristic.

Also, FIG. 26 (b) shows that the chip enable signal CE and the sleeve mode control signal SM or the power down signal PD generated in the semiconductor integrated circuit device are input to the select circuit SEL0, The output signal from this selector circuit SEL 0 is applied to each signal voltage level conversion circuit LV 1 to 3 and the buffer logic circuit (or the buffer circuit). (Logic circuit and waveform shaping inverter circuit) Each of the function modules in the semiconductor integrated circuit device is switched to an operation mode and a standby mode by being input to LOG1 to LOG3, respectively. Then, the control of the back gate electrodes of the PMOS and NMOS is performed by supplying the voltages Vnwl to 3 and the overvoltages Vpw 1 to 3 to the respective functional module wells as described above. It is.

In this case, since the back gate electrodes of the PMOS and NMOS can be controlled for each functional module, the MOS transistor structure of the semiconductor integrated circuit device is shown in FIG. 27 (a) or FIG. 27 (b). Will be able to

The MOS transistor structure in the functional module shown in Fig. 27 (a) has a triple-well structure in order to separate both the P-well of NM ゥ S and the N-well of PMOS from the substrate of the semiconductor integrated circuit device. You. For example, when the substrate SU B 1 of the semiconductor integrated circuit device is a P substrate, the barrier layer VA formed by N separates the P-well PWE L 1 forming the NMOS from the substrate SU B 1. It is formed so as to surround the P-well PWE L 1. The T barrier layer VA is formed separately from the N-well of the functional block different from the N-well NWEL 1 so as not to have a common potential. On the other hand, although not shown, if the substrate SUB 1 of the semiconductor integrated circuit device is an N-substrate, it becomes P because the N-well NWE L 1 on which the PMOS is formed is separated from the substrate SUB 1. A valid layer VA is formed so as to surround the N-well NWE L1. Further, the second P-valid layer VA is formed separately from the P-well of the function block different from the P-well PWE L1 so as not to have a common potential.

Similarly, the MOS transistor structure in the functional module shown in FIG. 27 (b) has a triple-well structure to separate both the NMOS P-well and the PMOS N-well from the substrate of the semiconductor integrated circuit device. Is done. For example, if the substrate S UB 2 of the semiconductor integrated circuit device is a P-substrate, the N-well NWE L 2 is separated from the substrate S UB 2 to separate the P-well P WE L 2 forming the NMOS from the substrate S UB 2. It is formed deeper than the PWE L2, and is separated to surround the PWE L2. The N-well NWEL 2 is formed so as to be separated from the N-well of another different function block so as not to have a common potential. Conversely, although not shown, when the substrate SUB 2 of the semiconductor integrated circuit device is an N substrate, the N-well NWE L 2 on which PM〇S is formed is removed from the substrate SUB 2. For separation, the P-well PWE L 2 is formed deeper than the N-well NWE L 2 and separated so as to surround the N-well NWE L 2. Further, the P-well PWE L2 is formed so as to be separated from the P-well of another different functional block so as not to have a common potential.

As described above, according to the semiconductor integrated circuit device of the present embodiment, a new power supply wiring area for controlling each of the back gate electrodes of the PMOS and NMOS different from the potentials of the power supply wiring and the grounding wiring is secured. Providing wiring rules for efficient wiring layout facilitates the layout design of power supply wiring and signal wiring, and has the effect of simultaneously realizing high-speed operation and low power consumption during standby. .

14th Example>

FIG. 28 shows a block diagram of a substrate bias control circuit according to the fourteenth embodiment of the present invention, and a cross-sectional structure of a MOS transistor constituting a functional module. The semiconductor integrated circuit device of this embodiment uses all of the functions in the semiconductor integrated circuit device by using one of the substrate bias control circuits for NMOS and PMOS described in the first to eighth embodiments. Module: Dynamically optimally controls the power consumption and speed of either the formed NM0S or PM0S. In other words, in the operation mode, operation is performed using the characteristics of the high-drive type MOS transistor, and in the standby mode, only one of the PMOS and NMOS is a low power consumption type MOS transistor. It is characterized in that it is configured to have S-transistor t-type.

In the substrate bias control circuit, as described in the first to twelfth embodiments, the first system power supplies Vddl and Vss supplied to a part of the first metal wiring layer (the power supply wiring layer Vddl and the ground wiring layer Vss 1). One of the 2 system power supply Vdd2 or Vss2, which has the same or different potential as 1 and is supplied to the second metal wiring layer (power supply wiring layer Vdd2 or ground wiring layer Vss2) Things. In other words, in the board bias control circuit, the system power supply Vss 2 or the system power supply Vdd2 is supplied to the NMOS P-well or the PMOS N-well of all functional modules ₍ and When the system power supply Vss2 is formed by the substrate bias control circuit for NMOS In this case, the secondary power supply Vss2 is supplied not only to all functional modules but also to the substrate bias control circuit for PMOS. Similarly, when the secondary power supply Vdd2 is formed by the board bias control circuit for PMOS, not only is the secondary power supply Vdd2 supplied to all functional modules, but also the board bias for NMOS is provided. It is also supplied to the control circuit.

Hereinafter, power supply from the substrate bias control circuit to the functional module in FIG. 28A will be described.

In the present embodiment, a description will be given of an example of a substrate bias control circuit that forms only the secondary power supply Vdd2 that is supplied to the N-well of the PM-S.

In the substrate bias control circuit of the present embodiment, the chip enable signal CE input from the external device is input to the second signal voltage level conversion circuit LV 4 P in the PM〇S substrate bias control circuit. A second buffer logic circuit connected to the second signal voltage level conversion circuit LV4P or a second buffer logic circuit and a second waveform shaping inverter circuit LOG4P to provide a secondary power supply Vdd2. Is controlled.

When the chip enable signal CE is set to the high level, the semiconductor integrated circuit device is set to the operation mode, and the chip enable signal CE is input to the second signal voltage level conversion circuit LV4P for PMOS. The output signal is input to the second buffer logic circuit (or the second buffer logic circuit and the second waveform shaping inverter circuit) L0G4P. Then, the voltage Vnw for controlling the potential of the N-well, which is the back gate electrode of the PMOS formed in the all-purpose module in the semiconductor integrated circuit, is formed by the L0G4P, and is input to the functional module. Further, the voltage Vpw (power supply voltage Vdd2) for controlling the potential of the P-well is also input to the first signal voltage level conversion circuit LV4N for the NMOS via the P-well. Since only the substrate bias control circuit is used, the N-type power supply of PMOS is supplied with the power supply of system 1 Vdd 1 (for example, 3 V) and the power supply of system 2 Vdd 2 (3 V) at the same potential, The same 1-system power supply Vssl (for example, 0 V) as the source electrode of NMOS is applied to the well. Thus, when the same potential is applied to the source electrode and the back gate electrode of the MOS transistor, the subthreshold characteristics of the MOS transistor are shown in Figs. 32 (a) and 32 (b). The state changes to state P1 and state N1, in which the threshold voltage of the MOS transistor is low in absolute value and the drain current is high.

On the other hand, when the chip enable signal CE is at the mouth level, the semiconductor integrated circuit device is set to the standby mode, and the second signal voltage level conversion circuit for the PMOS and the second buffer logic circuit or the second The voltage Viiw (power supply voltage Vdd2), which controls the N-level potential by performing the signal formation described above by the buffer logic circuit and the second waveform-shaping inverter circuit, functions via the N-level, respectively. The signal is input to the module and also to the substrate bias control circuit for PM〇S.

In other words, Vdd2 (for example, 5 V) having a higher potential than the 1-system power supply Vddl (for example, 3 V) is applied to the N-well of the PMOS, and the above-mentioned 1-system power supply Vssl (0 V) is applied to the NMO of the PMOS. Is applied.

In this way, when a high potential voltage is applied to the back gate electrode with respect to the source electrode of PMOS, the subthreshold characteristic of PM 、 S becomes the state P2 or P2 shown in FIG. In this state, the NMOS subthreshold characteristic does not change, but the absolute value of the threshold voltage of the PMOS transistor is high and the off-current is very small.

Therefore, when the semiconductor integrated circuit device is in the operation mode, it has a high drive type MOS transistor characteristic. Conversely, when the semiconductor integrated circuit device is in the standby mode, only the PM〇S is a low power consumption type MOS transistor. Characteristics.

Similarly to FIG. 26 (b), FIG. 28 (b) shows that the chip enable signal CE and the sleeve mode control signal SM or the power down signal PD generated in the semiconductor integrated circuit device are generated. The signal input to the selector circuit SEL 1 is output from the selector circuit SEL 1 to the signal voltage level conversion circuits LV 5 to 7 and the buffer logic circuit (logic circuit and waveform shaping inverter circuit) LOG 5 to 7 The respective functional modules in the semiconductor integrated circuit device are switched to an operation mode and a standby mode, respectively, by being input to the respective devices. And Fig. 28 (b) is Similarly to the above, the semiconductor integrated circuit device includes a substrate bias control circuit in which a 1-system power supply Vddl and Vssl and a 2nd-system power supply Vdd 2 having the same potential or a different potential from the 1-system power supply Vddl are formed. I have. Also in this case, the control of the back gate potential of the PM〇S is performed by supplying the voltages Vnwl〜3 and the voltages Vpwl〜3 to the respective functional module wells, as described above, for each functional module.

As described above, in the present embodiment, the control of the N-well potential for controlling the back gate potential of the PMOS using the substrate bias control circuit for the PMOS has been described with an example. Alternatively, it is also possible to control the back gate potential of the NMOS, that is, control the potential of the P-well, by using the NMOS via bias control circuit. Also in this case, the same operation and effect as the case where the present invention is applied to the above-described PMOS substrate bias control circuit can be obtained.

In this case, as described above, the control of the back gate electrode of the PMOS can be controlled for each functional module, and the MOS transistor structure of the semiconductor integrated circuit device is shown in FIG. 28 (c). Will be able to

The MOS transistor structure in the functional module shown in Fig. 28 (c) requires a triple-well structure to separate both the NM0S P-well and the PMOS N-well from the substrate of the semiconductor integrated circuit device. And not. For example, when the substrate SUB 3 of the semiconductor integrated circuit device is a P—substrate, the back gate electrode is controlled only by the N-level IS 5 on which the PM 0 S is formed. Therefore, the semiconductor shown in FIG. In the integrated circuit device, it is not necessary to separate both the P-well PWEL3 and the N-well NWEL 3 from the substrate of the semiconductor integrated circuit device.

Conversely, in the semiconductor integrated circuit device shown in FIG. 28 (c), when the substrate SUB 3 is a substrate, the 1-system power supplies Vddl and Vss 1 and the 1-system power supply Vss 1 have the same potential or different potentials. By providing the substrate bias control circuit in which a certain secondary power supply Vss2 is formed, the back gate electrode is controlled only in the PWell PWEL3 in which the NMOS is formed. Therefore, as shown in FIG. 28 (c), it is not necessary to separate both the P-well PWEL3 and the N-well NWEL3 from the substrate of the semiconductor integrated circuit device.

As described above, according to the semiconductor integrated circuit device of the present embodiment, power supply wiring and connection By limiting the new power supply wiring for controlling each back gate electrode of PMOS and NMOS which is different from the potential of the ground wiring to one of them, high-speed operation can be performed without changing the MOS transistor structure. This has the effect of simultaneously realizing power consumption during standby and standby.

Whether to control the back gate of both NMO S and PM〇 S or the back gate of the negative MOS transistor should be selected at the design stage according to the product specifications. Is also possible. For example, when controlling the back gate of only PM〇S, the manufacturing cost can be reduced. Also, in the design stage, only functional modules that require back gate control are selected according to product specifications and the like, and only the functional modules described above are formed with a well, and both or one of the MOS transistors of NMOS and PMOS are used. The backgate can also be controlled.

15th embodiment>

FIG. 29 shows a power supply wiring layout of the semiconductor integrated circuit device according to the fifteenth embodiment of the present invention.

FIG. 29 (a) shows that, in the ninth to 12th embodiments described above, the first metal is extended in the channel length direction of the MOS transistor supplied to a plurality of basic cell groups arranged in a matrix. A first-system power supply wiring Vddl and Vss 1 formed by a wiring layer; and a second-system power supply formed by a second metal wiring layer extending above the first metal wiring layer and extending in the channel width direction of the MOS transistor. The power supply wiring ratios of the wirings Vdd 2 and Vss 2 are shown.

On the other hand, FIG. 29 (b) shows that the 1-system auxiliary power supplies Vdd1,, Vss1 'for the 1-system power supply wirings Vdd1, Vss1, and the 2nd-system auxiliary power supply Vdd2, , Vss2 ′ are shown in the wiring layout.

The 1-system auxiliary power lines Vdd 1 ′ and Vss 1 ′ extend in the channel width direction of the MOS transistor and are formed by a second metal wiring layer, and are similar to the 2 system power lines Vdd 2 and Vss 2. In addition, they are arranged and wired in the wiring grid on the MOS electrode of the MOS transistor.

The 2nd system auxiliary power supply wiring Vdd2, Vss2, is the channel of the M0S transistor. It is extended in the longitudinal direction and is formed by a third metal wiring layer above the second metal wiring layer, and is wired on an arrangement grid not used for signal wiring by the third metal wiring layer. .

The first-system auxiliary power supply wiring and the second-system power supply wiring prevent a voltage drop inside the semiconductor integrated circuit device, particularly at the center, against the first- and second-system potentials supplied from the outside.

FIG. 30 shows a method of forming a MOS transistor in a semiconductor integrated circuit device according to the sixteenth and seventeenth embodiments of the present invention. By using one or both of the NMOS substrate bias control circuit and the PMOS substrate bias control circuit of the thirteenth and fourteenth embodiments described above, When dynamically controlling power consumption and speed optimally, MOS transistors must be formed in semiconductor integrated circuit devices that place importance on increasing the speed of functional modules, and in semiconductor integrated circuit devices that place importance on reducing power consumption of functional modules. It is desirable to divide the method clearly.

The semiconductor integrated circuit device shown in FIG. 30 (a) is a semiconductor integrated circuit device according to the thirteenth embodiment of the present invention, and particularly a semiconductor integrated circuit device which emphasizes high-speed function modules.

For example, a semiconductor constituted by a functional module forming region constituting a predetermined functional module, and an input / output circuit forming region (peripheral circuit forming region) I 0 which interfaces input / output signals of the functional module with an external device. In integrated circuit devices, the threshold voltage of the M0S transistor formed in the input / output circuit formation area where high-sensitivity input circuits and high-drive-capacity output circuits are formed depends on noise suppression and low power consumption. Therefore, the threshold voltage is formed at the first threshold voltage Vthl (for example, ± 0.7 V), which is higher in absolute value than the functional module formation area MO.

Then, the threshold voltage of the MOS transistor formed in the functional module forming area MO, which emphasizes high speed, is the first threshold voltage Vthl of the MOS transistor formed in the input / output circuit forming area I0. For example, it is formed at a second threshold voltage Vth2 (for example, ± 0.3 V) that is lower in absolute value than ± 0.7 V). When the functional module MO is set to the standby state, the potential of the back gate electrode of the MOS transistor formed in the functional module forming area MO is controlled, and the second threshold voltage Vth2 (for example, ± 0.3 V) is applied. Is also set to a third threshold voltage Vth3 which is high in absolute value (for example, ± 0.7 V which is the same as the first threshold voltage).

The semiconductor integrated circuit device shown in FIG. 30 (b) is a semiconductor integrated circuit device according to the fourteenth embodiment of the present invention, and particularly a semiconductor integrated circuit device which emphasizes low power consumption of functional modules. For example, a semiconductor integrated circuit device configured by a functional module forming area MO configuring a predetermined functional module, and an input / output circuit forming area I0 that interfaces input / output signals of the functional module with an external device, The threshold voltage of the MOS transistor formed in the input / output circuit formation area I0 where a high-sensitivity input circuit and an output circuit with high drive capability are formed is set to an absolute value from the viewpoint of noise suppression and low power consumption. It is formed with a first threshold voltage Vthl (for example, ± 0.7 V) that is high in value.

Similarly, the threshold voltage of the MOS transistor formed in the functional module formation area MO, which emphasizes low power consumption, is also the first threshold voltage of the MOS transistor formed in the input / output circuit formation area I0. Vthl (for example, ± 0.7 V), and when the functional module is set in the standby state, the potential of the back gate electrode of the MOS transistor formed in the functional module forming area M0 is controlled, and the first Is set to a second threshold voltage Vth2 (for example, ± 1.4V) that is higher in absolute value than the threshold voltage Vthl (for example, ± 0.7V) of the second threshold voltage.

As described above, the semiconductor integrated circuit device of the present invention controls the threshold voltage by the substrate bias control circuit, thereby controlling the gate potential of the MOS transistor, realizing products with various specifications with low power consumption. The functional module can be applied to, for example, digital integrated circuits such as SRAMs and gate arrays.

Claims

Range of request

1. In a semiconductor integrated circuit device having a functional module including a transistor of a first conductivity type and a transistor of a second conductivity type,

A control signal is applied to the gate electrode, on / off is controlled, and the source electrode is connected to a second power supply having a higher potential than the first power supply.

A second electrode in which a gate electrode is controlled by an inversion signal of the control signal, ON / OFF is controlled exclusively with the first first conductivity type transistor, and a source electrode is connected to the second power supply. A transistor of the first conductivity type;

A source electrode is connected to a third power supply having a lower potential than the first power supply, and is turned on based on the operation of the second first conductivity type transistor and the operation of the first first conductivity type transistor. A first second-conductivity-type transistor whose / off is controlled, and a source electrode connected to the third power supply, and the operation of the first first-conductivity-type transistor and the second first-conductivity transistor A second second conductivity type transistor whose on / off is controlled based on the operation of the transistor;

The first first conductivity type transistor and the first second conductivity type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power source. A third first conductivity type transistor having an electrode connected to the drain electrode of the first first conductivity type transistor;

A first electrode of the first conductivity type and a transistor of the first second conductivity type are interposed in series and interposed between the first and second transistors, and a gate electrode is connected to the first power supply and a source electrode Is connected to a drain electrode of the first second conductivity type transistor, and a third second conductivity type transistor whose drain electrode is connected to the drain electrode of the third first conductivity type transistor;

The second first conductivity type transistor and the second second conductivity type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power source and a source electrode Is connected to the drain electrode of the second transistor of the first conductivity type. A fourth transistor of the first conductivity type,

When the second first conductivity type transistor and the second second conductivity type transistor are connected in series and interposed therebetween, and a gate electrode is connected to the first power supply, In both cases, the source electrode is connected to the drain electrode of the second second conductivity type transistor, and the drain electrode is connected to the drain electrode of the fourth first conductivity type transistor. A first signal electrode including a transistor of the second conductivity type if: a level conversion circuit;

A first logic circuit that buffers an output signal of the first signal voltage level conversion circuit and controls a back gate electrode of a first conductivity type transistor that constitutes the functional module. Including a substrate bias control circuit,

In the first signal voltage level conversion circuit, a drain electrode of the first second conductivity type transistor and a source electrode of the third second conductivity type transistor may be connected to the second second conductivity type. The drain electrode of the second second conductivity type transistor and the source electrode of the fourth second conductivity type transistor are connected to the gate electrode of the transistor, and the gate electrode of the first second conductivity type transistor is connected to the gate electrode of the first second conductivity type transistor. A semiconductor integrated circuit in which a flip-flop is formed by a feedback loop comprising a first second conductivity type transistor and a second second conductivity type transistor connected to a single electrode.

2. In Claim 1,

The substrate bias control circuit may be configured such that the first, second, third, and fourth transistors of the first conductivity type are formed in the same region of the second conductivity type pail region, and the second conductivity type pail region is formed in the same region. The first electrode of the first, second, third, and fourth transistors is connected to the second power supply or a fourth power supply having a higher potential than the second power supply. Are formed in the same region of the first conductivity type peg region, and the first conductivity type peg electrode is connected to the third power supply. apparatus.

3. In Claim 1 or 2, The substrate bias control circuit may be configured such that the first and second transistors of the second conductivity type are formed in the same first region of the first conductivity type in the same region, and the transistor of the first first conductivity type is A third electrode of a second conductivity type is formed in a second first conductivity type of the transistor region; and a second first conductivity type of the transistor is connected to the third power supply. The third second conductivity type transistor is connected to a source electrode of the third second conductivity type transistor; the fourth second conductivity type transistor is formed in a third first conductivity type well region; A semiconductor integrated circuit device having the first signal voltage level conversion circuit, wherein a gate electrode of a first conductivity type plug region is connected to a source electrode of the fourth second conductivity type transistor.

4. In any one of claims 1 to 3,

The first signal voltage level conversion circuit may be configured such that at least one of the third and fourth second conductivity type transistors has a channel length of the first and second second conductivity type transistors. A channel width of at least one of the third and fourth transistors of the second conductivity type is smaller than a channel length of the first and second transistors of the second conductivity type. And the threshold voltage of at least one of the third and fourth second conductivity type transistors is smaller than that of the first and second second conductivity type transistors. A semiconductor integrated circuit device that satisfies one of the conditions of being formed with an absolute value lower than a threshold voltage.

5. In any one of claims 1 to 4,

In the first signal voltage level conversion circuit, a drain electrode of the first second conductivity type transistor, a source electrode of the third second conductivity type transistor, and the second second conductivity type A first output terminal of the first signal voltage level conversion circuit connected to the gate electrode of the second transistor, or a drain electrode of the second second conductivity type transistor and the fourth second conductivity type A second output terminal of the first signal voltage level conversion circuit, to which the source electrode of the transistor of the first type and the gate electrode of the transistor of the first second conductivity type are connected, comprises the first power supply and the second power supply. Discuss in the third power Semiconductor integrated circuit connected to an input terminal of the first logic circuit whose logical amplitude is defined

6. In Claim 5,

The substrate bias control circuit may include an output signal of the first logic circuit whose logic amplitude is defined by the first power supply and the third power supply, wherein the first signal voltage level conversion circuit and the first signal voltage level conversion circuit Is connected to the first conductivity type pail region of the other function module formation region instead of the region where the logic circuit is formed, and the potential of the back gate electrode of the second conductivity type transistor constituting the function module is controlled. Semiconductor integrated circuit device.

7. In Claim 5,

The substrate bias control circuit includes a back gate electrode of the first conductivity type transistor constituting the first logic circuit having a logic amplitude defined by the first power supply and the third power supply. A semiconductor integrated circuit device connected to the second turtle source or a fourth power supply having a higher potential than the second power supply.

8. In Claim 5,

The substrate bias control circuit includes a back gate electrode of the first conductivity type transistor constituting the first logic circuit having a logic amplitude defined by the first power supply and the third power supply. Wherein the semiconductor integrated circuit device is connected to the first power supply having the same potential as a source electrode of the first conductivity type transistor.

9. In Claim 5,

The substrate bias control circuit has a first inversion logic circuit for waveform shaping, and the first output terminal or the second output terminal of the first signal voltage level conversion circuit has the first waveform shaping first circuit. A human input terminal of the inverted logic circuit is connected, an output terminal is connected to an input terminal of the first logic circuit, a logic amplitude is defined by the first power supply and the third power supply, and Any of the following conditions: a larger channel length, a smaller channel width, and a higher threshold voltage than the first conductivity type transistor that constitutes the logic circuit 1 A semiconductor integrated circuit device having a first inversion logic circuit for waveform shaping including a first conductivity type transistor formed by the method described above.

10. A semiconductor integrated circuit device having a functional module including a transistor of the first conductivity type and a transistor of the second conductivity type,

A first second conductivity-type transistor in which a control signal is applied to a gate electrode to control on / off and a source electrode is connected to a first power supply;

A second electrode in which a gate electrode is controlled by an inverted signal of the control signal to control ON / OFF exclusively from the first second conductivity type transistor, and a lease electrode is connected to the first power supply. A transistor of the second conductivity type;

A source electrode is connected to a fourth power supply, and a first electrode whose on / off is controlled based on the operation of the transistor of the second second conductivity type and the operation of the transistor of the first second conductivity type A first conductivity type transistor;

A source electrode is connected to the fourth power supply, and a second second electrode whose on / off is controlled based on the operation of the first second conductivity type transistor and the operation of the second second conductivity type transistor 1 conductivity type transistor,

The first second conductivity type transistor and the first first conductivity type transistor are interposed in series and interposed, and a gate electrode has a higher potential than the first power supply; A third second conductivity type transistor connected to a second power source having a lower potential than the fourth power source and having a source electrode connected to a drain electrode of the first second conductivity type transistor When,

The transistor is connected in series between the transistor of the first second conductivity type and the transistor of the first first conductivity type, and has a gate electrode connected to the second power source and a source. A third first conductivity type transistor having an electrode connected to the drain electrode of the first first conductivity type transistor, and a drain electrode connected to the drain of the third second conductivity type transistor;

The transistor is connected in series between the second second conductivity type transistor and the second first conductivity type transistor, and has a gate electrode connected to the second power source and a source. An electrode is connected to the drain electrode of the second second conductivity type transistor. A fourth transistor of the second conductivity type,

The second second conductivity type transistor and the second first conductivity type transistor are connected in series and interposed between the second second conductivity type transistor and the second first conductivity type transistor, and have a gate electrode connected to the second power supply and a source electrode. Is connected to the drain electrode of the second first conductivity type transistor, and the fourth first conductivity type transistor is connected to the drain electrode of the fourth second conductivity type transistor. A second signal voltage level conversion circuit including:

A second logic circuit that buffers an output signal of the second signal voltage level conversion circuit and controls a back gate electrode of a second conductivity type transistor that forms the functional module. Including a bias control circuit,

In the second signal voltage level conversion circuit, a drain electrode of the first first conductivity type transistor and a source electrode of the third first conductivity type transistor may be connected to the second first conductivity type transistor. A drain electrode of the second first conductivity type transistor and a source electrode of the fourth first conductivity type transistor connected to a gate electrode of the transistor; A semiconductor integrated circuit device connected to a gate electrode, wherein a flip-flop is formed by a feedback loop formed by the first first conductivity type transistor and the second first conductivity type transistor.

1 1. In claim 10,

The substrate bias control circuit may be configured such that the first, second, third, and fourth transistors of the first conductivity type are formed in a second conductivity type pail region in the same region, and the second conductivity type pail is provided. A well electrode in the region is connected to the fourth power supply; the first, second, third, and fourth transistors of the second conductivity type are formed in the first conductivity type well region in the same region; A semiconductor integrated circuit device having the second signal voltage level conversion circuit in which a gate electrode in a first conductivity type plug region is connected to the first power supply or a third power supply having a lower potential than the first power supply; .

1 2. In claim 10 or 11, The substrate bias control circuit may be configured such that the first and second first-conductivity-type transistors are formed in a first second-conductivity-type well region in the same region, and the first and second-conductivity-type wells are formed. A third electrode of the third conductive type is formed in a second conductive region of the second conductive type, and a second conductive type of the second conductive type transistor is connected to the fourth power supply; A well electrode of the region is connected to a source electrode of the third first-conductivity-type transistor, and the fourth first-conductivity-type transistor is formed in a third second-conductivity-type well region; A semiconductor integrated circuit device having the second signal voltage level conversion circuit in which a third second conductivity type plug electrode is connected to a source electrode of the fourth first conductivity type transistor.

13. In any one of claims 10 to 12,

The second signal voltage level conversion circuit may be configured such that at least one of the third and fourth first conductivity type transistors has a channel length of the first and second first conductivity type transistors. A channel width of at least one of the third and fourth first conductivity type transistors is smaller than a channel width of the first and second first conductivity type transistors. And the threshold voltage of at least one of the third and fourth transistors of the first conductivity type is smaller than the threshold voltage of the first and second transistors of the first conductivity type. A semiconductor integrated circuit device that satisfies one of the conditions of being formed with a lower absolute value.

14. In any one of claims 10 to 12,

In the second signal voltage level conversion circuit, a drain electrode of the first first conductivity type transistor, a source electrode of the third first conductivity type transistor, and the second first A first output terminal of the second signal voltage level conversion circuit connected to a gate electrode of a conductive type transistor, or a drain electrode of the second first conductive type transistor and the fourth The second output terminal of the second signal voltage level conversion circuit to which the source electrode of the one conductivity type transistor is connected to the gate electrode of the first first conductivity type transistor is the fourth output terminal. A power supply and the second power supply A semiconductor integrated circuit device connected to an input terminal of the second logic circuit whose logic amplitude is defined.

1 δ. In claim 14,

The substrate bias control circuit may include an output signal of the second logic circuit whose logic amplitude is defined by the fourth power supply and the second power supply, wherein the output signal of the second logic circuit is the second signal voltage level conversion circuit and the second power supply. The back gate electrode of the transistor of the first conductivity type, which is connected to the second conductivity type p-well region of the other function module formation area, instead of the area where the logic circuit is formed, has a potential A semiconductor integrated circuit device to be controlled.

1 6., 1 In claim 14,

The substrate bias control circuit includes a back gate electrode of a transistor of the second conductivity type that configures the second logic circuit having a logic amplitude defined by the fourth power supply and the second power supply. A semiconductor integrated circuit device connected to the first power supply or a third power supply having an absolute value lower than that of the first power supply;

17. In claim 14,

The substrate bias control circuit includes a back gate electrode of the second conductivity type transistor that configures the second logic circuit having a logic amplitude defined by the fourth power supply and the second power supply. A semiconductor integrated circuit device connected to the second power supply having the same potential as a source electrode of the second conductivity type transistor.

18. In claim 14,

An input terminal is connected to a first output terminal or a second output terminal of the second signal voltage level conversion circuit, an output terminal is connected to an input terminal of the second logic circuit, and the fourth power supply A logic amplitude is defined by the second power supply, and any one of a channel length, a small channel width, and a high threshold voltage larger than the second conductivity type transistor constituting the second logic circuit is used. the semiconductor integrated circuit device having a second inverting logic circuit for waveform shaping by the second conductivity type Bok transistor formed by ₍

1 9. In claim 1 or 10,

The first logic circuit or the second logic circuit is a semiconductor integrated circuit device formed by connecting a logic circuit having a small driving capability formed on an input side and a logic circuit having a large driving capability. .

20. In any one of claims 1 to 18,

The semiconductor integrated circuit device is formed on a substrate of a second conductivity type, and the first signal voltage level conversion circuit, the first logic circuit, or the first signal voltage level conversion circuit, The first signal voltage level conversion circuit, the first logic circuit, or the first signal voltage level conversion circuit, the first logic circuit, the first logic circuit, A semiconductor integrated circuit in which only the back gate electrode of the second conductivity type transistor is formed in the first conductivity type pail region which is not the region where the inverted logic circuit is formed but the other function module formation region. Circuit device.

2 1. In any one of claims 1 to 18,

The semiconductor integrated circuit device is formed on a substrate of a first conductivity type, the second signal voltage level conversion circuit, the second processing circuit or the second signal voltage level conversion circuit, the second signal voltage level conversion circuit; A logic circuit, the second inversion logic circuit, the second signal voltage level conversion circuit, the second logic circuit or the second signal voltage level conversion circuit, the second logic circuit, the second A semiconductor integrated circuit in which only the back-gate electrode of the first conductivity type transistor formed in the second conductivity type well region, which is the other function module formation region, not the region where the inverted logic circuit is formed, is controlled. Circuit device.

22. In a semiconductor integrated circuit device having a peripheral circuit including a function module forming region constituting a predetermined function module and an input / output circuit forming region for interfacing an input / output signal of the function module with an external device,

A threshold voltage of a transistor provided in the peripheral circuit formation region is a first threshold voltage. A threshold voltage of a transistor provided in the functional module formation region is a second threshold value which is lower in absolute value than the first threshold voltage of a transistor provided in the peripheral circuit formation region. When the functional module is set in a standby state, the potential of a back gate electrode of a transistor provided in the functional module forming region is controlled to be lower than the second threshold voltage. A semiconductor integrated circuit device set to a third threshold voltage that is high in absolute value.

23. In a semiconductor integrated circuit device having a peripheral circuit including a functional module forming region constituting a predetermined functional module and an input / output circuit forming region for interfacing an input / output signal of the functional module with an external device, A threshold voltage of a transistor provided in the function module area and the transistor provided in the input / output circuit formation area is formed at a first threshold voltage, and the function module is set in a standby state, thereby being provided in the function module formation area. A semiconductor integrated circuit device in which the potential of the back gate electrode of the selected transistor is controlled and set to a second threshold voltage having an absolute value higher than the first threshold voltage.

24. A plurality of basic cells each including a basic cell composed of a transistor of the first conductivity type and a transistor of the second conductivity type, and arranged in a matrix to form a predetermined functional circuit by changing wiring. A functional module composed of a cell group and an external device arranged around the functional module composed of the basic cell group described above and a peripheral circuit including an input / output cell group for interfacing input / output signals. In a semiconductor integrated circuit device having

The power supplied to the plurality of basic cell groups is supplied in a first metal wiring layer and a second metal wiring layer above the first metal wiring layer,

In the first metal wiring layer extended in a channel length direction of the first and second conductivity type transistors, the second power supply and a first power supply having a lower potential than the second power supply. Supplying power to the basic cell group,

In the second metal wiring layer extended in the channel width direction of the first and second conductivity type transistors, a fourth power supply having the same or higher potential as the second power supply; A semiconductor integrated circuit device for supplying a third power supply having the same potential or a low potential to the basic cell group as the first power supply.

25. In claim 24,

A power supply wiring for supplying the third power supply and the fourth power supply, formed by the second metal wiring layer extending in the channel width direction of the first and second conductivity type transistors; Is a semiconductor integrated circuit device arranged and wired on a wiring grid and a jewel electrode in a channel width direction of the first and second conductivity type transistors.

26. In claim 24 or 25,

The power supply of the fourth power supply to the second conductive type electrode of the transistor of the first conductive type by the second metal wiring layer is performed via a connection hole or the connection hole and the first metal wiring layer. The power supply of the third power supply to the first conductivity type gage electrode of the transistor of the second conductivity type by the second metal wiring layer is performed through a connection hole or the connection hole and the first metal wiring layer. Semiconductor integrated circuit device.

2 7. In claim 24,

The connection hole, which is connected to the well electrode on which the first and second conductivity type transistors are formed, is connected to the basic cell, and is connected to the first power supply wiring and the second power supply wiring. The first conductive type transistor and the gate electrode are disposed between power supply wirings and on the wiring grid adjacent to the first and second conductive type transistors in the channel width direction. A connection hole for connecting to the first power supply wiring is disposed, and the second conductivity type transistor is disposed on a wiring grid adjacent to the first and second conductivity type transistors in the channel width direction. A semiconductor integrated circuit device in which a connection hole for connecting a power electrode to the second power supply wiring is arranged.

28. In any one of claims 24 to 27,

The semiconductor integrated circuit device is formed on a substrate of a first conductivity type; A second power supply is supplied by a first metal wiring layer extending in a channel length direction of the first and second conductivity type transistors, and only a power supply line for supplying the fourth power supply is provided. Formed by the second metal wiring layer extending in the channel width direction of the first and second conductivity type transistors; or

The semiconductor integrated circuit device is formed on a substrate of a second conductivity type, and the first power source and the second power source are extended in a channel length direction of the first and second transistors of the second conductivity type. The second metal wiring layer, which is supplied in the first metal wiring layer and has only a power supply line for supplying the third power supply extending in a channel width direction of the first and second conductivity type transistors; Formed by

The first conductive type well on which the second conductive type transistor is formed or the second conductive type well on which the first conductive type transistor is formed is separated from the substrate of the semiconductor integrated circuit device. Circuit device.

29. A basic cell composed of a transistor of the first conductivity type and a transistor of the second conductivity type is provided, and a plurality of the basic cells arranged in a matrix form a predetermined functional circuit by changing wiring. A semiconductor integrated circuit comprising: a functional module constituted by a group; and a peripheral circuit including an input / output cell group arranged around the functional module constituted by the basic cell group and interfacing an external device with an input / output signal. In the circuit device,

The power supply supplied to the plurality of basic cell groups includes a second power supply and a first power supply having a lower potential than the second power supply, and a channel length direction of the first and second conductivity type transistors. A fourth power supply, which is supplied by a first metal wiring layer extended to a second power supply and has the same potential as the second power supply or a higher potential than the second power supply, and the same potential as the first power supply or A third power supply having a lower potential than the first power supply, a first auxiliary power supply for assisting the first power supply, and a second auxiliary power supply for assisting the second power supply; A third auxiliary power supply that extends in the channel width direction of the conductive transistor and is supplied by a second metal wiring layer above the first metal wiring layer, and further assists the third power supply; A fourth auxiliary power supply that assists the fourth power supply is a channel of the first and second conductivity type transistors. Extended Le length direction, and the second metal interconnect layer A semiconductor integrated circuit device supplied by a third metal wiring layer above the metal.

30. In claim 29,

The fourth power source, the third power source, the first auxiliary power source, and the second auxiliary power source are the second metal extended in the channel width direction of the first and second conductivity type transistors. Power is supplied to the basic cell group by a power supply wiring and an auxiliary power supply wiring formed in a wiring layer, and the power supply wiring is provided on a wiring grid in a channel width direction of the first and second conductive transistors and on a gate electrode. Integrated circuit arranged and wired

3 1. In claim 29,

The first auxiliary power source and the second auxiliary power source supplied by the second metal wiring layer formed to extend in the channel width direction of the first and second conductivity type transistors are: Connected to the first metal wiring layer to which the first power supply and the second power supply are supplied via a connection hole, and in a channel length direction of the first and second conductivity type transistors; The third auxiliary power supply and the fourth auxiliary power supply supplied by the extended third metal wiring layer are supplied with the third power supply and the fourth power supply through a connection hole. A semiconductor integrated circuit device connected to the second metal wiring layer.

3 2. In any one of claims 29 to 31,

A first integrated circuit device formed on a first electrical type substrate, wherein the first power source and the second electrical power source extend in a channel length direction of the i-th and second conductive type transistors; The fourth power source, the first auxiliary power source, and the second auxiliary power source only being supplied in a metal wiring layer and extending in a channel width direction of the first and second conductivity type transistors; Being supplied in a second metal wiring layer, and only the fourth auxiliary power source being supplied in a third metal wiring layer extending in a channel length direction of the first and second conductivity type transistors; or ,

The semiconductor integrated circuit device is formed on a substrate of a second conductivity type, and the first power supply and the second power supply are arranged in a channel length direction of the first and second conductivity type transistors. Only the third power supply, the first auxiliary power supply, and the second auxiliary power supply are supplied by the extended first metal wiring layer, and only the channel width of the first and second conductivity type transistors is provided. Supplied in the second metal wiring layer extended in the direction,

Further, the semiconductor integrated circuit device in which only the third auxiliary power supply is supplied by the third metal wiring layer extended in the channel length direction of the first and second conductivity type transistors.

33. In any one of claims 25 to 32,

The third power supply and the fourth power supply, which are supplied in the second metal wiring layer extended in the channel width direction of the first and second conductivity type transistors, or the second metal wiring The third power supply and the fourth power supply, which are supplied in layers, and a third metal wiring layer extending in the channel length direction of the transistors of the first and second conductivity types. The third auxiliary power supply and the fourth auxiliary power supply have potentials in response to a chip enable signal input from an external device or a sleep mode control signal formed in the external device or inside the semiconductor integrated circuit device. Is a semiconductor integrated circuit device that is controlled.

3 4. ^ In any of claims 25 to 33,

The third power supply and the fourth power supply, which are supplied by the second metal wiring layer extended in the channel width direction of the first and second conductivity type transistors, or the first and second power supplies The third auxiliary power supplied by the third metal wiring layer extended in the channel length direction of the transistor of the second conductivity type and the fourth auxiliary power are each functional module in the semiconductor integrated circuit device. Each power supply line or auxiliary power supply line is separated for each device, and a chip enable signal input from an external device or a sleep mode control signal formed inside the external device or the semiconductor integrated circuit device is supplied to one selector circuit. The semiconductor integrated circuit device to be input.