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WO1997031395A1 - Procede permettant de produire des bosses sur des plages de connexion de composants electroniques - Google Patents

Procede permettant de produire des bosses sur des plages de connexion de composants electroniques Download PDF

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Publication number
WO1997031395A1
WO1997031395A1 PCT/DE1997/000317 DE9700317W WO9731395A1 WO 1997031395 A1 WO1997031395 A1 WO 1997031395A1 DE 9700317 W DE9700317 W DE 9700317W WO 9731395 A1 WO9731395 A1 WO 9731395A1
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WO
WIPO (PCT)
Prior art keywords
solder
auxiliary carrier
chip
openings
pad
Prior art date
Application number
PCT/DE1997/000317
Other languages
German (de)
English (en)
Inventor
Hermann Bürk
Günter TRAUSCH
Original Assignee
Siemens Aktiengesellschaft
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Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1997031395A1 publication Critical patent/WO1997031395A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01067—Holmium [Ho]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0338—Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0726—Electroforming, i.e. electroplating on a metallic carrier thereby forming a self-supporting structure

Definitions

  • the invention relates to a method for the parallel production of bumps for the electrical contacting of components according to the galvano-transfer technique.
  • soldering and adhesive bonding are essentially used for the electrical connection to the relatively coarse structures of lines leading outwards.
  • Electronic components such as transistors, integrated circuits and surface wave filters are mounted on carriers and connected to each other via circuits via circuits. This can be done on printed circuit boards, on thick or thin layer circuits.
  • SMD technology Surface Mounted Device
  • COB technology Chip On Board
  • the chip In COB, the chip is mounted directly on the respective carrier without a housing, electrically contacted and protected by a plastic covering.
  • the electrical contact takes place via wire bonding or via tape automated bonding or by means of the flip-chip technology.
  • the latter technique on the one hand represents the most compact and most miniaturized assembly technique, but is usually technically complex and very expensive.
  • Some assembly methods work with solder balls, with which electronic components can be mounted directly on a carrier with corresponding electrical connection means.
  • the BGA Bit Grid Array
  • the semiconductor module is mounted on a carrier and is electrically contacted with it using any other technology
  • the semiconductor module is connected directly to a carrier via bumps.
  • C4 method a method with the name "ControUed Colapse Chip Connection” (C4 method) is known.
  • the substrate the chip
  • the stencil is difficult to adjust and fix for the vacuum process Relatively high and closely spaced bumps cannot be realized
  • Another possibility is the production of bumps by chemical metal deposition.
  • the surface is then made solderable by dip tinning.
  • the process is still in development.
  • the height of the bumps and their distance are limited by lateral separation.
  • the relatively hard hump requires great uniformity and planarity.
  • the deposition times are very long.
  • Another process is the so-called solder injection process.
  • a pressure pulse in a container, the base of which is designed as a perforated plate with the corresponding grid of the bump structure transfers liquid solder from the container to the pads (electrical connection spots), thus forming the bump structure.
  • Disadvantages are that only large pad divisions are possible.
  • the solder dosage and thus the hump height are uneven. The process is very prone to failure.
  • the invention has for its object to produce bump contacts au ⁇ Lot with a relatively large height safely, quickly and inexpensively simultaneously on one or more chips or entire wafers. This object is achieved by the features of claim 1.
  • the invention is based on the knowledge that it is applied in a special way to an auxiliary carrier Solder deposits with a predetermined volume can be transferred easily and reliably to a corresponding pad structure of a chip.
  • a closed metal layer is applied on one side to a flat, electrically non-conductive carrier plate. This is followed by an insulator layer with openings where the metal is exposed. The arrangement of the openings is a mirror image of the position of the metallic contact pads on the electronic component.
  • Solder is electrodeposited in the openings of the carrier plate, which is electrically contacted externally. This takes place with a thickness which is a multiple of the insulator thickness and whose volume corresponds to that of the bump to be produced.
  • the solder grows predominantly laterally from the edges of the insulator openings over the insulator. If the carrier plate is heated above the melting point of the solder, the solder withdraws from the non-wettable insulator surface. This is done in order to form a ball with the lowest surface energy. The solder rises far above its original height and strikes an opposite pad of the component, which is also heated to above the solder melting point. The solder wets the pad (spreads) and detaches from the previous adhesive surface on the carrier plate. The plate is then the galvanized for a further Lottransfer as ⁇ and so forth. The process is called galvano-solder transfer bumpmg or GSD bumpmg.
  • Particularly advantageous configurations consist, for example, in that the area of the pads is a multiple of the area of the openings m of the insulator layer on the auxiliary carrier.
  • the area of an opening is thus small against the area of a pad. This supports or simplifies the detachment of the solder material from the auxiliary carrier in the direction of the pads.
  • the support plate ie the flat auxiliary support
  • the support plate in its flat dimensions to be larger than the arrangement of the components to be soldered, such as wafers, ceramic plates, printed circuit boards or other.
  • the carrier is made of glass, for example, it can be adjusted relative to the component from above by means of alignment marks in the metal layer.
  • auxiliary support Composition, thermal expansion, flatness
  • it can be made of other materials, such as metal, ceramic or laminates. If it is made of metal, there is no need to produce a surface metallization and the back must be covered in an insulating manner.
  • the point of view in the selection of the carrier plate of the auxiliary carrier is, for example, thermal expansion relative to the component, flatness, service life and costs.
  • metallization is applied. This can be done by sputtering, vapor deposition or by chemical deposition. Since the metallization generally alloys with this when the solder is heated (remelting), the metallization in the insulator openings gradually dissolves and can be worn away after many transfer cycles. It is no longer possible to galvanically deposit in such openings. For the metallization, therefore, above all metals are to be used which are only slightly or not soluble in the solder and which have sufficient adhesive strength during the electrodeposition. Two or more layers can also be deposited one above the other. These fulfill different functions such as, for example, adhesive layer, conductive layer and diffusion barrier. Typical metal layer thicknesses in thin film technology are 2 ⁇ m.
  • Organic insulators are, for example, polyimide, benzocyclobutene or thermally stabilized photoresist. These materials are partly can be structured photolithographically. Commercially available solder resist lacquers and solder resist dry resist that can be structured photolithographically are also suitable. Inorganic dielectrics such as silicon dioxide or silicon nitride are also suitable. The Ormocers are a suitable mixed product. Combinations such as a photoresist mask for structuring SiO 2 with subsequent thermal stabilization are also conceivable.
  • Typical layer thicknesses for organic insulators are 4 ⁇ m, those for inorganic insulators 1 ⁇ m. Whether high-melting solders can be transferred usually depends on the temperature stability of the insulator.
  • the openings in the insulator can be chemically etched in a known manner, dry or wet, or can be produced with the laser. The quality requirements for the openings are low. So fluctuations in size, edge roughness and edge inclination have no significant influence.
  • the insulator surface provided with openings should be somewhat larger than that of the substrate. Outside of the carrier edge, a circumferential metallic surface would then be expedient for contacting in the galvanic bath and for shielding the active field from excessive uncontrollable current densities.
  • the openings in the insulator layer are usually round or square and have z. B. a diameter of 30 microns. If large solder volumes are transferred in relation to the pad area, very high bumps can be generated. The transferable amount of solder is limited by the distance between the pads if laterally growing solder bumps overlap too much on the carrier plate. If they grow together only slightly, the tear-off during melting still takes place without solder displacement according to the principle of a solder chain. If the pad division in one direction is too narrow, large amounts of solder can be deposited with little lateral growth by forming the insulator opening as a slot which is orthogonal to this direction. An advantage here are relatively short deposition times.
  • All of the electrodeposable metals such as tin, lead, indium and their alloys, which can be melted in a non-oxidizing environment, can be used as solder material.
  • the SnPb alloys mainly used in practice are well suited.
  • the cause of the elevation of the solder is the large surface area of the galvanic volume compared to the surface that is as tight as possible, the spherical surface. This energetically unfavorable state can change after the liquefaction by the formation of a solder ball.
  • the influence of gravity is irrelevant for the relevant volumes and depends on the density of the surrounding medium (oil or gas).
  • the solder When the ascending solder comes into contact with the wettable pad of the component, the solder spreads over the entire surface, whereby its height decreases compared to the previous ball diameter. If the distance between the auxiliary carrier and the component is large enough, the solder constricts over the insulator opening when the auxiliary carrier metallization is wetting and tears off by leaving a small amount. The solder volume transferred to the remaining one behaves approximately like the area of a pad on the component to the area of an insulator opening of the auxiliary carrier. If the distance is small, there remains a weak connection to the carrier plate, which can easily be broken off after solidification. While the solder is transferred to the substrate in the active area, it accumulates outside the shielding area of the carrier with every new galvanization. Excess and disruptive solder can be removed by briefly immersing the carrier in a solder bath.
  • auxiliary support and the component With regard to the positioning between the auxiliary support and the component, it should be noted that an exact adjustment is not absolutely necessary. It is sufficient if the ascending solder ball touches the corresponding pad somewhere.
  • the congruent adjustment before the solder transfer can be done via brands in a manner similar to that in photo lithography. A defined distance and parallelism can be achieved by briefly swiveling in reference balls and corresponding readjustments. Soft contact is also possible before remelting, a defined distance then being established depending on the pad size and solder volume. In this case, if the subcarrier and component are separated after the solder has solidified, you get leveled cusps. Defined distances are also achieved by means of distance sensors between the component (chip). A solder transfer in the liquid state can be implemented at distances above the height of the solder, in which the solder balls of the auxiliary carrier are detached either by impulse or by electrostatic charging of the auxiliary carrier by repulsion and accelerated as drops to the pads.
  • FIG. 1 shows a side view of a detail of a chip 1 and an auxiliary carrier 3 with solder balls 7, 8, 9 lying between them
  • FIG. 2 shows an arrangement with an elastic auxiliary carrier 3,
  • FIG. 3 shows a section III from FIG. 2.
  • the figure shows a section arranged at the top of a chip 1 (semiconductor component) with a pad 2 (electrical connection pad).
  • a section from an auxiliary carrier 3 is shown opposite on the underside.
  • the auxiliary carrier consists of a substrate, a metal layer 4 and an insulator layer 5.
  • a galvanic solder volume 7 was deposited on the auxiliary carrier 3 in a previous step. This solder volume has been deposited in a multiplicity of openings 6 in the isolator layer 5 and has been made very wide relative to the opening 6 or seen laterally.
  • the openings 6 are positioned corresponding to the pads 2, so that in the case of a plurality of pads 2 and openings 6 and in the opposite positioning between the chip 1 and the auxiliary carrier 3, an opening 6 is opposite to a pad 2.
  • electrodeposited solder volume 7 assume the shape with the lowest surface tension, so the dashed ball, the remelted solder volume 8 would result.
  • the distance 14 between chip 1 and carrier 3 is designed such that, in the event of remelting or melting, contact of the solder volume with pad 2 is achieved.
  • the solder has a tendency to completely wet this pad 2.
  • the height 12 of the galvanically separated solder volume 7 is thus changed by the theoretical solder elevation 13 such that a bump 9 with a height 15 is formed.
  • the method according to the invention can be implemented in the form of various variants.
  • solder Individual positions on substrates can be partially covered with solder by means of dispensable solder transfer (defined deposition volume). If the area to be tinned is large and not limited by dewetting areas, the solder spreads out a thin layer. If it is limited, the layer becomes adjustable in thickness, depending on the amount of solder transferred (in extreme cases, a spherical bump is formed). However, non-planar raised areas of any parts can also be partially soldered, provided that they are to be brought into contact with the unmelted solder 8 on the carrier plate 3 (e.g. tinning of tips).
  • bumps of different heights are formed depending on the area of the pads on components. Therefore, in the event that bumps of different heights have to be produced at the same time, the pad surfaces can be made of different sizes.
  • different solder volumes are deposited on insulator openings of different sizes in the auxiliary carrier, so that bumps of different heights can in turn be produced on pads of the same size.
  • Bumps on relief surfaces are often required.
  • the direct galvanic deposition with full-surface metallization in a vacuum, photoresist application and subsequent etching of the conductive layer is then often problematic.
  • the proposed method makes it possible to produce cusps at raised and depressed points.
  • An example of this is the use of the method in the production of surface wave filters which have a partial protective cover (laid-open specification WO 95/30276).
  • Bumps can be realized on the deep-lying pads 2, which protrude above the 100 ⁇ m high protective cover.
  • metal layer 5 dissolves in the solder
  • a 5 ⁇ m thick layer of nickel can be deposited on a 2 ⁇ m thick copper base. This is done so that in the case of very thin metal layers, after a large number of solder transfer processes, the carrier of the auxiliary carrier 3 is not to be exposed and thus lose the galvanic base.
  • the isolator openings are thus filled and easily monitored, so that the isolator edges are also protected against wear.
  • the conductive layer of the auxiliary carrier 3 can also consist of metals on which liquid solder is wetted, as long as it can be electrodeposited thereon. In such cases, the solder transfer takes place completely and the carrier plate can be separated from the chip 2 just as easily in the cooled state. In this case, it is not necessary for the insulator opening of the auxiliary carrier to be small against the pad surface of the component, so it can also be the same size or larger.
  • the metallization is wetting and the openings 6 in the insulator layer 5 are very much smaller than the area of the pads 2.
  • the solder volumes are stationary at the openings 6 through the wetting metallic surfaces until a transfer has taken place. This avoids short circuits due to detached, not yet transferred stray solder balls.
  • auxiliary carrier 3 only a part of the solder depot can be produced on an auxiliary carrier 3 by temporarily covering corresponding points before the galvanic deposition, for example with protective lacquer or adhesive tape. In this way, substrates can be partially provided with bumps.
  • the auxiliary carrier 3 does not necessarily have to be built up in layers, but it can also be made from commercially available semi-finished products, for example insulator-metal-insulators, by exposing the openings 6 and the outer region.
  • the openings 6 in the insulator 5 can be designed as slots. There is a risk that the mass of the liquid solder that wants to form into a ball will shift in an uncontrolled manner in the slot direction and the adjustment relative to the chip will be impaired.
  • the position of the solder ball can be defined by the slot having an extension at the appropriate point, for example a cross-shaped extension.
  • the Lottran ⁇ fer can also on small parts, for. B. individual components if they can be aligned and heated accordingly. In the case of components with low heat capacity, the heating can take place directly via the solder by heat transfer from the auxiliary carrier.
  • the auxiliary carrier 3 can be designed in such a way that it is firmly deposited with another flat plate during the galvanic deposition, takes over the shielding and contacting functions and is separated from the transfer plate before the solder transfer.
  • solder transfer can be carried out in two or more
  • Stages take place one after the other. Then support plates are used which have only a part of the openings and therefore have larger divisions. In individual cases, a large transfer carrier plate can be transferred to several wafers or substrates at the same time if the alignment is possible with sufficient accuracy. Additional approximate dimensions entered in the figure are the layer thicknesses of the insulator 17 and the metalization 18, which are low in relation to the total thickness of the auxiliary carrier 3 and thus represent surface coatings.
  • the theoretical diameter of an unmelted solder volume 8 is provided with the reference number 20. As a rule, the height 12 of the galvanic solder volume 7 is approximately equal to the lateral growth 10, 11 of this solder volume.
  • An auxiliary carrier 3 has, for example, the dimensioning of 4 "x 4".
  • the material is, for example, photo mask glass made of quartz. This has a thickness of 1.5 mm with a 2 ⁇ m thick nickel layer as the conductive layer or metal layer 4. There is a 4 ⁇ m thick, thermally stabilized layer of photoresist. Electroplated solder of the SnPb 63/67 type is deposited.
  • the height 12 of the galvanic solder volume 7 is approximately 100 ⁇ m, the diameter 19 of the opening 6 approximately 30 ⁇ m, the diameter 16 of the pad 2 approximately 200 ⁇ m.
  • a solder volume of approx. 3.1 x 10 6 ⁇ m 3 0.0031 mm * is deposited.
  • the later height 15 of the bump 9 is 128 ⁇ m.
  • the theoretical diameter 20 of the solder volume would be 182 ⁇ m.
  • the essential advantage of the invention lies, inter alia, in the possibility of simultaneously scoring a wafer consisting of a plurality of structured chips 2, in which the individual components have not yet been separated or separated.
  • solder bumps for example with intervals greater than or equal to 0.4 mm
  • metal stencils or masks for example with vapor-deposited with solder pastes using metal stencils or masks. Expensive processes such as their galvano-solder transfer are therefore of particular interest for narrow grids on the chip (pad grid), a dewetting surface of the metal layer 4 being unsuitable.
  • the increasingly used flip-chip technology for contact tion of components connected with a special connection layout This often requires solder bumps in a narrow grid (e.g. 0.15 mm). Since so-called "underfillers" are generally to be introduced between the chip and the substrate for stable fixation, the solder bumps must be relatively high.
  • the permissible fluctuation range of the distance is therefore 54 ⁇ m.
  • the exemplary embodiment relates to surface wave filters with a special 100 ⁇ m high passivation. In general, the hump height and thus also the permissible fluctuation range of the distance is significantly smaller.
  • the solder transfer from the auxiliary carrier 3 to the chip 1 is carried out with a flexible, elastically deformable variant of the auxiliary carrier 3.
  • spacing elements 21 are provided between the carrier plate 31 and the chip 1. The carrier plate 31 is pressed onto the chip 1 or onto the spacer elements 21.
  • the carrier plate preferably consists of a metal sheet with a thickness of 0.1 to 0.5 mm. Using sheets that are too thin increases the risk of dents and kinks occurring during handling. Hard and elastic metals, such as spring steel, are particularly suitable. Has the material already had the desired properties (nickel or platinum ... wettable) with regard to wettability with solder;
  • metal sheets it is often necessary thermal expansion are taken into account. Since this is usually several times higher than that of silicon as the wafer material for metals, the necessary heating of approximately 200 ° C. with large-area transfer leads to inadmissible interference of the congruence. It is therefore expedient to use, for example, nickel or platinum or an alloy with a high nickel content, such as an iron-nickel alloy. Such sheets can have a thermal expansion that is on the order of silicon.
  • a silicon wafer is suitable as a subcarrier base material with regard to thermal expansion.
  • the required elasticity is given for thin wafers, and handling is very difficult due to the risk of breakage.
  • the spacer elements 21 can, for example, consist of the same material as the insulator layer 5. This can be a thermosetting photoresist or a polyimide (up to approximately 50 ⁇ m thick). A solder resist or a solder film (up to approx. 150 ⁇ m) can also be used.
  • the spacer elements are arranged in as large a number as possible distributed over the auxiliary carrier 3. You can e.g. represent round or square islands or have a bar shape. If the chips 1 are densely occupied with connections, it is sufficient to place them over the sawing track.
  • the height of the spacer elements 21 is selected such that the conditions for the transfer distance described above in an example are met.
  • solder transfer when using a flexible auxiliary carrier 3 is described with reference to FIGS. 2 and 3: in order to apply the elastic auxiliary carrier 3 with all spacing elements 21 to the wafer or chip 1 to be processed simultaneously after the adjustment, it is expedient for the space to evacuate between the two parts. Due to the negative pressure applied or the external pressure acting, a constant pressure is then applied over the entire area is taken care of, since the elastic auxiliary carrier 3 is positioned accordingly.
  • the number of necessary spacing elements 21 per chip 1 or wafer 25 is variable. If, for example, a structured wafer 25 is fitted with solder bumps 9, which contains several hundred chips 1, a solder bump 9 is sufficient on or in the area of each chip.
  • the wafer 25 is placed on a support 26 (chuck).
  • the auxiliary carrier 3 is positioned above it with spacing.
  • the auxiliary carrier 3 and the support 26 are in indirect contact via the seal 22.
  • the resulting interior can be evacuated or refilled via a suction / pressure line 24.
  • a pressure ring 23 required for temporarily locking the auxiliary carrier 3 presses the auxiliary carrier 3 against the seal 22.
  • the detail III is shown in FIG. 3 in accordance with FIG. 2.
  • the auxiliary carrier 3 is pressed onto the spacing elements 21 from above, a predetermined spacing 14 corresponding to FIG. 1 being initially maintained.
  • the galvanic solder volume 7 is transferred to the pad 2 in the course of the method.
  • the pad 2 is on the chip 1.
  • the support 26 in FIG. 2 can be, for example, the upper part of an x / y table of an adjusting device. After adjusting and evacuating, the entire arrangement comes with a connected vacuum line, for example on a hotplate. In this respect, the heating is unproblematic because the heat transfer due to the initially cold support table prevents the wafer from heating up too quickly. If the heat conduction is not sufficient to heat the entire arrangement, then, for example, infrared heating can also be used from above. According to FIGS. 2 and 3, the auxiliary carrier 3 can be separated hot from the chip 1, ie when the solder is still liquid.
  • auxiliary carrier 3 If the auxiliary carrier 3 is slightly higher at the edges than the wafer or chip surface, it becomes so when it is put on of the negative pressure is deformed elastically and lifts off when the pressure is equalized after the transfer. Another possibility of lifting the auxiliary carrier 3 after the transfer in the active area is to press it into the area of the seal 22 with a pressure ring 23 and to place the previously evacuated interior space under an overpressure.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de transfert de volumes d'alliage d'apport, déposés par voie galvanique sur un support auxiliaire (3), qui sont transférés dans le cadre d'un processus de refusion sur des points de connexion de composants électroniques par l'intermédiaire d'une bosse d'alliage d'apport. Afin de garantir le transfert des volumes d'alliage d'apport et le décollement du matériau de soudage du support auxiliaire, le volume galvanique d'alliage d'apport est déposé essentiellement latéralement au-dessus d'une couche superficielle isolante du support auxiliaire, chacune des ouvertures de la couche isolante libérant une couche de métal située dessous et servant de base de galvanisation.
PCT/DE1997/000317 1996-02-23 1997-02-21 Procede permettant de produire des bosses sur des plages de connexion de composants electroniques WO1997031395A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19606816.9 1996-02-23
DE19606816 1996-02-23

Publications (1)

Publication Number Publication Date
WO1997031395A1 true WO1997031395A1 (fr) 1997-08-28

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Application Number Title Priority Date Filing Date
PCT/DE1997/000317 WO1997031395A1 (fr) 1996-02-23 1997-02-21 Procede permettant de produire des bosses sur des plages de connexion de composants electroniques

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TW (1) TW329035B (fr)
WO (1) WO1997031395A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11631650B2 (en) 2021-06-15 2023-04-18 International Business Machines Corporation Solder transfer integrated circuit packaging

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3719981A (en) * 1971-11-24 1973-03-13 Rca Corp Method of joining solder balls to solder bumps
EP0544305A2 (fr) * 1991-11-28 1993-06-02 Nitto Denko Corporation Procédé de fabrication d'un plot de contact utilisant un film composé
US5323947A (en) * 1993-05-03 1994-06-28 Motorola, Inc. Method and apparatus for use in forming pre-positioned solder bumps on a pad arrangement
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
DE4438098A1 (de) * 1993-10-28 1995-05-04 Hitachi Ltd Verfahren zum Herstellen leitender Höcker auf Leiterplatten
EP0685879A1 (fr) * 1994-05-31 1995-12-06 AT&T Corp. Procédé pour l'interconnexion d'un dispositif électronique en utilisant un support transmissible comme porteur de brasure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3719981A (en) * 1971-11-24 1973-03-13 Rca Corp Method of joining solder balls to solder bumps
EP0544305A2 (fr) * 1991-11-28 1993-06-02 Nitto Denko Corporation Procédé de fabrication d'un plot de contact utilisant un film composé
US5323947A (en) * 1993-05-03 1994-06-28 Motorola, Inc. Method and apparatus for use in forming pre-positioned solder bumps on a pad arrangement
US5388327A (en) * 1993-09-15 1995-02-14 Lsi Logic Corporation Fabrication of a dissolvable film carrier containing conductive bump contacts for placement on a semiconductor device package
DE4438098A1 (de) * 1993-10-28 1995-05-04 Hitachi Ltd Verfahren zum Herstellen leitender Höcker auf Leiterplatten
EP0685879A1 (fr) * 1994-05-31 1995-12-06 AT&T Corp. Procédé pour l'interconnexion d'un dispositif électronique en utilisant un support transmissible comme porteur de brasure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11631650B2 (en) 2021-06-15 2023-04-18 International Business Machines Corporation Solder transfer integrated circuit packaging

Also Published As

Publication number Publication date
TW329035B (en) 1998-04-01

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