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WO1997024655A1 - Disque a ram virtuel - Google Patents

Disque a ram virtuel Download PDF

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Publication number
WO1997024655A1
WO1997024655A1 PCT/US1996/019926 US9619926W WO9724655A1 WO 1997024655 A1 WO1997024655 A1 WO 1997024655A1 US 9619926 W US9619926 W US 9619926W WO 9724655 A1 WO9724655 A1 WO 9724655A1
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WO
WIPO (PCT)
Prior art keywords
memory
controller
disk
host processor
reserved
Prior art date
Application number
PCT/US1996/019926
Other languages
English (en)
Inventor
Michael J. Scharland
Armando D. Garbero
Stephen J. Ippolito
Original Assignee
Ipl Systems, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ipl Systems, Inc. filed Critical Ipl Systems, Inc.
Publication of WO1997024655A1 publication Critical patent/WO1997024655A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0662—Virtualisation aspects
    • G06F3/0664—Virtualisation aspects at device level, e.g. emulation of a storage device or system

Definitions

  • This invention relates generally to disk storage systems and, more particularly, to disk controllers used in disk storage systems.
  • a solid state disk is a solid state random access memory (RAM) that attaches to a host processor in a manner similar to that in which a magnetic hard disk drive attaches to a computer.
  • the solid state disk appears to the host processor as a magnetic disk memory except that data access times and data transfer rates of the solid state disk are relatively fast compared with the access times and transfer rates of magnetic disk drive memories because solid state memories do not require any mechanical movement when performing read or write operations.
  • One problem with solid state disks is that they are relatively expensive compared with magnetic disk or magnetic tape storage devices. Thus, it would be prohibitively expensive to provide an array of solid state disks.
  • Magnetic disk drive memories may be provided having a solid state random access memory (RAM), generally referred to as a cache memory.
  • Cache memories have a storage capacity which is relatively small compared with the storage capacity of a magnetic disk drive memory.
  • Cache memories on the other hand, have data access times which are relatively fast compared with the data access times of a disk drive.
  • LRU least recently used replacement
  • the cache memory is transparent to the host processor except that, as mentioned above, when the data is read from or written to the cache memory, the access time is less than the access time associated with a magnetic disk drive.
  • transparent means that the cache memory cannot be directly accessed by the host processor. Rather, the host processor issues a read or write request, and a disk controller or some other mechanism on a disk drive determines whether to satisfy the host request from the cache memory.
  • a disk array is intended to provide improved fault tolerance and performance compared tc several independent disk drives.
  • the disk array is typically coupled to the host processor through a disk controller.
  • the disk controller is coupled to the host processor through one or more host ports and to the hard disks of the disk array through one or more disk ports.
  • the disks in the disk array do not connect directly to the host processor, but rather are coupled to the host processor through a disk controller.
  • the disk controller typically includes a controller processor which executes firmware to control the flow of data between the host processor and the array of disks.
  • the controller may also include a controller memory which is typically provided as a solid state memory device and which can be used as cache memory to satisfy selected read and write requests directly in order to decrease the average data access time of a disk storage system. Such a cache memory, however, is transparent to the host processor.
  • the disk controller may allocate a portion of the cache memory to each of the disks in the disk array in accordance with a predetermined cache memory allocation scheme. For example, the disk controller may allocate equal memory portions of the cache memory to each of the ⁇ isks in the disk array. Alternatively, the disk controller may permanently allocate portions of the cache memory to contain data stored on particular locations of one or more hard disks. This technique is generally referred to as "pinning the cache” or “cache pinning.” Thus, with a cache pinning technique, data stored in specific locations of the disk drives are always also stored in the cache memory.
  • the host processor should be able to store particular data directly on the relatively fast storage medium.
  • a cache memory of a disk controller is transparent to the host processor, it is not suited for storage of data in write-intensive data processing applications because the host processor cannot directly access the cache memory of a disk controller.
  • the pinned cache technique is not ideal, since it is typically very inconvenient for a host processor to store data in specific locations on a hard disk to thus insure that the data is subsequently available in the pinned cache memory.
  • Solid state disks work well in write-intensive applications since a host computer can directly write data on the solid state disk, however, as mentioned above, a solid state disk is relatively expensive. It would, therefore, be desirable to provide a system which is relatively inexpensive and which allows a host processor to directly store data in, and retrieve data from, a memory having a data access time which is relatively short compared with a data access time of a magnetic disk drive.
  • a disk controller includes a controller processor and a controller memory having a plurality of memory locations with predetermined ones of the memory locations reserved for direct access by a host processor.
  • the reserved memory locations of the controller memory may be referred to as a RAMDISK.
  • the RAMDISK is configured such that it appears to the host processor as a solid state disk drive having a relatively small storage capacity. All read/write requests issued by the host processor and directed to the RAMDISK are thus satisfied via reserved memory regions within a solid state controller memory provided as part of a disk controller. Thus, the host processor need not read data from, or write data to, magnetic media such as a magnetic disk drive memory or a magnetic tape memory.
  • the net effect of providing a system having a RAMDISK is similar to providing a disk storage system having a cache memory which operates with a one hundred percent cache hit rate on both read and write operations.
  • the RAMDISK may be provided as a software-selectable option within the disk controller. If the RAMDISK option in the disk controller has been enabled, the controller memory locations reserved for use as a RAMDISK are allocated from available memory locations in the controller memory identified from a poll of memory available to the disk controller. It should also be noted that the size of the RAMDISK is also selectable and variable and is limited only by the amount of controller memory available to the disk controller. The data written to the RAMDISK device should preferably persist across power cycles (i.e. between power up and power down cycles of the disk storage system).
  • the disk controller Since the RAMDISK is provided from memory locations of a volatile memory within the disk controller, the disk controller periodically transfers or "flushes" data stored in the RAMDISK to magnetic media for permanent storage. Such transfers are preferably done at a frequency sufficient to ensure that all data will be available from the magnetic media after a power down and subsequent powerup of the disk storage system. In one embodiment, such data flushes are performed in response to an idle timer providing a signal after a predetermined period of time or in response to a command issued by the host processor.
  • the risk of losing data stored in the RAMDISK can be further reduced by providing either a continuous power source to the disk controller or by equipping the disk controller with a battery of sufficient strength to maintain power to the disk controller for a relatively short period of time thereby allowing a memory flush-to be performed in the event of an abnormal or forced powerdown condition of the disk controller or the disk storage system.
  • the data is flushed to a non-volatile disk or other non-volatile storage device rather than simply remaining in a battery powered volatile memory.
  • the data is permanently stored and the data integrity of the system is thereby improved.
  • the data may be spread evenly over all the disks in the disk array under control of the disk controller.
  • standard parity protection schemes e.g. RAID schemes
  • the host processor system can view the disks in the disk array as still having a uniform storage capacity.
  • mirroring or other techniques which require disks to have the same storage capacity may be used.
  • host configuration of the disks is relatively simple to accomplish.
  • the RAMDISK When configured, the RAMDISK appears to the host processor merely as another logical unit (LU) within an existing disk storage system which LU is coupled to a disk controller. However, unlike stand alone solid state disk drives, no additional hardware or issues of host system addressability (I/O adaptor, bus or identification resources) arise by the addition of the RAMDISK.
  • the RAMDISK is relatively easy to configure and implement in a disk storage system.
  • Cache memory schemes which make use of main storage inside the host processor system for I/O cache memories are generally limited by cost and the amount of available memory.
  • the RAMDISK storage By placing the RAMDISK storage external to the host processor, the amount of memory allocated to RAMDISK(s) within the system is both easily scaled and relatively inexpensive. Also, CPU processing overhead required for management of in-board caching schemes is eliminated.
  • cache pinning techniques it is desirable to control placement of data on a disk drive to ensure that the data is placed on a portion of the disk drive which is "pinned", thereby ensuring that the data will later be available in the cache memory. In many computer systems, however, control or visibility of data placement on a disk drive is limited or impossible and hence, "tuning" a cache memory to optimize performance (e.g. increase the number of cache hits) is relatively difficult.
  • the RAMDISK appears to the host processor as single disk drive having an assigned logical unit number and, thus, which is directly accessible by the host computer as if it were a disk drive in the disk array.
  • FIG. 1 is block diagram of a computer system having a disk controller and a disk storage system coupled thereto;
  • FIG. 2 is a flow diagram illustrating' the processing performed by a disk controller during an initialization procedure of a disk storage system
  • FIG. 3 is a flow diagram illustrating the processing performed by a disk controller to process read and write requests from a host processor
  • FIG. 4 is a flow diagram illustrating the processing performed by a disk controller to determine whether all information presently stored in a memory of the controller should be transferred to a disk.
  • a computer system 10 includes a host processor 15 having a disk storage system 16 coupled thereto.
  • Disk storage system 16 includes a disk controller 20 coupled to one or more of host ports 15a - 15N of host processor 15.
  • a disk array 28 having a plurality of magnetic disk drives 28a - 28N are coupled to the disk controller 20.
  • Disk controller 20 includes a controller processor 22, a nonvolatile memory 23 and a solid state controller memory 24.
  • Controller memory 24 may be provided, for example, as a dynamic random access memory (DRAM), a static RAM (SRAM) or any other type of memory. Controller memory 24 is preferably provided as a relatively inexpensive, relatively fast memory.
  • DRAM dynamic random access memory
  • SRAM static RAM
  • controller memory 24 A predetermined number of memory locations of controller memory 24 are reserved for direct access by host processor 15.
  • the reserved memory locations of controller memory 24 may be referred to as a RAMDISK 26.
  • the RAMDISK 26 provides controller 20 having a memory region which appears to host processor 15 as a disk drive having a relatively small storage capacity. Thus, the memory locations of RAMDISK 26 are directly accessible by host processor 15.
  • disk controller 20 Each read or write request issued by the host processor 15 and directed to RAMDISK 26 is satisfied by accessing solid state memory 24 within disk controller 20.
  • disk controller 20 need not access slower magnetic media such as a magnetic disk drives 28 or a magnetic tape memory.
  • the net effect of providing controller 20 with RAMDISK 26 is quite similar to providing a controller having a caching disk device which operates with one hundred percent-cache hit rates on both read and write operations.
  • the RAMDISK 26 may be provided as a software- selectable option within the disk controller 20.
  • disk controller 20 may be provided having a front panel which includes a display device (e.g. a liquid crystal diode (LCD)) and an input device.
  • LCD liquid crystal diode
  • controller initialization software may cause text to appear on the LCD display to query a user as to whether a RAMDISK option should be enabled. If a user indicates that the RAMDISK option should be enabled, then the user is further queried as to the desired size of the RAMDISK. As will be described in detail in conjunction with FIGs. 2 and 3, the controller processor 22 then performs those steps necessary to properly configure the RAMDISK with the host processor 5. Thus, the portions of memory 24 used to provide RAMDISK 26 are allocated and designated as RAMDISK only if a RAMDISK option has been selected by a user or by the host processor.
  • the size of RAMDISK 26 may be designated by a user via a front panel of a controller.
  • the selection of a RAMDISK option and size of the RAMDISK may be specified by host processor 15.
  • a host processor interface protocol would be established to allow host processor selection of the RAMDISK option.
  • the size of RAMDISK 26 is software-selectable and is limited only by the amount of memory available to the disk controller 20.
  • the disk controller memory 24 having a memory size of about one-hundred and twenty-eight megabytes (MB) RAMDISK 26 may be designated as having a size typically in the range of about eight to thirty-two MB.
  • RAMDISK 26 having a size up to one-hundred and twenty-eight megabytes MB (i.e. the same size as controller memory 24). In this case, controller memory 24 would not be available for storage of data other than specified by host processor 15. In those applications where less than all of the controller memory 24 is specified as RAMDISK memory, those portions of memory 24 not reserved as RAMDISK 26 may be used for general purpose read/write cache, general purpose I/O cache for other I/O disk drives in the disk array 28 or for any other conventional use.
  • the actual memory locations used to provide RAMDISK 26 are allocated by first polling memory 24 to identify available memory locations in memory 24 and then allocating predetermined ones of the available memory locations as RAMDISK memory locations.
  • the available memory locations of controller memory 24 reserved for RAMDISK operation are preferably contiguous memory locations but need not be contiguous memory locations.
  • Disk controller 20 is provided having three operating modes which will be described in detail below in conjunction with FIGs. 2-4. Suffice it here to say that disk controller 20 may operate in an initialization mode, a read/write request processing mode, and a data flush mode.
  • FIGs. 2 - 4 are a series flow diagrams showing the processing performed by disk controller 15.
  • the rectangular elements (typified by element 42), herein denoted
  • processing blocks represent computer software instructions or groups of instructions.
  • the diamond shaped elements (typified by element 40), herein denoted “decision blocks,” represent computer software instructions, or groups of instructions which affect the execution of the computer software instructions represented by the processing blocks.
  • the flow diagrams do not depict syntax of any particular programming language. Rather, the flow diagrams illustrate the functional information one skilled in the art requires to generate computer software or firmware to perform the processing required of disk controller 20. It should be noted that many routine program elements, such as initialization of loops and variables and the use of temporary variables are not shown
  • controller processor first determines if a RAMDISK option has been selected and the RAMDISK size specified. If the RAMDISK option has not been selected then processing in the initialization mode concludes in step 50 as shown.
  • the host processor is configured to allow direct access to the RAMDISK. Processing then continues to processing block 42 where an amount of memory equal to a requested RAMDISK memory capacity is reserved from an available memory pool of a controller memory. The reserved memory will be set aside for RAMDISK use while a disk array is coupled to the disk controller is operational. Provisions for the case where sufficient memory is not available are implementation-specific and will not be discussed here in detail. Suffice it to say that if a case arises where sufficient memory is not available for a RAMDISK of a desired size, then the host processor is informed that insufficient memory is not available and no RAMDISK memory is assigned.
  • a host image for the actual disk drives in the disk array is altered tcshow a reduction in available memory capacity.
  • the term "host image” refers to the appearance to the host computer of the disk drives in the disk array. That is, host image refers to the appearance the disk controller presents to the host processor of the disk drives in the disk array such as disk capacity, physical disk characteristics and any other parameters of the disk drives in the disk array .
  • the disk controller could provide this information to the host processor.
  • the disk controller could alternatively represent to the host processor that the disk array included sixteen disk drives with each of the sixteen disk drives having a one GB storage capacity.
  • the disk controller would be required to perform some logical to physical mapping between the host processor and the disk array in order to allow the host processor to properly access each of the eight disk drives.
  • the particular image the disk controller presents to the host processor depends at least in part on what processing is normally performed by the disk controller.
  • the amount of memory capacity by which the disk drives must be reduced corresponds to the amount of memory space allocated on each disk drive for the non-volatile storage of RAMDISK data and may be computed as:
  • SIZE NEW SIZE OR , GINAL - M/D in which: SIZE N ⁇ w corresponds to the apparent memory size of the disk drives to the host processor after allocation of the RAMDISK memory;
  • NAL corresponds to the actual memory size of the disk drives
  • M corresponds to the configured memory size of the RAMDISK memory
  • D corresponds to the number of disk drives in the disk array.
  • the configured RAMDISK memory capacity is divided equally among all of the disk drives in the disk array.
  • Each disk drive must be accessed during the initialization process to retrieve data stored in the memory portion of the disk drive reserved for storage of RAMDISK data.
  • the data is retrieved from the reserved memory area of the magnetic disk drive and stored in the reserved memory area of the controller memory reserved as the RAMDISK.
  • data may be retrieved from the RAMDISK and data from write operations of the host processor will be stored and/or updated in the RAMDISK and then flushed to the disk drives.
  • the information stored in the nonvolatile memory of the controller indicates that a RAMDISK was configured during a previous power up, then this indicates that the areas of the disk drives reserved for storage of RAMDISK data may contain data during the last operating period of the system. Thus, the data is read from the reserved areas of magnetic disk drives back into the RAMDISK.
  • the controller still reads the reserved areas of the magnetic disk drive memories, however, such memory areas will not contain any useful data.
  • the host processor should know that this RAMDISK has never been used before and thus the host processor may want to initiate write operations to the RAMDISK rather than read operations since no meaningful data would yet be stored in the RAMDISK.
  • Host processor and disk controller response to a case where a data retrieval operation fails is implementation-specific. A data retrieval operation may fail due to failure of one or more disk drives in the disk array upon power up or due to physical removal of a disk drive from the disk array.
  • an idle timer flag is reset and a dirty flag is set to a logical FALSE value.
  • the idle timer flag and dirty flag control a flush process by detecting appropriate points in time at which to perform RAMDISK flush operations based on activity and validity of data store in the RAMDISK. Specifically, the idle timer counts for a predetermined period of time and provides a signal which indicates whether data in the RAMDISK has been written to the disk array within that predetermined period of time.
  • the dirty flag indicates whether data stored in the RAMDISK has been modified since it was last written to the disk array. Thus the dirty flags indicate whether data stored in the disk array is valid (i.e. up to date).
  • the dirty flags can be used to track the validity of RAMDISK data in varying granularities. Choice of this granularity can be made based on RAMDISK size, size of the smallest modifiable unit of storage, amount of available memory, or other such criteria.
  • the disk controller can support 500 MB of cache, however, a relatively small amount of memory from the controller memory is reserved for use as a RAMDISK.
  • the RAMDISK may have a storage capacity in the range of about 8-32 MB. Thus in this embodiment only a single dirty flag is required for the entire RAMDISK.
  • a single dirty flag may be used to indicate whether any write operations have occurred to any memory locations of the RAMDISK.
  • the use of a single dirty bit works satisfactorily for a RAMDISK provided from a relatively small amount of memory because flushing of the RAMDISK can be done relatively quickly.
  • a plurality of dirty flags could be used. For example, if the RAMDISK were 32 MB of memory then it may be desirable to use four dirty flags with each of the four dirty flags representing an 8 MB portion of the 32 MB RAMDISK. Alternatively still, a dirty bit could be assigned for every 100 bytes of RAMDISK memory. Such an approach, however, would lead to a plurality of dirty bits and a concomitant complexity in tracking dirty bits and multiple flushing operations.
  • FIG. 3 shows processing performed by disk controller 20 while processing read and write requests from the host processor 15.
  • controller processor first determines if a read or write request has been received from host processor 15. When the disk controller detects a read or write request, processing continues to block 54 where the controller processor determines if the host processor request is directed to the RAMDISK.
  • processing continues to processing block 56 where the request is processed for the appropriate disk drive in the disk array.
  • processing continues to processing block 58 where the controller processor performs a mapping step to translate the data being addressed by the host processor into a corresponding location within the reserved memory area of the controller memory 24 (FIG. 1).
  • This mapping function is fairly implementation-specific, with the only requirement being that there exist a unique storage location for each host-addressable element of the RAMDISK.
  • the RAMDISK appears to the host processor as a block-oriented disk device having 512 bytes per block
  • the host processor accesses logical block address (LBA) 1
  • LBA logical block address
  • data from bytes 0 through 511 of the reserved memory area i.e. the RAMDISK
  • LBA 1 access to LBA 2
  • LBA 2 affects bytes 1024 through 1535 of the RAMDISK and so on.
  • LBA MAX ( Configured RAMDISK memory size / bytes per block) - 1
  • the RAMDISK appears to the host processor as a track-oriented disk device having 32 kilobytes (KB) per track, and the RAMDISK is not provided from contiguous memory locations of the controller memory but rather is provided from a plurality of 32 KB buffers from various memory locations of the controller memory, then in this case a pointer table entry should be generated which contains the address of a start buffer. An offset within the pointer table can then be defined as the host track number.
  • the controller processor determines the type of request issued by the host processor If decision is made that the host request corresponds to a write request, then processing continues to blocks 62 and 64 where the host data is received into a reserved memory area of a controller memory (i e. the RAMDISK) and a dirty flag is set to a logical TRUE value
  • the disk controller accepts data from the host into the appropriate memory area, and additionally identifies the memory area as dirty so that data stored in the memory area will be flushed to the sik array at an appropriate point in time.
  • processing continues to processing block 68 where an idle timer is reset to a predetermined timeout value. After the idle timer is set, the controller processor subsequently resumes checking for idle periods to flush data if necessary Referring now to FIG. 4, the processing steps performed in disk controller 15 to perform a flush operation are shown.
  • decision block 70 decision is made as to whether a host processor directed flush was received.
  • a host processor directed flush is the highest priority flush request (a possible exception to this is a system which has been equipped with a short-term battery to allow flushing in the event of a power failure).
  • Host-directed flushing provides the host processor with the ability to force all RAMDISK data to be backed up at logical boundaries within the host processing sequence (e.g. dismounting a database).
  • a host ordered flush typically occurs when the host processor determines that it will no longer access data stored in the RAMDISK.
  • processing flows directly to processing block 78 where a predetermined amount of data stored in the RAMDISK memory is transferred to each disk drive in the disk array.
  • the predetermined amount of data- is preferably of a size corresponding to M/D bytes where M is the configured size of the RAMDISK and D is the number of disk drives in the disk array. Processing then flows to processing block 80 where the dirty flag is set to a logical value of FALSE and processing again begins at decision block 70.
  • decision block 72 checks to see if an idle timer has expired. A flush request having a lower-priority than a host flush request results from the expiration of the idle timer. Expiration of the idle time which results in an idle timer flush request indicates that the host processor has not addressed the RAMDISK for a predetermined period of time.
  • the idle time period for flushing may be selected in accordance with a plurality of factors and a preferred idle time period may be different in different applications.
  • the idle time period may be select as one minute. This time period may be selected because typical computer systems do not shut down in less than one minute and battery back-up systems typically sustain disk subsystems for a period of time which is not less than one minute.
  • an idle time may also be selected based on performance of the computer system. For example, if a system performs many write operations every thirty seconds it may be desirable to set the idle time to thirty seconds.
  • the idle timer is immediately restarted and the dirty flags are scanned to determine whether any portions of the RAMDISK data in reserved memory are out of sync with the non-volatile copy of the RAMDISK data stored on the disk drives of the disk array. If any such portions are found, a flush operation will proceed, else the timeout condition will be ignored.

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  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
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Abstract

L'invention porte sur un contrôleur (20) de disque comportant un processeur (22) et une mémoire (24) à plusieurs emplacements de mémoire dont certaines sont réservées à l'accès direct par un processeur hôte. Cette disposition particulière permet d'obtenir un contrôleur (20) de disque doté d'une mémoire à circuits intégrés accessible à l'hôte pour un coût très inférieur à celui d'un disque à circuits intégrés. Les emplacements de mémoire réservées de la mémoire du contrôleur qui peuvent prendre l'appellation de disques à RAM (26), sont configurées de manière à apparaître au processeur hôte comme une unité de disque à circuits intégrés de capacité de stockage relativement faible. Toutes les demandes de lecture/écriture émises par le processeur hôte et dirigées sur le disque à RAM (26) sont satisfaites par les zones réservées d'une mémoire à circuits intégrés (24) du contrôleur (20). De ce fait, le processeur hôte ne doit ni lire ni écrire de données sur le support magnétique comme avec les mémoires (28, 28a, 28n) sur disques magnétiques ou sur bandes magnétiques. L'avantage net d'un système utilisant un disque à RAM (26) est semblable à celui d'une antémémoire à taux de présence en antémémoire de 100 % pour les opérations de lecture et d'écriture. Le disque à RAM (26) peut être offert comme option sélectionnable par logiciel depuis le contrôleur de disque (20), et s'ils sont validés, les emplacements sections de mémoire réservées pour servir de disque à RAM (26) sont attribuées à partir d'emplacements de la mémoire du contrôleur (24) disponibles, identifiés à partir d'une mémoire interrogeable cycliquement accessible au contrôleur de disque.
PCT/US1996/019926 1995-12-28 1996-12-27 Disque a ram virtuel WO1997024655A1 (fr)

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Cited By (3)

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US7949814B2 (en) * 2004-05-22 2011-05-24 Kam Fu Chan Swapping “fixed system” hard disk
CN104298619A (zh) * 2014-09-26 2015-01-21 北京控制工程研究所 基于Ramdisk和固态硬盘的高速二级存储系统及数据存取方法
EP1869557B1 (fr) * 2005-03-23 2017-09-27 Qualcomm Incorporated Indicateur global modifie pour reduire la consommation d'energie sur un cache-miss (absence d'informations dans le cache)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7949814B2 (en) * 2004-05-22 2011-05-24 Kam Fu Chan Swapping “fixed system” hard disk
EP1869557B1 (fr) * 2005-03-23 2017-09-27 Qualcomm Incorporated Indicateur global modifie pour reduire la consommation d'energie sur un cache-miss (absence d'informations dans le cache)
CN104298619A (zh) * 2014-09-26 2015-01-21 北京控制工程研究所 基于Ramdisk和固态硬盘的高速二级存储系统及数据存取方法

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