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WO1997019467A1 - Side trench isolation method using a two-component protective layer of polysilicon on silicon nitride for insulator layer planarisation by chemical-mechanical polishing - Google Patents

Side trench isolation method using a two-component protective layer of polysilicon on silicon nitride for insulator layer planarisation by chemical-mechanical polishing Download PDF

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Publication number
WO1997019467A1
WO1997019467A1 PCT/FR1996/001844 FR9601844W WO9719467A1 WO 1997019467 A1 WO1997019467 A1 WO 1997019467A1 FR 9601844 W FR9601844 W FR 9601844W WO 9719467 A1 WO9719467 A1 WO 9719467A1
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WO
WIPO (PCT)
Prior art keywords
layer
attack
mechanical polishing
substrate
insulating material
Prior art date
Application number
PCT/FR1996/001844
Other languages
French (fr)
Inventor
Pierre Brouquet
Claude Masurel
Maurice Rivoire
Original Assignee
France Telecom
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR9513917A external-priority patent/FR2741749B1/en
Priority claimed from FR9513916A external-priority patent/FR2741748B1/en
Application filed by France Telecom filed Critical France Telecom
Publication of WO1997019467A1 publication Critical patent/WO1997019467A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step

Definitions

  • the invention relates to the electrical isolation of electronic components.
  • the invention will be more particularly described with respect to the lateral isolation of the active areas of a semiconductor substrate. It is understood that the invention is not limited to this application and that it can also be implemented for other applications.
  • a suitable technique for leveling the insulation is chemical mechanical polishing.
  • the quality of the electrical insulation of the semiconductor devices obtained by implementing planarization by chemical mechanical polishing has been insufficient.
  • defect effect This is a significant recess in large unmasked areas and large trenches, while the insulating material has not yet been removed entirely on certain predetermined masked areas. It can thus appear after polishing, two types of defect on the substrate: recesses in the insulation zones sometimes accompanied by a consumption of part of the substrate, and insulation residues on the predetermined zones. These defects considerably lower the quality of the electrical insulation of the semiconductor devices manufactured. Furthermore, the presence of oxide residues on the predetermined areas gives rise to additional disadvantages when the protective layer is made of silicon nitride. Indeed, the presence of oxide on the layer of silicon nitride generates the formation of a silicon oxynitride very difficult to attack. This effect is commonly called the KOOI effect. The protective layer can then only be difficult to remove so that the future active areas undergoing this effect are not easily accessible, for example, for subsequent implantation.
  • the object of the invention is to provide an effective leveling of the insulating layer by correcting the aforementioned defects, thus leading to a isolation of active areas by lateral trenches ensuring good quality of electrical insulation.
  • the invention provides a method of electrically isolating the active regions of an electronic component formed on a semiconductor substrate, comprising isolating the active regions of a semiconductor substrate by lateral trenches in which, a) is deposited a protective bilayer on the semiconductor substrate before defining the zones intended to subsequently form the active zones of the electronic component, this bilayer consisting of a stack of a lower layer of silicon nitride and of an upper layer of polycrystalline silicon, b) trenches are arranged within the semiconductor substrate arranged laterally relative to the predetermined areas of the substrate intended to subsequently form the active areas, c) is deposited, in the trenches and on the predetermined areas of the substrate covered with the protective bilayer, a layer of insulating material, and d) a flattening of the semi block is carried out conductor by a single mechanical-chemical polishing step of the insulating material so that the attack speed of the polycrystalline silicon is greater than that of the insulating material and so that the silicon nitride of the lower layer
  • the material of the lower layer of the protective bilayer has an attack speed during the chemical mechanical polishing of step d), lower than that of the insulating material. This last feature provides increased protection of predetermined areas of the substrate during polishing.
  • the attack speed of the polycrystalline silicon of the upper layer of the protective bilayer differs from that of the insulating material by at least a factor 10.
  • the planarization step of the insulating material by chemical mechanical polishing can advantageously be assisted by an end of attack detection taking place at least on the upper polycrystalline silicon layer of the protective bilayer, then acting as a layer stopping the chemical mechanical polishing.
  • the attack speed of the polycrystalline silicon of the upper layer of the protective bilayer can also differ sufficiently, preferably by at least a factor of 10, from that of the silicon nitride of the lower layer of the protective bilayer, so that an end of attack signal can be detected in particular by means of conventional detection systems.
  • an end of attack detection invariably taking place on the upper layer or the lower layer of the protective bilayer, or even a double end of attack detection taking place on these two layers, these layers then acting as stop layers for the planarization operation by chemical mechanical polishing.
  • the thickness of the protective bilayer must be sufficient to ensure good protection of the predetermined areas during, in particular, the planarization step by chemical mechanical polishing. It is advantageously between 500 and 2000 ⁇ , typically of the order of 1000 ⁇ .
  • the thickness of the upper layer of the protective bilayer is at least 300 ⁇ , preferably with a thickness ratio of the lower layer to the upper layer of between 0.3 and 1, typically of the order of 1.
  • the method of the invention can be more particularly applied to the lateral insulation of silicon semiconductor substrates.
  • the insulating material is preferably a silicon oxide.
  • the inventors have shown that it was then particularly advantageous to use a protective bilayer composed of a stack of a lower layer composed of silicon nitride and an upper layer composed of polycrystalline silicon. It turns out that the implementation of the process of the invention, using a protective bilayer of silicon nitride and polycrystalline silicon and by making the insulating level by a single chemical-mechanical polishing step, allows a rapid and complete attack of the silicon oxide covering the predetermined areas of the substrate without generating a "dishing effect", thereby eliminating the drawbacks associated with the KOOI effect.
  • planarization step by chemical mechanical polishing has the advantage compared to conventional techniques, of liquid or plasma etching, of etching the materials by very effectively planarizing the initial reliefs.
  • the realization of planarization in a single step by chemical mechanical polishing also makes it possible to reduce the duration of the process and the number of manipulations during the electrical isolation of the future active areas of a semiconductor substrate, while providing a good quality of electrical insulation.
  • assistance by detecting the end of attack of this chemical mechanical polishing makes it possible to better control the degree of polishing.
  • the method of the invention including this attack detection has an additional advantage insofar as it allows the automation of the planarization operation, thereby reducing the manufacturing costs of semiconductor devices.
  • the semiconductor devices manufactured by the above process using in particular a polycrystalline silicon protective bilayer on silicon nitride, have very good electrical insulation.
  • Figures 1a to 1f illustrate a preferred embodiment of the method according to the invention
  • Figures 1g to 1h illustrate an alternative to the steps illustrated in Figures 1a to 1f, according to one aspect of the method of the invention
  • the figures 2a and 2b illustrate the faults encountered in the prior art linked to the techniques for planing the insulating material.
  • the semiconductor substrate is silicon and the insulator is a silicon oxide. It is understood that in accordance with the above, the invention is not limited to this mode.
  • the implementation of the method according to the invention comprises first of all the formation on a semiconductor substrate 1 which may be made of silicon, gallium arsenide or else of the silicon type on insulator, a primary oxide layer 2 such as silicon dioxide for example.
  • a primary oxide layer 2 such as silicon dioxide for example.
  • the formation of this primary layer is carried out by growth of oxide to a thickness of between 50 and 500 ⁇ .
  • One of its functions is to stabilize the interface of substrate 1. It also guarantees the absence of subsequent electrical faults.
  • a protective bilayer 3 composed of a stack of two layers 3a and 3b respectively based on silicon nitride and on polycrystalline silicon.
  • the thickness of the protective bilayer 3 deposited on the primary oxide 2 must be sufficient to ensure good protection of the substrate on which it is deposited, in particular predetermined areas of the substrate intended to subsequently form the active areas. It is advantageously between 500 and 2000 ⁇ , typically of the order of 1000 ⁇ . Furthermore, the thickness of the layer 3b varies according to the performance of the chemical mechanical polishing. This thickness should be adjusted as a function of performance; it may typically be of the order of 300 ⁇ . The thickness of the layer 3a must be sufficient to protect the predetermined active areas during from chemical mechanical polishing and after the disappearance of the upper layer 3a. It is typically at least 300 ⁇ . The thickness ratio of layer 3a to layer 3b can vary between 0.3 and 1, and is generally close to 1.
  • the next step consists in defining the predetermined areas of substrate intended to subsequently form active areas of the final electronic component.
  • a definition step conventionally comprises a deposit of a resin 4 which is isolated through a mask for defining the active areas and then which is developed to finally lead to the structure illustrated in FIG. 1b.
  • the substrate is then chemically etched on either side of the resin 4 so as to form laterally with respect to these predetermined zones trenches more or less deep and more or less narrow.
  • the resin is then removed and an additional layer of oxide, such as silicon dioxide, is grown on the semiconductor block, so as to obtain a layer 5 making it possible to achieve a good interface between the substrate 1 and the future insulating trenches 7, as well as to protect the substrate 1 from impurities.
  • the structure obtained at this stage of the process is illustrated in FIG.
  • the predetermined areas of the substrate intended to subsequently form the active areas of the electronic component, are referenced 6 and are surmounted by the primary oxide layer 2 and the protective bilayer 3.
  • the trenches 7 are thus formed laterally on both sides other of zones 6 and are upholstered by the additional layer of oxide 5.
  • the next step of the process according to the invention consists in depositing in the trenches 7 and on the predetermined areas 6 of the substrate 1, at least one layer of an insulating material 8, in particular silicon dioxide.
  • This structure is illustrated in Figure Id.
  • the thickness of the layer 8 of insulating material is such that the trenches of minimum width existing on the wafer are perfectly filled. Furthermore, this thickness must be greater than the sum of the thickness of the primary oxide layer 2, of the protective bilayer 3 and of the depth of the trench 7. This thickness is preferably chosen to be greater than 10% of said sum.
  • the next step is to flatten the layer
  • planarization is carried out according to the method of the invention in a single step consisting of a chemical-mechanical polishing of the insulating layer 8 uncovering the upper layer 3b of the protective bilayer 3, and, according to one aspect of the process of the invention, uncovering the lower layer 3a of this bilayer.
  • the geometric configurations of the predetermined areas of a semiconductor substrate intended to subsequently form the active areas of electronic component (s) are extremely varied.
  • this geometry can reveal trenches of variable widths which can range from 0.3 ⁇ m to several hundred microns.
  • a polycrystalline silicon protective layer quickly disappears during the chemical mechanical polishing of the silicon dioxide deposited as an insulator, due to an attack speed ten times higher than the attack speed of the dioxide. silicon.
  • an overpolishing or an over-etching can be carried out which risks not only continuing to remove the insulation in the trenches but also damaging the substrate itself in future active areas.
  • FIG. 2a shows a group of predetermined zones 6 mutually separated by lateral trenches 7 of narrow width. This group is isolated from a large predetermined area 6a by an insulating trench 7, from another future active area 6 by an insulating trench 7, the area 6a itself being separated by a wide insulating trench 7a separates this latter area 6 other areas of the substrate.
  • the substrate 1 is surmounted by a protective monolayer 3 ′ composed for example of silicon nitride or polycrystalline silicon.
  • An insulating layer 8 has been deposited which is thick enough to perfectly fill the trenches 7 and 7a and so as to cover the predetermined areas 6 and 6a.
  • these defects are corrected in particular by using a protective bilayer in place of the usual monolayer.
  • This bilayer is composed of a stack of polycrystalline silicon on silicon nitride.
  • the particular conditions of the planing operation adapted to the nature of the protective layer also contribute to the correction of these defects.
  • the planarization of the insulating material is carried out in a single step by chemical mechanical polishing, so that the polycrystalline silicon of the upper layer of the protective bilayer has an attack speed greater than that of the insulation.
  • attack speeds preferably differ by at least a factor of 10 according to a preferred implementation of the method of the invention.
  • Polycrystalline silicon has a higher attack speed during chemical mechanical polishing than that of silicon dioxide, because, according to a preferred implementation of the process of the invention, it attacks at least ten times faster under l action of polishing as silicon oxide.
  • the inventors have demonstrated, when using a protective bilayer of silicon nitride-polycrystalline silicon, that the presence of a layer of polycrystalline silicon underlying the insulating layer in the masked areas more or smaller, makes it possible to accelerate the polishing locally on these zones, by completely clearing the surface above the predetermined zones.
  • the localized acceleration of the chemical-mechanical attack above the predetermined areas protruding from the substrate eliminates the risk of over-etching or overpolishing above the substrate or in the lateral trenches, responsible for the recess of these areas of isolation and destruction of the substrate observed previously. Furthermore, this rapid and complete attack above the predetermined zones ensures complete deoxidation of the underlying silicon nitride.
  • the drawbacks linked to the KOOI effect are therefore also overcome.
  • attack speeds of the insulator and of the polycrystalline silicon differ sufficiently to generate a signal of end of attack of the insulator, one can advantageously assist the single step of planarization by mechanical-chemical polishing of a detection end of attack taking place on the upper layer 3b of the protective bilayer 3 which then acts as a stop layer of the chemical mechanical polishing step.
  • the end of attack detection can be carried out using conventional detection means. This end of attack detection makes it possible to further control the chemical mechanical polishing process and to determine more precisely the completion of the deoxidation of the surface above the predetermined areas of the substrate.
  • the silicon nitride of the layer 3a has an attack speed during chemical mechanical polishing not only lower than that of polycrystalline silicon but also lower than that of the insulating material.
  • the attack speed of the polycrystalline silicon can be thirty times that of the nitride.
  • a chemical mechanical polishing of the insulating layer 8 is implemented.
  • the polishing discovers the underlying underlying layer 3b of said protective layer 3, the chemical mechanical attack is accelerated .
  • the insulating material of the layer 8 is removed completely and quickly above the predetermined zones 6.
  • an end detection d attack can be carried out using a conventional end of attack detection system.
  • the layers 3b, 3a and 2 are then removed according to conventional methods.
  • a polycrystalline silicon layer is removed, for example, by plasma etching or by chemical etching using a mixture of hydrofluoric, acetic and nitric acid.
  • a layer of silicon nitride can be removed, for example, by etching of orthophosphoric acid.
  • the predetermined areas of the substrate 6 are deoxidized so as to obtain the final device illustrated in FIG. 1f.
  • This device therefore comprises the predetermined areas of the substrate 6 discovered at their upper surface and which will subsequently form, after implantation for example, the future active areas of semiconductor components.
  • These future active areas 6 are mutually isolated by trenches 7 comprising in the present case an additional layer 5 of oxide such as silicon dioxide, a layer of insulating material 8, such as an oxide, in particular silicon dioxide.
  • the operating conditions of the chemical mechanical polishing can be fixed so that the silicon nitride of the lower layer 3a of the protective bilayer 3 has an attack speed during this mechanical polishing chemical which differs from that of the polycrystalline silicon of the upper layer 3b by at least a factor of 10.
  • the chemical mechanical polishing of the insulating layer 8 is carried out, the insulating material is removed completely and quickly above the predetermined zones 6.
  • the planarization can be continued until also removing the polycrystalline silicon from the upper layer 3b, revealing the underlying lower layer 3a.
  • the chemical mechanical polishing can then advantageously be assisted by an end of attack detection taking place on the lower layer 3a then acting as a stop layer of the planarization step.
  • the layer 3a is then removed according to conventional methods and then the predetermined areas of substrate 6 are deoxidized so as to obtain the final device illustrated in FIG. 1h.
  • This device therefore comprises the predetermined substrate areas 6 discovered at their upper surface and which will subsequently form, after implantation for example, the future active areas of the electronic components.
  • These future active zones 6 are mutually isolated by trenches 7, comprising in the present case an additional layer of oxide 5, such as silicon dioxide and a layer of insulating material 8, such as an oxide, in particular silicon dioxide.
  • the semiconductor devices manufactured using the method of the invention have good quality of electrical insulation.
  • the process for manufacturing integrated circuits can then continue in a conventional manner.

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Abstract

A method for isolating the working areas of a semiconductor substrate using side trenches, wherein (a) a two-component protective layer (3) consisting of silicon nitride and polysilicon is deposited on the semiconductor substrate, (b) trenches (7) are provided in the semiconductor substrate (1) alongside predetermined areas (6) of the substrate (1) that are covered with the protective layer (3) and intended to form the working areas at a later stage, (c) a layer of insulating material (8) is deposited in the trenches (7) and on the predetermined areas (6) of the substrate (1), and (d) the semiconductor block is planarised in a single step by chemical-mechanical polishing in such a way that the polysilicon of the upper layer (3b) has a higher etching rate during chemical-mechanical polishing than the insulating material, while the nitride of the lower layer (3a) has good resistance to chemical-mechanical etching. In one embodiment, the chemical-mechanical polishing of step (d) is combined with end-of-etching detection on the two-component protective layer (3).

Description

Procédé d'isolement latéral par tranchées utilisant une bicouche de protection en polysilicium sur nitrure de silicium pour l'aplanissement par polissage mécano-chimique de la couche d'isolant.Method of lateral isolation by trenches using a protective bilayer of polysilicon on silicon nitride for planarization by chemical mechanical polishing of the insulating layer.
L'invention concerne l'isolement électrique de composants électroniques. L'invention sera plus particulièrement décrite par rapport à l'isolement latéral des zones actives d'un substrat semi¬ conducteur. Il est bien entendu que l'invention ne se limite pas à cette application et qu'elle peut également être mise en oeuvre pour d'autres applications.The invention relates to the electrical isolation of electronic components. The invention will be more particularly described with respect to the lateral isolation of the active areas of a semiconductor substrate. It is understood that the invention is not limited to this application and that it can also be implemented for other applications.
Dans le cadre de la réduction des dimensions et de l'augmentation de la densité dans le domaine de la micro-électronique, les techniques d'isolement latéral évoluent. Les techniques à base d'oxydation localisée connues sous les dénominations "LOCOS ", "PBL",As part of the reduction in dimensions and the increase in density in the field of microelectronics, lateral isolation techniques are evolving. The techniques based on localized oxidation known under the names "LOCOS", "PBL",
"SILO" sont utilisées pour ce type d'isolement. Toutefois ces techniques présentent des limites notamment lorsque les composants électroniques atteignent des dimensions inférieures à 0,3 μm."SILO" are used for this type of isolation. However, these techniques have limits, especially when the electronic components reach dimensions of less than 0.3 μm.
Pour de telles dimensions, il est nécessaire d'appliquer d'autres techniques d'isolation combinant conjointement la gravure de tranchées profondes ou peu profondes dans le substrat, disposées latéralement par rapport aux futures zones actives et le remplissage de ces tranchées par un matériau isolant suivi de l'aplanissement de cet isolant. Dans ces techniques d'isolation latérale par tranchées on protège les futures zones actives du substrat des opérations successives du procédé et notamment de l'opération d'aplanissement de la couche d'isolant au moyen d'une couche de protection, également appelée "masque de protection", déposée sur le substrat avant l'opération de gravure des tranchées. La technique de gravure des tranchées peu profondes est communément appelée en langue anglaise "Bured Oxide (BOX)" ou "Shallow Trench Isolation (STI)". Ces techniques d'isolement présentent néanmoins une limite liée à l'aplanissement de l'isolant après remplissage des tranchées.For such dimensions, it is necessary to apply other insulation techniques which jointly combine the engraving of deep or shallow trenches in the substrate, arranged laterally with respect to future active areas and the filling of these trenches with an insulating material. followed by the leveling of this insulator. In these lateral isolation techniques by trenches, the future active areas of the substrate are protected from successive operations of the process and in particular from the planarizing operation of the insulating layer by means of a protective layer, also called a "mask". ", deposited on the substrate before the trench etching operation. The technique of engraving shallow trenches is commonly called in English "Bured Oxide (BOX)" or "Shallow Trench Isolation (STI)". These isolation techniques nevertheless have a limit linked to the leveling of the insulation after filling the trenches.
Une technique appropriée pour effectuer l'aplanissement de l'isolant est le polissage mécano-chimique. Or jusqu'à présent, la qualité de l'isolation électrique des dispositifs semi-conducteurs obtenus en mettant en oeuvre un aplanissement par polissage mécano- chimique, est insuffisante.A suitable technique for leveling the insulation is chemical mechanical polishing. However, up to now, the quality of the electrical insulation of the semiconductor devices obtained by implementing planarization by chemical mechanical polishing has been insufficient.
Il a été constaté que le polissage mécano-chimique engendre des défauts dans les dispositifs semi-conducteurs fabriqués, résultant de la mauvaise uniformité d'attaque de cette technique de polissage. Ces défauts n'ont pu être évités malgré l'utilisation des couches ou masques de protection couvrant les zones prédéterminées du substrat destinées à former ultérieurement les zones actives. On observe notamment ce que l'on nomme communément en langue anglaise leIt has been found that chemical mechanical polishing causes defects in the semiconductor devices manufactured, resulting from the poor uniformity of attack of this polishing technique. These defects could not be avoided despite the use of protective layers or masks covering the predetermined areas of the substrate intended to subsequently form the active areas. We observe in particular what is commonly called in English the
"dishing effect". Il s'agit d'un évidement important dans les grandes zones non masquées et les larges tranchées, alors que le matériau isolant n'a pas encore été éliminé entièrement sur certaines zones prédéterminées masquées. Il peut ainsi apparaître après le polissage, deux types de défaut sur le substrat : des évidements des zones d'isolation accompagnés parfois d'une consommation d'une partie du substrat, et des résidus d'isolant sur les zones prédéterminées. Ces défauts baissent considérablement la qualité de l'isolation électrique des dispositifs semi-conducteurs fabriqués. Par ailleurs, la présence de résidus d'oxyde sur les zones prédéterminées entraîne des inconvénients supplémentaires lorsque la couche de protection est en nitrure de silicium. En effet, la présence d'oxyde sur la couche de nitrure de silicium engendre la formation d'un oxynitrure de silicium très difficilement attaquable. Cet effet est communément appelé l'effet KOOI. La couche de protection ne peut alors que difficilement être retirée de sorte que les futures zones actives subissant cet effet ne sont pas facilement accessibles, par exemple, pour implantation ultérieure."dishing effect". This is a significant recess in large unmasked areas and large trenches, while the insulating material has not yet been removed entirely on certain predetermined masked areas. It can thus appear after polishing, two types of defect on the substrate: recesses in the insulation zones sometimes accompanied by a consumption of part of the substrate, and insulation residues on the predetermined zones. These defects considerably lower the quality of the electrical insulation of the semiconductor devices manufactured. Furthermore, the presence of oxide residues on the predetermined areas gives rise to additional disadvantages when the protective layer is made of silicon nitride. Indeed, the presence of oxide on the layer of silicon nitride generates the formation of a silicon oxynitride very difficult to attack. This effect is commonly called the KOOI effect. The protective layer can then only be difficult to remove so that the future active areas undergoing this effect are not easily accessible, for example, for subsequent implantation.
L'invention a pour but un aplanissement efficace de la couche d'isolant en corrigeant les défauts précités conduisant ainsi à un isolement des zones actives par tranchées latérales assurant une bonne qualité d'isolation électrique.The object of the invention is to provide an effective leveling of the insulating layer by correcting the aforementioned defects, thus leading to a isolation of active areas by lateral trenches ensuring good quality of electrical insulation.
L'invention propose un procédé d'isolement électrique des régions actives d'un composant électronique formé sur un substrat semi-conducteur, comprenant l'isolement des zones actives d'un substrat semi-conducteur par tranchées latérales dans lequel, a) on dépose sur le substrat semi-conducteur une bicouche de protection avant de définir les zones destinées à former ultérieurement les zones actives du composant électronique, cette bicouche étant constituée d'un empilement d'une couche inférieure en nitrure de silicium et d'une couche supérieure en silicium polycristallin, b) on réalise au sein du substrat semi-conducteur des tranchées disposées latéralement par rapport aux zones prédéterminées du substrat destinées à former ultérieurement les zones actives, c) on dépose, dans les tranchées et sur les zones prédéterminées du substrat recouvertes de la bicouche de protection, une couche d'un matériau isolant, et d) on effectue un aplanissement du bloc semi-conducteur par une seule étape de polissage mécano-chimique du matériau isolant de manière à ce que la vitesse d'attaque du silicium polycristallin soit supérieure à celle du matériau isolant et de manière à ce que le nitrure de silicium de la couche inférieure de la bicouche de protection présente une bonne résistance à l'attaque physico-chimique, de préférence supérieure à celle du silicium polycristallin de la couche supérieure.The invention provides a method of electrically isolating the active regions of an electronic component formed on a semiconductor substrate, comprising isolating the active regions of a semiconductor substrate by lateral trenches in which, a) is deposited a protective bilayer on the semiconductor substrate before defining the zones intended to subsequently form the active zones of the electronic component, this bilayer consisting of a stack of a lower layer of silicon nitride and of an upper layer of polycrystalline silicon, b) trenches are arranged within the semiconductor substrate arranged laterally relative to the predetermined areas of the substrate intended to subsequently form the active areas, c) is deposited, in the trenches and on the predetermined areas of the substrate covered with the protective bilayer, a layer of insulating material, and d) a flattening of the semi block is carried out conductor by a single mechanical-chemical polishing step of the insulating material so that the attack speed of the polycrystalline silicon is greater than that of the insulating material and so that the silicon nitride of the lower layer of the protective bilayer has good resistance to physicochemical attack, preferably greater than that of polycrystalline silicon in the upper layer.
Les inventeurs ont mis en évidence que l'utilisation d'une telle bicouche de protection permet, lors de l'aplanissement par le seul polissage mécano-chimique dans les conditions décrites, de découvrir la surface supérieure des zones prédéterminées du substrat sans la dégrader tout en ôtant tous résidus d'isolant, et de laisser subsister dans les tranchées latérales le matériau isolant sans l'entamer.The inventors have demonstrated that the use of such a protective bilayer makes it possible, during planarization only by chemical-mechanical polishing under the conditions described, to discover the upper surface of the predetermined areas of the substrate without degrading it entirely. by removing all insulation residue, and allowing the insulating material to remain in the side trenches without damaging it.
Selon une mise en oeuvre préférentielle du procédé de l'invention, le matériau de la couche inférieure de la bicouche de protection possède une vitesse d'attaque lors du polissage mécano- chimique de l'étape d), inférieure à celle du matériau isolant. Cette dernière caractéristique assure une protection accrue des zones prédéterminées du substrat lors du polissage.According to a preferred implementation of the process of the invention, the material of the lower layer of the protective bilayer has an attack speed during the chemical mechanical polishing of step d), lower than that of the insulating material. This last feature provides increased protection of predetermined areas of the substrate during polishing.
Selon une autre mise en oeuvre préférentielle du procédé de l'invention, la vitesse d'attaque du silicium polycristallin de la couche supérieure de la bicouche de protection diffère de celle du matériau isolant d'au moins un facteur 10. Dans ce cas, l'étape d'aplanissement du matériau isolant par polissage mécano-chimique peut avantageusement être assistée d'une détection de fin d'attaque s'effectuant au moins sur la couche supérieure en silicium polycristallin de la bicouche de protection, agissant alors en tant que couche d'arrêt du polissage mécano-chimique.According to another preferred implementation of the process of the invention, the attack speed of the polycrystalline silicon of the upper layer of the protective bilayer differs from that of the insulating material by at least a factor 10. In this case, the planarization step of the insulating material by chemical mechanical polishing can advantageously be assisted by an end of attack detection taking place at least on the upper polycrystalline silicon layer of the protective bilayer, then acting as a layer stopping the chemical mechanical polishing.
Selon un aspect du procédé de l'invention, la vitesse d'attaque du silicium polycristallin de la couche supérieure de la bicouche de protection peut également suffisamment différer, de préférence d'au moins un facteur 10, de celle du nitrure de silicium de la couche inférieure de la bicouche de protection, pour qu'un signal de fin d'attaque puisse être détecté notamment au moyen de systèmes de détection classiques. On peut alors envisager une détection de fin d'attaque s'effectuant invariablement sur la couche supérieure ou la couche inférieure de la bicouche de protection, voire une double détection de fin d'attaque s'effectuant sur ces deux couches, ces couches agissant alors en tant que couches d'arrêt de l'opération d'aplanissement par polissage mécano-chimique.According to one aspect of the process of the invention, the attack speed of the polycrystalline silicon of the upper layer of the protective bilayer can also differ sufficiently, preferably by at least a factor of 10, from that of the silicon nitride of the lower layer of the protective bilayer, so that an end of attack signal can be detected in particular by means of conventional detection systems. We can then envisage an end of attack detection invariably taking place on the upper layer or the lower layer of the protective bilayer, or even a double end of attack detection taking place on these two layers, these layers then acting as stop layers for the planarization operation by chemical mechanical polishing.
L'épaisseur de la bicouche de protection doit être suffisante pour assurer une bonne protection des zones prédéterminée lors, notamment, de l'étape d'aplanissement par polissage mécano-chimique. Elle est avantageusement comprise entre 500 et 2000 Â, typiquement de l'ordre de 1000 Â. L'épaisseur de la couche supérieure de la bicouche de protection est au moins 300 Â, avec de préférence un rapport d'épaisseur de la couche inférieure à la couche supérieure compris entre 0,3 et 1, typiquement de l'ordre de 1.The thickness of the protective bilayer must be sufficient to ensure good protection of the predetermined areas during, in particular, the planarization step by chemical mechanical polishing. It is advantageously between 500 and 2000 Å, typically of the order of 1000 Å. The thickness of the upper layer of the protective bilayer is at least 300 Å, preferably with a thickness ratio of the lower layer to the upper layer of between 0.3 and 1, typically of the order of 1.
Le procédé de l'invention peut être plus particulièrement appliqué à l'isolement latéral des substrats semi-conducteurs en silicium. Dans ce cas, le matériau isolant est de préférence un oxyde de silicium. Les inventeurs ont mis en évidence qu'il était alors particulièrement avantageux d'utiliser une bicouche de protection composée d'un empilement d'une couche inférieure composée de nitrure de silicium et d'une couche supérieure composée de silicium polycristallin. II s'avère en effet que la mise en oeuvre du procédé de l'invention, utilisant une bicouche de protection en nitrure de silicium et silicium polycristallin et en réalisant l'aplanissement de l'isolant par une étape unique de polissage mécano-chimique, permet une attaque rapide et complète de l'oxyde de silicium couvrant les zones prédéterminée du substrat sans générer de "dishing effect", s'affranchissant du même coup des inconvénients liés à l'effet KOOI. L'étape d'aplanissement par polissage mécano-chimique présente l'avantage par rapport aux techniques conventionnelles, de gravure liquide ou par plasma, de graver les matériaux en aplanissant très efficacement les reliefs initiaux. La réalisation de l'aplanissement en une seule étape par polissage mécano-chimique permet également de réduire la durée du procédé et le nombre de manipulations lors de l'isolation électrique des futures zones actives d'un substrat semi¬ conducteur, tout en procurant une bonne qualité d'isolation électrique. Selon certaines caractéristiques préférentielles du procédé de l'invention, l'assistance par une détection de fin d'attaque de ce polissage mécano-chimique permet de mieux contrôler le degré du polissage. Par ailleurs, le procédé de l'invention incluant cette détection d'attaque présente un avantage supplémentaire dans la mesure où il permet l'automatisation de l'opération de d'aplanissement réduisant ainsi les coûts de fabrication des dispositifs semi¬ conducteurs.The method of the invention can be more particularly applied to the lateral insulation of silicon semiconductor substrates. In this case, the insulating material is preferably a silicon oxide. The inventors have shown that it was then particularly advantageous to use a protective bilayer composed of a stack of a lower layer composed of silicon nitride and an upper layer composed of polycrystalline silicon. It turns out that the implementation of the process of the invention, using a protective bilayer of silicon nitride and polycrystalline silicon and by making the insulating level by a single chemical-mechanical polishing step, allows a rapid and complete attack of the silicon oxide covering the predetermined areas of the substrate without generating a "dishing effect", thereby eliminating the drawbacks associated with the KOOI effect. The planarization step by chemical mechanical polishing has the advantage compared to conventional techniques, of liquid or plasma etching, of etching the materials by very effectively planarizing the initial reliefs. The realization of planarization in a single step by chemical mechanical polishing also makes it possible to reduce the duration of the process and the number of manipulations during the electrical isolation of the future active areas of a semiconductor substrate, while providing a good quality of electrical insulation. According to certain preferred characteristics of the method of the invention, assistance by detecting the end of attack of this chemical mechanical polishing makes it possible to better control the degree of polishing. Furthermore, the method of the invention including this attack detection has an additional advantage insofar as it allows the automation of the planarization operation, thereby reducing the manufacturing costs of semiconductor devices.
Les dispositifs semi-conducteurs fabriqués par le procédé ci- dessus, utilisant notamment une bicouche de protection en silicium polycristallin sur nitrure de silicium, présentent une isolation électrique de très bonne qualité.The semiconductor devices manufactured by the above process, using in particular a polycrystalline silicon protective bilayer on silicon nitride, have very good electrical insulation.
D'autres avantages et caractéristiques de l'invention apparaîtront à l'examen de la description détaillée de modes de réalisation et de mise en oeuvre du procédé de l'invention, nullement limitatif, et des dessins annexés sur lesquels : les figures la à lf illustrent un mode de mise en oeuvre préférentiel du procédé selon l'invention, les figures lg à lh illustrent une alternative aux étapes illustrées dans les figures le à lf, selon un aspect du procédé de l'invention, les figures 2a et 2b illustrent les défauts rencontrés dans l'art antérieur liés aux techniques d'aplanissement du matériau isolant.Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments and implementation of the method of the invention, in no way limiting, and the appended drawings in which: Figures 1a to 1f illustrate a preferred embodiment of the method according to the invention, Figures 1g to 1h illustrate an alternative to the steps illustrated in Figures 1a to 1f, according to one aspect of the method of the invention, the figures 2a and 2b illustrate the faults encountered in the prior art linked to the techniques for planing the insulating material.
Pour une meilleure compréhension de l'invention, celle-ci sera souvent décrite ci-après par référence au mode de réalisation dans lequel le substrat semi-conducteur est du silicium et l'isolant un oxyde de silicium. Il est bien entendu que conformément à ce qui précède, l'invention ne se limite pas à ce mode.For a better understanding of the invention, it will often be described below with reference to the embodiment in which the semiconductor substrate is silicon and the insulator is a silicon oxide. It is understood that in accordance with the above, the invention is not limited to this mode.
Tel qu'illustré sur les figures la à lf, la mise en oeuvre du procédé selon l'invention comporte tout d'abord la formation sur un substrat 1 semi-conducteur qui peut être en silicium, en arséniure de gallium ou bien du type silicium sur isolant, une couche primaire d'oxyde 2 tel que du dioxyde de silicium par exemple. La formation de cette couche primaire est effectuée par croissance d'oxyde jusqu'à une épaisseur comprise entre 50 et 500 Â. L'une de ses fonctions est de stabiliser l'interface du substrat 1. Elle garantit par ailleurs l'absence de défauts électriques ultérieurs.As illustrated in FIGS. 1a to 1f, the implementation of the method according to the invention comprises first of all the formation on a semiconductor substrate 1 which may be made of silicon, gallium arsenide or else of the silicon type on insulator, a primary oxide layer 2 such as silicon dioxide for example. The formation of this primary layer is carried out by growth of oxide to a thickness of between 50 and 500 Å. One of its functions is to stabilize the interface of substrate 1. It also guarantees the absence of subsequent electrical faults.
Sur cette couche primaire d'oxyde 2 est déposée une bicouche de protection 3 composée d'un empilement de deux couches 3 a et 3b respectivement à base de nitrure de silicium et en silicium polycristallin.On this primary oxide layer 2 is deposited a protective bilayer 3 composed of a stack of two layers 3a and 3b respectively based on silicon nitride and on polycrystalline silicon.
L'épaisseur de la bicouche de protection 3 déposée sur l'oxyde primaire 2 doit être suffisante pour assurer une bonne protection du substrat sur lequel elle est déposée, notamment des zones prédéterminées du substrat destiné à former ultérieurement les zones actives. Elle est avantageusement comprise entre 500 et 2000 À, typiquement de l'ordre de 1000 À. Par ailleurs, l'épaisseur de la couche 3b varie selon les performance du polissage mécano-chimique. Il convient d'ajuster cette épaisseur en fonction de performances elle peut être typiquement de l'ordre de 300 À. L'épaisseur de la couche 3a doit être suffisante pour protéger les zones actives prédéterminées lors du polissage mécano-chimique et après la disparition de la couche supérieure 3a. Elle est typiquement d'au moins 300 Â. Le rapport d'épaisseur de la couche 3a à la couche 3b peut varier entre 0,3 et 1, et est généralement voisin de 1. L'étape suivante consiste en la définition des zones prédéterminées de substrat destinées à former ultérieurement des zones actives du composant électronique final. Une telle étape de définition comprend classiquement un dépôt d'une résine 4 que l'on isole à travers un masque de définition des zones actives puis que l'on développe pour aboutir finalement à la structure illustrée sur la figure lb. Le substrat est ensuite gravé chimiquement de part et d'autre de la résine 4 de façon à réaliser latéralement par rapport à ces zones prédéterminées des tranchées plus ou moins profondes et plus ou moins étroites. La résine est ensuite retirée et l'on fait croître sur le bloc semi-conducteur une couche additionnelle d'oxyde, tel que du dioxyde de silicium, de façon à obtenir une couche 5 permettant de réaliser une bonne interface entre le substrat 1 et les futures tranchées isolantes 7, ainsi qu'à protéger le substrat 1 vis-à-vis des impuretés. La structure obtenue à ce stade du procédé est illustrée à la figure le. Les zones prédéterminées du substrat destinées à former ultérieurement les zones actives du composant électronique, sont référencées 6 et sont surmontées de la couche primaire d'oxyde 2 et de la bicouche de protection 3. Les tranchées 7 sont ainsi ménagées latéralement de part et d'autre des zones 6 et sont tapissées par la couche additionnelle de d'oxyde 5.The thickness of the protective bilayer 3 deposited on the primary oxide 2 must be sufficient to ensure good protection of the substrate on which it is deposited, in particular predetermined areas of the substrate intended to subsequently form the active areas. It is advantageously between 500 and 2000 Å, typically of the order of 1000 Å. Furthermore, the thickness of the layer 3b varies according to the performance of the chemical mechanical polishing. This thickness should be adjusted as a function of performance; it may typically be of the order of 300 Å. The thickness of the layer 3a must be sufficient to protect the predetermined active areas during from chemical mechanical polishing and after the disappearance of the upper layer 3a. It is typically at least 300 Å. The thickness ratio of layer 3a to layer 3b can vary between 0.3 and 1, and is generally close to 1. The next step consists in defining the predetermined areas of substrate intended to subsequently form active areas of the final electronic component. Such a definition step conventionally comprises a deposit of a resin 4 which is isolated through a mask for defining the active areas and then which is developed to finally lead to the structure illustrated in FIG. 1b. The substrate is then chemically etched on either side of the resin 4 so as to form laterally with respect to these predetermined zones trenches more or less deep and more or less narrow. The resin is then removed and an additional layer of oxide, such as silicon dioxide, is grown on the semiconductor block, so as to obtain a layer 5 making it possible to achieve a good interface between the substrate 1 and the future insulating trenches 7, as well as to protect the substrate 1 from impurities. The structure obtained at this stage of the process is illustrated in FIG. The predetermined areas of the substrate intended to subsequently form the active areas of the electronic component, are referenced 6 and are surmounted by the primary oxide layer 2 and the protective bilayer 3. The trenches 7 are thus formed laterally on both sides other of zones 6 and are upholstered by the additional layer of oxide 5.
Sur une plaquette de matériau semi-conducteur, sont disposées plusieurs zones prédéterminées destinées à former ultérieurement les zones actives d'un ou plusieurs composants semi¬ conducteurs. Les configurations géométriques de ces futures zones actives peuvent être extrêmement variées, il peut s'agir de zones actives isolées, ou bien séparées d'autres zones actives par de larges tranchées isolantes, ou bien de groupes de zones actives mutuellement séparées latéralement par des tranchées dont la profondeur peut être plus ou moins grande et la largeur plus ou moins étroite selon les cas. L'étape suivante du procédé selon l'invention consiste à déposer dans les tranchées 7 et sur les zones prédéterminées 6 du substrat 1 , au moins une couche d'un matériau isolant 8, particulièrement du dioxyde de silicium. Cette structure est illustrée à la figure Id. L'épaisseur de la couche 8 de matériau isolant est telle que les tranchées de largeur minimale existant sur la plaquette soient parfaitement remplies. Par ailleurs, cette épaisseur doit être supérieure à la somme de l'épaisseur de la couche primaire d'oxyde 2, de la bicouche de protection 3 et de la profondeur de la tranchée 7. Cette épaisseur est choisie de préférence supérieure à 10 % de ladite somme.On a wafer of semiconductor material, are arranged several predetermined zones intended to subsequently form the active zones of one or more semiconductor components. The geometrical configurations of these future active zones can be extremely varied, they can be isolated active zones, or separated from other active zones by large insulating trenches, or groups of active zones mutually separated laterally by trenches the depth of which may be greater or lesser and the width more or less narrow depending on the case. The next step of the process according to the invention consists in depositing in the trenches 7 and on the predetermined areas 6 of the substrate 1, at least one layer of an insulating material 8, in particular silicon dioxide. This structure is illustrated in Figure Id. The thickness of the layer 8 of insulating material is such that the trenches of minimum width existing on the wafer are perfectly filled. Furthermore, this thickness must be greater than the sum of the thickness of the primary oxide layer 2, of the protective bilayer 3 and of the depth of the trench 7. This thickness is preferably chosen to be greater than 10% of said sum.
L'étape ultérieure consiste en un aplanissement de la coucheThe next step is to flatten the layer
8 d'isolant de façon à découvrir la surface supérieure des zones prédéterminées 6 du substrat 1 et à laisser subsister le matériau isolant dans les tranchées latérales 7. L'aplanissement est effectué selon le procédé de l'invention en une seule étape consistant en un polissage mécano-chimique de la couche d'isolant 8 découvrant la couche supérieure 3b de la bicouche de protection 3, et, selon un aspect du procédé de l'invention, découvrant la couche inférieure 3a de cette bicouche. H apparaît que dans les techniques d'isolement latéral de substrats semi-conducteurs, le polissage mécano-chimique soit la solution la plus performante pour cette étape d'aplanissement car il présente l'avantage, par rapport aux techniques conventionnelles de gravure liquide ou par plasma, de graver les matériaux en aplanissant très efficacement les reliefs initiaux. L'inconvénient de cette technique réside toutefois dans la mauvaise uniformité de l'attaque mécano- chimique.8 of insulation so as to uncover the upper surface of the predetermined zones 6 of the substrate 1 and to leave the insulating material in the lateral trenches 7. The planarization is carried out according to the method of the invention in a single step consisting of a chemical-mechanical polishing of the insulating layer 8 uncovering the upper layer 3b of the protective bilayer 3, and, according to one aspect of the process of the invention, uncovering the lower layer 3a of this bilayer. It appears that in the techniques of lateral isolation of semiconductor substrates, chemical mechanical polishing is the most efficient solution for this planarization step because it has the advantage, compared to conventional techniques of liquid etching or by plasma, to engrave the materials by very effectively flattening the initial reliefs. The disadvantage of this technique however lies in the poor uniformity of the chemical mechanical attack.
Comme on l'a vu plus haut, les configurations géométriques des zones prédéterminées d'un substrat semi-conducteur destinées à former ultérieurement les zones actives de composant(s) électronique(s) sont extrêmement variées. Ainsi cette géométrie peut faire apparaître des tranchées de largeurs variables pouvant aller de 0,3 μm à plusieurs centaines de microns. Cette géométrie associée à la relative mauvaise uniformité d'aplanissement, inhérente à la technique même du polissage, favorise le "dishing effect". Cet effet n'est pas atténué par l'utilisation de couche de protection classique.As seen above, the geometric configurations of the predetermined areas of a semiconductor substrate intended to subsequently form the active areas of electronic component (s) are extremely varied. Thus this geometry can reveal trenches of variable widths which can range from 0.3 μm to several hundred microns. This geometry associated with the relative poor uniformity of planing, inherent in the very technique of polishing, promotes the "dishing effect". This effect is not mitigated by the use of conventional protective layer.
En effet, une couche de protection en silicium polycristallin disparaît rapidement lors du polissage mécano-chimique du dioxyde de silicium déposé à titre d'isolant, du fait d'une vitesse d'attaque dix fois supérieure à la vitesse d'attaque du dioxyde de silicium. On observe rapidement une destruction, localisée ou non, de certaines zones prédéterminées, voire un évidement des zones isolantes. L'utilisation de nitrure de silicium, matériau plus résistant à l'attaque mécano- chimique que le silicium polycristallin, pour protéger les zones prédéterminées d'un substrat semi-conducteur, conduit quant à elle à ce que l'on appelle communément l'effet KOOI lorsqu'après le polissage il subsiste des résidus d'oxyde sur la couche de nitrure de silicium. Afin d'éviter cet effet, on peut procéder à un surpolissage ou une surgravure qui risque non seulement de poursuivre le retrait de l'isolant dans les tranchées mais encore d'entamer le substrat lui-même dans les futures zones actives.Indeed, a polycrystalline silicon protective layer quickly disappears during the chemical mechanical polishing of the silicon dioxide deposited as an insulator, due to an attack speed ten times higher than the attack speed of the dioxide. silicon. We quickly observe a destruction, localized or not, of certain predetermined areas, or even a recess of the insulating areas. The use of silicon nitride, a material more resistant to mechanical and chemical attack than polycrystalline silicon, to protect the predetermined areas of a semiconductor substrate, leads to what is commonly called KOOI effect when after polishing there remains oxide residues on the silicon nitride layer. In order to avoid this effect, an overpolishing or an over-etching can be carried out which risks not only continuing to remove the insulation in the trenches but also damaging the substrate itself in future active areas.
Les figures 2a et 2b illustrent les inconvénients cités plus haut, dus à l'utilisation du polissage mécano-chimique pour l'aplanissement de la couche isolante. Sur la figure 2a on a représenté un groupe de zones prédéterminées 6 mutuellement séparées par des tranchées latérales 7 de largeur étroite. Ce groupe est isolé d'une large zone prédéterminée 6a par une tranchée isolante 7, d'une autre future zone active 6 par une tranchée isolante 7, la zone 6a étant elle-même séparée par une large tranchée isolante 7a sépare cette dernière zone 6 d'autres zones du substrat. Le substrat 1 est surmonté d'une monocouche de protection 3' composée par exemple de nitrure de silicium ou de silicium polycristallin. On a déposé une couche d'isolant 8 suffisamment épaisse pour remplir parfaitement les tranchées 7 et 7a et de manière à recouvrir les zones prédéterminées 6 et 6a. On a ensuite effectué un polissage mécano-chimique du bloc semi-conducteur pour aplanir la couche 8 d'isolant. Le résultat de cette opération est illustré sur la figure 2b. On constate que la large tranchée isolante 7a présente un évidement alors que sur certaines zones prédéterminées 6 des résidus de matériau isolant persistent. On observe également à l'endroit de la large zone prédéterminée 6a une destruction du substrat résultant d'un polissage trop prononcé à cet endroit alors que le polissage s'est avéré insuffisant à l'endroit où le matériau isolant n'a pu être enlevé ("dishing effect").Figures 2a and 2b illustrate the drawbacks mentioned above, due to the use of chemical mechanical polishing for planarizing the insulating layer. FIG. 2a shows a group of predetermined zones 6 mutually separated by lateral trenches 7 of narrow width. This group is isolated from a large predetermined area 6a by an insulating trench 7, from another future active area 6 by an insulating trench 7, the area 6a itself being separated by a wide insulating trench 7a separates this latter area 6 other areas of the substrate. The substrate 1 is surmounted by a protective monolayer 3 ′ composed for example of silicon nitride or polycrystalline silicon. An insulating layer 8 has been deposited which is thick enough to perfectly fill the trenches 7 and 7a and so as to cover the predetermined areas 6 and 6a. A chemical mechanical polishing of the semiconductor block was then carried out to flatten the layer 8 of insulation. The result of this operation is illustrated in Figure 2b. It can be seen that the large insulating trench 7a has a recess while in certain predetermined areas 6 residues of insulating material persist. We also observe at the location of the large predetermined area 6a a destruction of the substrate resulting from too pronounced polishing at this location when the polishing proved to be insufficient at the location where the insulating material could not be removed ("dishing effect").
Selon le procédé de l'invention, ces défauts sont corrigés notamment en utilisant une bicouche de protection en lieu et place de la monocouche habituelle. Cette bicouche est composée d'un empilement de silicium polycristallin sur nitrure de silicium. Les conditions particulières de l'opération d'aplanissement adaptées à la nature de la couche de protection contribuent également à la correction de ces défauts.According to the method of the invention, these defects are corrected in particular by using a protective bilayer in place of the usual monolayer. This bilayer is composed of a stack of polycrystalline silicon on silicon nitride. The particular conditions of the planing operation adapted to the nature of the protective layer also contribute to the correction of these defects.
Selon une caractéristique générale du procédé de l'invention, l'aplanissement du matériau isolant est réalisé en une seule étape par polissage mécano-chimique, de sorte que le silicium polycristallin de la couche supérieure de la bicouche de protection possède une vitesse d'attaque supérieure à celle de l'isolant. Ces vitesses d'attaque diffèrent de préférence d'au moins un facteur 10 selon une mise en oeuvre préférentielle du procédé de l'invention.According to a general characteristic of the method of the invention, the planarization of the insulating material is carried out in a single step by chemical mechanical polishing, so that the polycrystalline silicon of the upper layer of the protective bilayer has an attack speed greater than that of the insulation. These attack speeds preferably differ by at least a factor of 10 according to a preferred implementation of the method of the invention.
Bien que n'étant lié à aucune théorie particulière, l'amélioration de la qualité de l'isolement latéral de substrats semi- conducteurs s'expliquerait selon les inventeurs par le phénomène suivant :Although not linked to any particular theory, the improvement in the quality of the lateral insulation of semiconductor substrates can be explained by the inventors by the following phenomenon:
Le silicium polycristallin possède une vitesse d'attaque lors du polissage mécano-chimique supérieure à celle du dioxyde de silicium, car, selon une mise en oeuvre préférentielle du procédé de l'invention, il s'attaque au moins dix fois plus rapidement sous l'action du polissage que l'oxyde de silicium. Les inventeurs ont mis en évidence, lors de l'utilisation d'une bicouche de protection en nitrure de silicium-silicium polycristallin, que la présence d'une couche de silicium polycristallin sous-jacente à la couche d'isolant dans les zones masquées plus ou moins grandes, permet d'accélérer localement le polissage sur ces zones, en dégageant complètement la surface au- dessus des zones prédéterminées. L'accélération localisée de l'attaque mécano-chimique au-dessus des zones prédéterminées en saillie du substrat supprime le risque d'une surgravure ou surpolissage au-dessus du substrat ou dans les tranchées latérales, responsable de l'évidement de ces zones d'isolation et de destruction du substrat observées auparavant. Par ailleurs, cette attaque rapide et complète au-dessus des zones prédéterminées assure une désoxydation complète du nitrure de silicium sous-jacent. Les inconvénients liés à l'effet KOOI sont donc également surmontés.Polycrystalline silicon has a higher attack speed during chemical mechanical polishing than that of silicon dioxide, because, according to a preferred implementation of the process of the invention, it attacks at least ten times faster under l action of polishing as silicon oxide. The inventors have demonstrated, when using a protective bilayer of silicon nitride-polycrystalline silicon, that the presence of a layer of polycrystalline silicon underlying the insulating layer in the masked areas more or smaller, makes it possible to accelerate the polishing locally on these zones, by completely clearing the surface above the predetermined zones. The localized acceleration of the chemical-mechanical attack above the predetermined areas protruding from the substrate eliminates the risk of over-etching or overpolishing above the substrate or in the lateral trenches, responsible for the recess of these areas of isolation and destruction of the substrate observed previously. Furthermore, this rapid and complete attack above the predetermined zones ensures complete deoxidation of the underlying silicon nitride. The drawbacks linked to the KOOI effect are therefore also overcome.
Lorsque les vitesses d'attaque de l'isolant et du silicium polycristallin diffèrent suffisamment pour générer un signal de fin d'attaque de l'isolant, on peut avantageusement assister l'unique étape d'aplanissement par polissage mécano-chimique d'une détection de fin d'attaque s'effectuant sur la couche supérieure 3b de la bicouche de protection 3 qui agit alors en tant que couche d'arrêt de l'étape de polissage mécano-chimique. La détection de fin d'attaque peut s'effectuer en utilisant des moyens de détection classiques. Cette détection de fin d'attaque permet de contrôler davantage le processus de polissage mécano-chimique et de déterminer avec plus de précision l'accomplissement de la désoxydation de la surface au-dessus des zones prédéterminées du substrat.When the attack speeds of the insulator and of the polycrystalline silicon differ sufficiently to generate a signal of end of attack of the insulator, one can advantageously assist the single step of planarization by mechanical-chemical polishing of a detection end of attack taking place on the upper layer 3b of the protective bilayer 3 which then acts as a stop layer of the chemical mechanical polishing step. The end of attack detection can be carried out using conventional detection means. This end of attack detection makes it possible to further control the chemical mechanical polishing process and to determine more precisely the completion of the deoxidation of the surface above the predetermined areas of the substrate.
De préférence, le nitrure de silicium de la couche 3a possède une vitesse d'attaque lors du polissage mécano-chimique non seulement inférieure à celle du silicium polycristallin mais encore inférieure à celle du matériau isolant. Selon la mise en oeuvre de l'opération d'aplanissement, la vitesse d'attaque du silicium polycristallin peut être trente fois supérieure à celle du nitrure.Preferably, the silicon nitride of the layer 3a has an attack speed during chemical mechanical polishing not only lower than that of polycrystalline silicon but also lower than that of the insulating material. Depending on the implementation of the planarization operation, the attack speed of the polycrystalline silicon can be thirty times that of the nitride.
Ainsi, selon l'invention, on met en oeuvre un polissage mécano-chimique de la couche d'isolant 8. Lorsque le polissage découvre la couche supérieure sous-jacente 3b de ladite couche de protection 3, l'attaque mécano-chimique est accélérée. Le matériau isolant de la couche 8 est retiré totalement et rapidement au-dessus des zones prédéterminées 6. Lorsque les vitesses d'attaque entre isolant et silicium polycristallin de la couche supérieure 3b diffèrent d'au moins un facteur 10, une détection de fin d'attaque peut s'effectuer au moyen d'un système classique de détection de fin d'attaque. On obtient alors la structure illustrée à la figure le. On retire alors les couches 3b, 3a et 2 selon des méthodes classiques. Une couche en silicium polycristallin est retirée, par exemple, par gravure plasma ou par gravure chimique au moyen d'un mélange d'acide fluorhydrique, acétique et nitrique. Une couche en nitrure de silicium peut être retirée, par exemple, par attaque d'acide orthophosphorique. On procède ensuite à une désoxydation des zones prédéterminées du substrat 6 de façon à obtenir le dispositif final illustré à la figure lf.Thus, according to the invention, a chemical mechanical polishing of the insulating layer 8 is implemented. When the polishing discovers the underlying underlying layer 3b of said protective layer 3, the chemical mechanical attack is accelerated . The insulating material of the layer 8 is removed completely and quickly above the predetermined zones 6. When the attack speeds between the insulator and the polycrystalline silicon of the upper layer 3b differ by at least a factor of 10, an end detection d attack can be carried out using a conventional end of attack detection system. We then obtain the structure illustrated in Figure le. The layers 3b, 3a and 2 are then removed according to conventional methods. A polycrystalline silicon layer is removed, for example, by plasma etching or by chemical etching using a mixture of hydrofluoric, acetic and nitric acid. A layer of silicon nitride can be removed, for example, by etching of orthophosphoric acid. Next, the predetermined areas of the substrate 6 are deoxidized so as to obtain the final device illustrated in FIG. 1f.
Ce dispositif comporte donc les zones prédéterminées du substrat 6 découvertes au niveau de leur surface supérieure et qui formeront ultérieurement, après implantation par exemple, les futures zones actives de composants semi-conducteurs. Ces futures zones actives 6 sont mutuellement isolées par des tranchées 7 comportant dans le cas présent une couche additionnelle 5 d'oxyde tel que du dioxyde de silicium, une couche de matériau isolant 8, tel qu'un oxyde notamment du dioxyde de silicium.This device therefore comprises the predetermined areas of the substrate 6 discovered at their upper surface and which will subsequently form, after implantation for example, the future active areas of semiconductor components. These future active areas 6 are mutually isolated by trenches 7 comprising in the present case an additional layer 5 of oxide such as silicon dioxide, a layer of insulating material 8, such as an oxide, in particular silicon dioxide.
Selon un aspect du procédé de l'invention, les conditions opératoires du polissage mécano-chimique peuvent être fixées de sorte que le nitrure de silicium de la couche inférieure 3a de la bicouche de protection 3 possède une vitesse d'attaque lors de ce polissage mécano-chimique qui diffère de celle du silicium polycristallin de la couche supérieure 3b d'au moins un facteur 10. Lorsque l'on met en oeuvre le polissage mécano-chimique de la couche d'isolant 8, le matériau isolant est retiré totalement et rapidement au-dessus des zones prédéterminées 6. L'aplanissement peut être poursuivi jusqu'à retirer également le silicium polycristallin de la couche supérieure 3b, découvrant la couche inférieure sous-jacente 3a. Le polissage mécano- chimique peut alors avantageusement être assisté d'une détection de fin d'attaque s'effectuant sur la couche inférieure 3a agissant alors en tant que couche d'arrêt de l'étape d'aplanissement. On obtient alors la structure illustrée à la figure lg. On retire ensuite la couche 3a selon des méthodes classiques puis on procède à une désoxydation des zones prédéterminées de substrat 6 de façon à obtenir le dispositif final illustré à la figure lh. Ce dispositif comporte donc les zones prédéterminées de substrat 6 découvertes au niveau de leur surface supérieure et qui formeront ultérieurement, après implantation par exemple, les futures zones actives des composants électroniques. Ces futures zones actives 6 sont mutuellement isolées par des tranchées 7, comportant dans le cas présent une couche additionnelle d'oxyde 5, tel que du dioxyde de silicium et une couche de matériau isolant 8, tel qu'un oxyde, notamment du dioxyde de silicium.According to one aspect of the process of the invention, the operating conditions of the chemical mechanical polishing can be fixed so that the silicon nitride of the lower layer 3a of the protective bilayer 3 has an attack speed during this mechanical polishing chemical which differs from that of the polycrystalline silicon of the upper layer 3b by at least a factor of 10. When the chemical mechanical polishing of the insulating layer 8 is carried out, the insulating material is removed completely and quickly above the predetermined zones 6. The planarization can be continued until also removing the polycrystalline silicon from the upper layer 3b, revealing the underlying lower layer 3a. The chemical mechanical polishing can then advantageously be assisted by an end of attack detection taking place on the lower layer 3a then acting as a stop layer of the planarization step. We then obtain the structure illustrated in Figure lg. The layer 3a is then removed according to conventional methods and then the predetermined areas of substrate 6 are deoxidized so as to obtain the final device illustrated in FIG. 1h. This device therefore comprises the predetermined substrate areas 6 discovered at their upper surface and which will subsequently form, after implantation for example, the future active areas of the electronic components. These future active zones 6 are mutually isolated by trenches 7, comprising in the present case an additional layer of oxide 5, such as silicon dioxide and a layer of insulating material 8, such as an oxide, in particular silicon dioxide.
On n'observe aucun évidement des zones isolantes ni de destruction de zones prédéterminées et du substrat ainsi traité. Les dispositifs semi-conducteurs fabriqués en mettant en oeuvre le procédé de l'invention présentent une bonne qualité d'isolation électrique.No recessing of the insulating zones or destruction of predetermined zones and of the substrate thus treated is observed. The semiconductor devices manufactured using the method of the invention have good quality of electrical insulation.
Le procédé de fabrication de circuits intégrés peut se poursuivre ensuite de manière classique. The process for manufacturing integrated circuits can then continue in a conventional manner.

Claims

REVENDICATIONS
1. Procédé d'isolement électrique des régions actives d'un composant électronique formé sur un substrat semi-conducteur comportant l'isolement des zones actives du substrat semi-conducteur (1) par tranchées latérales comprenant les étapes suivantes : a) on dépose sur le substrat semi-conducteur (1) une bicouche de protection (3) constituées d'un empilement d'une couche inférieure (3a) en nitrure de silicium et d'une couche supérieure (3b) en silicium polycristallin, b) on réalise au sein du substrat semi-conducteur ( 1 ) des tranchées (7) disposées latéralement par rapport aux zones prédéterminées (6) du substrat (1 ) recouvertes de la bicouche de protection (3) et destinées à former ultérieurement les zones actives, c) on dépose dans les tranchées (7) et sur les zones prédéterminées (6) du substrat, une couche d'un matériau isolant (8), et d) on effectue un aplanissement du bloc semi-conducteur en une seule étape mettant en oeuvre un polissage mécano-chimique du matériau isolant (8) de manière à ce que la vitesse d'attaque du silicium polycristallin soit supérieure à celle du matériau isolant, et de manière à ce que le nitrure de silicium de la couche inférieure (3a) présente une résistance à l'attaque physico-chimique supérieure à celle du matériau de la couche supérieure (3b).1. A method of electrically isolating the active regions of an electronic component formed on a semiconductor substrate comprising isolating the active regions of the semiconductor substrate (1) by lateral trenches comprising the following steps: a) depositing on the semiconductor substrate (1) a protective bilayer (3) consisting of a stack of a lower layer (3a) of silicon nitride and an upper layer (3b) of polycrystalline silicon, b) within the semiconductor substrate (1) trenches (7) arranged laterally with respect to the predetermined areas (6) of the substrate (1) covered with the protective bilayer (3) and intended to subsequently form the active areas, c) on depositing in the trenches (7) and on the predetermined areas (6) of the substrate, a layer of insulating material (8), and d) a flattening of the semiconductor block is carried out in a single step using polishing mechano-chi mique insulating material (8) so that the attack speed of the polycrystalline silicon is higher than that of the insulating material, and so that the silicon nitride of the lower layer (3a) has a resistance to l physicochemical attack superior to that of the material of the upper layer (3b).
2. Procédé selon la revendication 1, caractérisé en ce que dans l'étape d), la vitesse d'attaque du nitrure de silicium de la couche inférieure (3a) est inférieure à celle du matériau isolant.2. Method according to claim 1, characterized in that in step d), the attack speed of the silicon nitride of the lower layer (3a) is lower than that of the insulating material.
3. Procédé selon la revendication 1 ou 2, caractérisé en ce que dans l'étape d), le rapport de la vitesse d'attaque du silicium polycristallin de la couche supérieure (3b) à la vitesse d'attaque du matériau isolant est au moins 10. 3. Method according to claim 1 or 2, characterized in that in step d), the ratio of the attack speed of the polycrystalline silicon of the upper layer (3b) to the attack speed of the insulating material is at minus 10.
4. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que dans l'étape d), d'aplanissement par le polissage mécano-chimique est assisté d'une détection de fin d'attaque s'effectuant sur la couche supérieure (3b) en silicium polycristallin agissant alors en tant que couche d'arrêt du polissage.4. Method according to any one of claims 1 to 3, characterized in that in step d), leveling by chemical mechanical polishing is assisted by an end of attack detection taking place on the upper layer (3b) of polycrystalline silicon then acting as a polishing stop layer.
5. Procédé selon l'une quelconque des revendications 1 à 4, caractérisé en ce que dans l'étape d), la vitesse d'attaque du silicium polycristallin de la couche supérieure (3b) diffère de la vitesse d'attaque du nitrure de silicium de la couche inférieure (3a) d'au moins un facteur 10.5. Method according to any one of claims 1 to 4, characterized in that in step d), the attack speed of the polycrystalline silicon of the upper layer (3b) differs from the attack speed of the nitride of silicon of the lower layer (3a) by at least a factor of 10.
6. Procédé selon la revendication 5, caractérisé en ce que dans l'étape d), l'aplanissement par polissage mécano-chimique est assistée d'une détection de fin d'attaque s'effectuant sur la couche inférieure (3a) en nitrure de silicium.6. Method according to claim 5, characterized in that in step d), the planarization by chemical mechanical polishing is assisted by an end of attack detection taking place on the lower nitride layer (3a) of silicon.
7. Procédé selon l'une quelconque des revendications 1 à 6, caractérisé en ce que l'épaisseur de la bicouche de protection (3) est comprise entre 500 et 2000 À, typiquement 1000 À. 7. Method according to any one of claims 1 to 6, characterized in that the thickness of the protective bilayer (3) is between 500 and 2000 Å, typically 1000 Å.
8. Procédé selon l'une quelconque des revendications 1 à 7, caractérisé en ce que l'épaisseur de la couche supérieure (3b) est de l'ordre de 300 Â, avec un rapport d'épaisseur de la couche inférieure (3a) à la couche supérieure (3b) compris entre 0,3 et 1, typiquement de l'ordre de 1. 8. Method according to any one of claims 1 to 7, characterized in that the thickness of the upper layer (3b) is of the order of 300 Â, with a thickness ratio of the lower layer (3a) to the upper layer (3b) of between 0.3 and 1, typically of the order of 1.
PCT/FR1996/001844 1995-11-23 1996-11-21 Side trench isolation method using a two-component protective layer of polysilicon on silicon nitride for insulator layer planarisation by chemical-mechanical polishing WO1997019467A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
FR9513917A FR2741749B1 (en) 1995-11-23 1995-11-23 METHOD OF LATERAL ISOLATION BY TRENCHES USING A SACRIFICIAL LAYER FOR MECHANICAL CHEMICAL POLISHING OF THE INSULATION LAYER
FR95/13916 1995-11-23
FR95/13917 1995-11-23
FR9513916A FR2741748B1 (en) 1995-11-23 1995-11-23 LATERAL ISOLATION METHOD WITH MECHANICAL CHEMICAL POLISHING OF THE INSULATOR ASSISTED BY AN ATTACK DETECTION

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2797603A1 (en) * 1997-09-01 2001-02-23 United Microelectronics Corp Shallow trench isolation production, especially in a silicon wafer in VLSI or ULSI manufacture, involves insulation layer planarization using a chemical-mechanical polishing holder sleeve having suspension passages
US6117748A (en) * 1998-04-15 2000-09-12 Worldwide Semiconductor Manufacturing Corporation Dishing free process for shallow trench isolation
EP1295321A1 (en) * 2000-01-27 2003-03-26 Infineon Technologies North America Corp. Planarization process to achieve improved uniformity across semiconductor wafers
WO2001084625A1 (en) * 2000-05-02 2001-11-08 Advanced Micro Devices, Inc. Flash memory array and a method and system of fabrication thereof
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US6610580B1 (en) 2000-05-02 2003-08-26 Advanced Micro Devices, Inc. Flash memory array and a method and system of fabrication thereof
SG103325A1 (en) * 2001-01-16 2004-04-29 Chartered Semiconductor Mfg Extended poly buffer sti scheme
FR2910180A1 (en) * 2006-12-15 2008-06-20 St Microelectronics Complementary MOS transistor e.g. dual metal gates transistor, manufacturing method for integrated electronic circuit, involves performing chemical mechanical polishing until mask layers are attained, and eliminating deposited mask layers

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