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WO1997015072A1 - Procede de production d'un dispositif a semi-conducteur, comprenant une etape d'implantation - Google Patents

Procede de production d'un dispositif a semi-conducteur, comprenant une etape d'implantation Download PDF

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Publication number
WO1997015072A1
WO1997015072A1 PCT/SE1996/001206 SE9601206W WO9715072A1 WO 1997015072 A1 WO1997015072 A1 WO 1997015072A1 SE 9601206 W SE9601206 W SE 9601206W WO 9715072 A1 WO9715072 A1 WO 9715072A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
sic
semiconductor
annealing
Prior art date
Application number
PCT/SE1996/001206
Other languages
English (en)
Inventor
Christopher Harris
Kurt Rottner
Original Assignee
Abb Research Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/544,979 priority Critical patent/US5849620A/en
Priority claimed from US08/544,979 external-priority patent/US5849620A/en
Application filed by Abb Research Limited filed Critical Abb Research Limited
Priority to EP96935659A priority patent/EP0870323A1/fr
Publication of WO1997015072A1 publication Critical patent/WO1997015072A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • a method for producing a semiconductor device compri- sing an implantation step
  • the present invention relates to a method for produc ⁇ ing a semiconductor device having a semiconductor layer of SiC, said method comprising at least the steps of applying an insulating layer on said semi ⁇ conductor layer, implantation of an impurity dopant -Into said semiconductor layer and annealing this layer at such a high temperature that the implanted impurities are activated, said insulating layer being applied before and maintained on said semiconductor layer during said annealing step.
  • the production of all types of semiconductor devices is comprised, such as for example different types of diodes, transistors and thyristors.
  • SiC has a high thermal stability due to a large band gap energy, such that devices fabricated from said material are able to operate at high temperatures, namely up to 1000 K. Furthermore, it has a high thermal conductivity, so that SiC- devices can dissipate a high power without overheat ⁇ ing. SiC also has a more than five times higher breakdown field than Si , so that it is well suited as a material in high power devices operating under con ⁇ ditions where high voltages may occur in the blocking state of a device .
  • US patent 5 384 270 describes a method of producing a silicon carbide MOSFET using a so called self alignment technique, i.e. the implan- tation of impurity dopants into said semiconductor layer of SiC is made while using layers comprising the device itself, here the gate electrode, as a mask for the ion implantation. Accordingly, the insulating layer has to be there before the ion implantation and will also be there during the following annealing step.
  • Si ⁇ 2 is accordingly used as insulating layer and the annealing temperature required for efficient activation after an implanta ⁇ tion will damage the insulating layer, so that a semiconductor device produced in the way described in this US patent will not have an appropriate function, especially will the insulating properties be degraded and the conductivity in the inversion channel will be reduced.
  • the object of the present invention is to provide a method according to the introduction, which makes it possible to produce semiconductor devices having a semiconductor layer of SiC by using ion implantation while solving the problems discussed above.
  • This object is in accordance with the invention obtained by applying a material having AIN as major component on said semiconductor layer as said insu ⁇ lating layer.
  • AIN can be made stable at least up to 2000 K and thus well capable of withstanding the high temperature activation anneal following the implanta- tion step, so that this insulating layer will not be destroyed by said annealing.
  • AIN has a very good lattice match with SiC with a misfit of only 0,7% and it has nearly the same coefficient of thermal expansion as SiC, so that it will be possible to grow an insulating layer having AIN as a major component with a high quality on the SiC semiconduc ⁇ tor layer, and this insulating layer will not be negatively affected by the high annealing tempera ⁇ tures required for activating impurities implanted in SiC.
  • the expression "as major component” means that it will be possible to add some other components to AIN for forming said insulating layer, such as smaller amounts of other Group III B-nitrides should this be desired, but such additions will decreasing the lattice match with SiC.
  • a material having AIN as major component as an insulating layer in a method for producing a semiconductor device of this type has many advantages, which will appear from the discussion of preferred embodiments of the invention following below, wherein said insulating layer may be used for utilising the self aligned technology for isolated gate devices, as a mask for said implantation and be left on the device as a pas ⁇ sivation layer and so on.
  • the material is Al x B ( i__ x) N.
  • B the lattice match of the insulating layer to SiC may be improved.
  • a theoretical perfect lattice match will be obtained when x is about 0,96, i.e. the B- content is about 4%.
  • a B-content in AIN will also in- crease the bandgap and the breakdown voltage thereof.
  • AIBN is more resistent to oxidation than AIN.
  • said method comprises at least a step of self aligned implantation, and said insulating layer is present during this step.
  • a layer having AIN as major component as the in ⁇ sulating dielectric
  • the insulating layer is not degraded by the activation anneal, so that this very advantageous technique for the production of semicon ⁇ ductor devices may be used also for the production of isolated gate devices with a semiconductor layer of SiC.
  • This technique is very advantageous with respect to other production techniques, since you do not need any realignment between the different steps .
  • a gate material this material being a suit ⁇ able refractory metal, for example Ta, layer for said semiconductor device is applied on said insulating layer before said step of self aligned implantation, said gate material layer leaving at least one opening for the penetration of the implanted impurity dopant into said semiconductor layer during said step of self aligned implantation for making the implanted region in said semiconductor layer aligned with said opening.
  • This method has the advantages discussed above, and it may for instance be used for the production of isolated gates semiconductor devices with an insulating layer still having an excellent quality after the high temperature anneal for acti ⁇ vating the impurity dopant implanted in the SiC- layer.
  • said method comprises a step of implantation of a P-type impurity dopant, and said insulating layer is present during the activation annealing af ⁇ ter this implantation. It is very advantageous to be able to introduce acceptors as impurity dopants by the implantation technique, since these acceptors need a higher annealing temperature for being acti ⁇ vated than the donors, so that this case is particu ⁇ larly troublesome with known insulating materials, but the thermal stability of AIN allows these high temperatures .
  • said insulating layer is used as a mask for implantation for preventing the areas of said semi ⁇ conductor layer located therebehind being reached by the impurities implanted.
  • the use of an insulating layer having AIN as major component as an implanta ⁇ tion mask is very advantageous, since AIN is a radiation hard material, i.e. it is only damaged on the surface due to a high resistance to implantation and the ions so implanted in the surface layer thereof will not diffuse through said mask to the in ⁇ terface with the semiconductor layer during the annealing step.
  • a layer having AIN as major component can therefore be used as an implantation mask enabling structures to be defined in a non-mesa planar technology, for example implanted p-n diodes, field rings etc. The mask layer will remain intact as a means of device isolation (passivation) .
  • said gate is made of a refractory metal, and this metal is TiN.
  • This refractory metal makes it possible to use the self aligned technology for producing isolated gate devices having a semiconductor layer of SiC, since it will not be damaged by the high annealing tempera ⁇ tures needed for activation of the impurities im ⁇ planted.
  • the gate of TiN and said insulating layer when it is made of AIN, may be grown in one single growth run facilitating the production of the semiconductor device.
  • said insulating layer is applied on said semiconductor layer at a thickness allowing implanta ⁇ tion therethrough but adapted to prevent out-diffu- sion of the dopants and Si-evaporation from the SiC surface during said annealing step. Selecting such a thickness of the insulating layer will make it possible to allow implantation into the SiC-layer therebehind while at the same time taking advantage of the low diffusivity in AIN for preventing out-dif ⁇ fusion and Si-evaporation during the high temperature annealing step.
  • the invention also comprises a use of a material hav ⁇ ing AIN as major component in a semiconductor device having a semiconductor layer of SiC, said device be ⁇ ing created by a method comprising ion implantation and annealing at high temperatures for activating the implant in the presence of said material, as well as a semiconductor device produced by carrying out a method comprising the characteristics according to any of the appended method claims .
  • a material hav ⁇ ing AIN as major component in a semiconductor device having a semiconductor layer of SiC, said device be ⁇ ing created by a method comprising ion implantation and annealing at high temperatures for activating the implant in the presence of said material, as well as a semiconductor device produced by carrying out a method comprising the characteristics according to any of the appended method claims .
  • Fig 1 - 4 illustrate schematically different steps of a method for producing a semiconductor power device in the form of an isolated gate device of SiC accord ⁇ ing to a first preferred embodiment of the invention
  • Fig 5-6 illustrate schematically two of the steps of a method for producing a semiconductor power device in the form of a rectifier diode of SiC according to a second preferred embodiment of the invention.
  • Fig 1 - 4 illustrate a few important steps of a large number of steps of a method according to the inven- tion for producing an isolated gate device made of SiC for a high power application by using the implan ⁇ tation technique and in one step the self alignment technique.
  • a thin insulating layer 1 of AIN has been epitaxially grown onto a low doped N-type semiconduc- tor layer 2 of SiC, and a mask 3 is applied onto an area of said insulating layer 1 for preventing that the areas of said semiconductor layer located there- behind are reached by the impurities implanted in an ion implantation step described below.
  • the insulating layer 1 may have a thickness of about 500 A allowing implantation therethrough.
  • the donor concentration in the low doped layer 2 will typically be about 10 ⁇ 5 cm ⁇ 3.
  • the crystal is exposed to a bombardment of ions having a kinetic energy of several hundred keV or more, for instance 300 keV, for implanting impurities of P-type into said semiconductor layer 2. These high energies are needed as a consequence of the physical properties of SiC, and a kinetic energy of 300 keV may for instance result in a penetration depth of less than 1 ⁇ m in the SiC-layer.
  • Said impurities may for instance be B or Al .
  • the implantation process is indicated by the arrows 4. In this way a doped P-type layer 5 will be formed in the SiC crystal in the area not covered by said mask 3.
  • etching Reactive Ion Etching
  • RIE Reactive Ion Etching
  • the insulating layer 1 of AIN is well capable of with ⁇ standing these high temperature activation anneal and will also prevent out-diffusion of the dopants and Si-evaporation from the SiC-surface during the annealing step.
  • Fig 2 shows the crystal after said annealing step. After that a gate electrode material 6 is applied on a part of the insulating layer 1, and a further mask 7 is applied on another part thereof leaving an opening 8 therebetween for ion implanta ⁇ tion.
  • Said gate electrode 6 is made of a refractory metal, for instance TiN.
  • an implantation step (see arrows 9) is carried out for implantation cf a N-type impurity dopant in the SiC-layer behind said opening 8.
  • a highly doped, for instance 10 ⁇ - cm " 3/ N-type layer 10 is obtained.
  • This layer 10 is aligned with the gate electrode 6, which will remain intact in the semiconductor device, so that this implantation step uses the self alignment technology.
  • said mask 7 is removed and the crystal is annealed for activating the donors im ⁇ planted in the highly doped N-type layer 10.
  • the A1N- layer 1 will have the same function during this annealing step as during the annealing step described above.
  • a source area covering the implanted N + -layer and also partly the P-layer is etched away and a metal contact layer 11 forming the source is grown.
  • a semiconductor device having a gate 6 isolated by an isolating layer 1 having a high quality has been produced by using the self aligned technology.
  • the device has a source 11 and a drain not shown connected to the N + substrate on which the low-doped N-type layer 2 is grown.
  • the current through this device may be controlled by controlling the gate potential.
  • Fig 5 and 6 illustrate some steps of another pre ⁇ ferred method according to the invention, in which AIN is used as a material for an implantation mask and left after said implantation for passivation pur ⁇ poses.
  • a layer 12 of AIN is grown onto a low-doped N- type SiC crystal 13.
  • insulating layer material is removed by a suitable technique, so that there will be a thin layer portion 14 having a thickness allowing the penetration of ions therethrough during an implanta ⁇ tion step thereafter.
  • the thickness of this layer portion 14 may be for instance 0,05 ⁇ m, whereas the thickness of the rest of the layer 12 may be for instance 1 ⁇ m, which will be enough for preventing implantation ions to reach the interface between said layer 12 and the SiC semiconductor layer 13.
  • a layer of AIN having a thickness of 1,28 ⁇ m will be required to prevent boron having a kinetic energy of 1 MeV from penetrating to said in ⁇ terface, and boron is the P-type impurity that penetrates most deeply into a layer of AIN.
  • a mask made of AIN or having AIN as major component may be made comparatively thin thanks to the radiation hardness of AIN.
  • a P-type impurity for instance Al or B
  • these impurities will penetrate through the thin layer portion 14 but not through the layer 12 forming an implantation mask.
  • a P-type doped region 16 is formed below or behind said layer portion 14.
  • the crystal is annealed at a temperature above 1700°C for activating the acceptors in said region 16. During this anneal said thin layer portion 14 prevents out-diffusion of dopants from the region 16, and the layer 12 will not in any way be harmed by the high temperatures thanks to the physi ⁇ cal properties of AIN.
  • said layer portion 14 is removed by for instance reactive ion etching, and an ohmic contact 17 is af ⁇ ter that applied in the opening so formed in the in- sulating layer 12.
  • the insulating layer 12 is then left as a passivation layer of the rectifier diode so created.
  • an insulating layer of AIN or of a material having AIN as major component makes it possible to use the ion implantation technique for p-roducing semiconductor devices of SiC when it is a requirement or a desire to have said insulating layer present during the high temperature anneal for activating the impurity dopant implanted.
  • the invention is ap ⁇ plicable to all types of semiconductor devices, preferably semiconductor devices adapted to operate under extreme conditions, such as high voltages and the generation of large amounts of heat, while taking advantage of the physical properties of SiC.
  • the invention does not only cover methods for produc- ing SiC semiconductor devices according to the two embodiments described above, but every production method in which an implantation and after that an an- nealing takes place in the presence of an insulating layer is within the scope of the invention.
  • the invention also comprises methods in which N-type impurity dopants, such as N and P, are implanted and a high temperature activating anneal is used thereaf ⁇ ter.
  • the definition layer is to be interpreted broadly and comprise all types of volume extensions and shapes.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Cette invention concerne un procédé de production d'un dispositif à semi-conducteur comportant une couche semi-conductrice (2) de SiC, lequel procédé consiste au moins à appliquer une couche d'isolation (1) sur ladite couche semi-conductrice, à implanter un dopant d'impuretés dans ladite couche semi-conductrice et à recuire cette couche à une température suffisamment élevée pour que les impuretés implantées soient activées. Cette couche d'isolation est appliquée sur la couche semi-conductrice avant l'étape de recuit, et maintenue sur cette dernière tout au long cette même étape. Un matériau comportant du AlN en qualité de composant principal, est ensuite appliqué sur la couche semi-conductrice de manière à former ladite couche isolante.
PCT/SE1996/001206 1995-10-18 1996-09-27 Procede de production d'un dispositif a semi-conducteur, comprenant une etape d'implantation WO1997015072A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US08/544,979 US5849620A (en) 1995-10-18 1995-10-30 Method for producing a semiconductor device comprising an implantation step
EP96935659A EP0870323A1 (fr) 1995-10-18 1996-09-27 Procede de production d'un dispositif a semi-conducteur, comprenant une etape d'implantation

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
SE9503631A SE9503631D0 (sv) 1995-10-18 1995-10-18 A method for producing a semiconductor device comprising an implantation step
SE9503631-5 1995-10-18
US08/544,979 US5849620A (en) 1995-10-18 1995-10-30 Method for producing a semiconductor device comprising an implantation step

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WO1997015072A1 true WO1997015072A1 (fr) 1997-04-24

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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629011A (en) * 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US3999206A (en) * 1974-11-04 1976-12-21 Vladimir Alexandrovich Babenko Semiconductor indicating device and method for production of same
US4030942A (en) * 1975-10-28 1977-06-21 International Business Machines Corporation Semiconductor masking for device fabrication utilizing ion implantation and other methods
US4058413A (en) * 1976-05-13 1977-11-15 The United States Of America As Represented By The Secretary Of The Air Force Ion implantation method for the fabrication of gallium arsenide semiconductor devices utilizing an aluminum nitride protective capping layer
US4173063A (en) * 1976-07-15 1979-11-06 Siemens Aktiengesellschaft Fabrication of a semiconductor component element having a Schottky contact and little series resistance utilizing special masking in combination with ion implantation
DD221591A1 (de) * 1983-11-30 1985-04-24 Gera Elektronik Veb Formierverfahren fuer hochvoltanodenfolie
US5384270A (en) * 1992-11-12 1995-01-24 Fuji Electric Co., Ltd. Method of producing silicon carbide MOSFET
EP0697714A1 (fr) * 1994-08-18 1996-02-21 Samsung Electronics Co., Ltd. Procédé pour former une électrode grille d'un dispositif semi-conducteur
WO1996032743A1 (fr) * 1995-04-10 1996-10-17 Abb Research Limited PROCEDE COMPRENANT UNE ETAPE DE MASQUAGE POUR L'ELABORATION D'UN DISPOSITIF SEMI-CONDUCTEUR COMPORTANT UNE COUCHE SEMI-CONDUCTRICE DE SiC

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3629011A (en) * 1967-09-11 1971-12-21 Matsushita Electric Ind Co Ltd Method for diffusing an impurity substance into silicon carbide
US3999206A (en) * 1974-11-04 1976-12-21 Vladimir Alexandrovich Babenko Semiconductor indicating device and method for production of same
US4030942A (en) * 1975-10-28 1977-06-21 International Business Machines Corporation Semiconductor masking for device fabrication utilizing ion implantation and other methods
US4058413A (en) * 1976-05-13 1977-11-15 The United States Of America As Represented By The Secretary Of The Air Force Ion implantation method for the fabrication of gallium arsenide semiconductor devices utilizing an aluminum nitride protective capping layer
US4173063A (en) * 1976-07-15 1979-11-06 Siemens Aktiengesellschaft Fabrication of a semiconductor component element having a Schottky contact and little series resistance utilizing special masking in combination with ion implantation
DD221591A1 (de) * 1983-11-30 1985-04-24 Gera Elektronik Veb Formierverfahren fuer hochvoltanodenfolie
US5384270A (en) * 1992-11-12 1995-01-24 Fuji Electric Co., Ltd. Method of producing silicon carbide MOSFET
EP0697714A1 (fr) * 1994-08-18 1996-02-21 Samsung Electronics Co., Ltd. Procédé pour former une électrode grille d'un dispositif semi-conducteur
WO1996032743A1 (fr) * 1995-04-10 1996-10-17 Abb Research Limited PROCEDE COMPRENANT UNE ETAPE DE MASQUAGE POUR L'ELABORATION D'UN DISPOSITIF SEMI-CONDUCTEUR COMPORTANT UNE COUCHE SEMI-CONDUCTRICE DE SiC

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY, Volume 6, 1969, A.J. NOREIKA et al., "Structural, Optical and Dielectric Properties of Reactively Sputtered Films in the System AIN-BN", pages 722-726. *
PATENT ABSTRACTS OF JAPAN, Vol. 7, No. 222, E-201; & JP,A,58 112 372 (YOKOYAMA NAOKI), 4 July 1983. *

Also Published As

Publication number Publication date
SE9503631D0 (sv) 1995-10-18
EP0870323A1 (fr) 1998-10-14

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