WO1997014220A3 - Electrically reprogrammable, reduced power, programmable logic device circuit - Google Patents
Electrically reprogrammable, reduced power, programmable logic device circuit Download PDFInfo
- Publication number
- WO1997014220A3 WO1997014220A3 PCT/IB1996/001041 IB9601041W WO9714220A3 WO 1997014220 A3 WO1997014220 A3 WO 1997014220A3 IB 9601041 W IB9601041 W IB 9601041W WO 9714220 A3 WO9714220 A3 WO 9714220A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gates
- arrays
- programmable logic
- logic device
- reduced power
- Prior art date
Links
- 238000003491 array Methods 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
- H03K19/1736—Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAS. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits. These arrays may be programmed by EEPROM or EPROM transistors or in the alternative, binary latches may be used to store information determinative of the desired programming.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US54324795A | 1995-10-13 | 1995-10-13 | |
US08/543,247 | 1995-10-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997014220A2 WO1997014220A2 (en) | 1997-04-17 |
WO1997014220A3 true WO1997014220A3 (en) | 1997-05-09 |
Family
ID=24167202
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1996/001041 WO1997014220A2 (en) | 1995-10-13 | 1996-10-03 | Electrically reprogrammable, reduced power, programmable logic device circuit |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO1997014220A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6424567B1 (en) | 1999-07-07 | 2002-07-23 | Philips Electronics North America Corporation | Fast reconfigurable programmable device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4636661A (en) * | 1984-12-21 | 1987-01-13 | Signetics Corporation | Ratioless FET programmable logic array |
US4652777A (en) * | 1984-12-18 | 1987-03-24 | Cline Ronald L | CMOS programmable logic array |
US5270587A (en) * | 1992-01-06 | 1993-12-14 | Micron Technology, Inc. | CMOS logic cell for high-speed, zero-power programmable array logic devices |
-
1996
- 1996-10-03 WO PCT/IB1996/001041 patent/WO1997014220A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4652777A (en) * | 1984-12-18 | 1987-03-24 | Cline Ronald L | CMOS programmable logic array |
US4636661A (en) * | 1984-12-21 | 1987-01-13 | Signetics Corporation | Ratioless FET programmable logic array |
US5270587A (en) * | 1992-01-06 | 1993-12-14 | Micron Technology, Inc. | CMOS logic cell for high-speed, zero-power programmable array logic devices |
Also Published As
Publication number | Publication date |
---|---|
WO1997014220A2 (en) | 1997-04-17 |
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