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WO1997006599B1 - Efficient in-system programming structure and method for non-volatile programmable logic devices - Google Patents

Efficient in-system programming structure and method for non-volatile programmable logic devices

Info

Publication number
WO1997006599B1
WO1997006599B1 PCT/US1996/013036 US9613036W WO9706599B1 WO 1997006599 B1 WO1997006599 B1 WO 1997006599B1 US 9613036 W US9613036 W US 9613036W WO 9706599 B1 WO9706599 B1 WO 9706599B1
Authority
WO
WIPO (PCT)
Prior art keywords
data
register
isp
address
instruction
Prior art date
Application number
PCT/US1996/013036
Other languages
French (fr)
Other versions
WO1997006599A1 (en
Filing date
Publication date
Priority claimed from US08/512,796 external-priority patent/US5734868A/en
Application filed filed Critical
Priority to EP96927385A priority Critical patent/EP0843915A1/en
Priority to JP9508692A priority patent/JPH11511307A/en
Publication of WO1997006599A1 publication Critical patent/WO1997006599A1/en
Publication of WO1997006599B1 publication Critical patent/WO1997006599B1/en

Links

Abstract

An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin (TDI), a data output pin, an instruction register (103A, 103B), a plurality of data registers (506A, 506B) including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

Claims

AMENDED CLAIMS
[received by the International Bureau on 11 February 1997 (11.02.97); original claim 2 cancelled; original claims 1 and 3 amended; remaining claims unchanged (1 page)] 1 . An in-system progra ming/erasing/veri fying structure for non-volatile programmable logic devices including: a data input pin; a data output pin; an instruction register; a plurality of data registers including an ISP register, wherein said ISP register includes: an address field; a data field; and a status field, wherein said instruction register and said plurality of data registers are coupled to parallel between said data input pin and said data output pin; and a controller for synchronizing the clocking of said instruction register and said plurality of data registers.
2. Cancelled.
3. The in-system progr-imming/erasing/verifying structure in Claim 1 wherein said status field stores a two-bit code.
4. An in-system programming method for a non¬ volatile programmable logic device including: shifting a program instruction into an instruction register, thereby selecting an ISP register as the active data register; shifting an address, data, and status code into said ISP register; initiating a programming pulse for said data at said address; terminating said programming pulse; and automatically performing a verify operation on said address.
PCT/US1996/013036 1995-08-09 1996-08-09 Efficient in-system programming structure and method for non-volatile programmable logic devices WO1997006599A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96927385A EP0843915A1 (en) 1995-08-09 1996-08-09 Efficient in-system programming structure and method for non-volatile programmable logic devices
JP9508692A JPH11511307A (en) 1995-08-09 1996-08-09 Efficient in-system programming constructs and methods for nonvolatile programmable logic devices

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/512,796 1995-08-09
US08/512,796 US5734868A (en) 1995-08-09 1995-08-09 Efficient in-system programming structure and method for non-volatile programmable logic devices

Publications (2)

Publication Number Publication Date
WO1997006599A1 WO1997006599A1 (en) 1997-02-20
WO1997006599B1 true WO1997006599B1 (en) 1997-03-20

Family

ID=24040601

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/013036 WO1997006599A1 (en) 1995-08-09 1996-08-09 Efficient in-system programming structure and method for non-volatile programmable logic devices

Country Status (4)

Country Link
US (2) US5734868A (en)
EP (1) EP0843915A1 (en)
JP (1) JPH11511307A (en)
WO (1) WO1997006599A1 (en)

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