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WO1997001768A2 - Systeme d'imagerie ultrasonique portatif - Google Patents

Systeme d'imagerie ultrasonique portatif Download PDF

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Publication number
WO1997001768A2
WO1997001768A2 PCT/US1996/011166 US9611166W WO9701768A2 WO 1997001768 A2 WO1997001768 A2 WO 1997001768A2 US 9611166 W US9611166 W US 9611166W WO 9701768 A2 WO9701768 A2 WO 9701768A2
Authority
WO
WIPO (PCT)
Prior art keywords
delay
circuitry
signals
ultrasonic
array
Prior art date
Application number
PCT/US1996/011166
Other languages
English (en)
Other versions
WO1997001768A3 (fr
Inventor
Alice M. Chiang
Steven R. Broadstone
Original Assignee
Teratech Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/496,805 external-priority patent/US5839442A/en
Priority claimed from US08/496,804 external-priority patent/US5590658A/en
Application filed by Teratech Corporation filed Critical Teratech Corporation
Priority to JP9504611A priority Critical patent/JPH11508461A/ja
Priority to AU63446/96A priority patent/AU700274B2/en
Priority to US08/981,427 priority patent/US5964709A/en
Priority to EP96922638A priority patent/EP0835458A2/fr
Priority to US08/773,647 priority patent/US5904652A/en
Publication of WO1997001768A2 publication Critical patent/WO1997001768A2/fr
Publication of WO1997001768A3 publication Critical patent/WO1997001768A3/fr
Priority to US08/971,938 priority patent/US5957846A/en
Priority to KR19970709973A priority patent/KR19990028651A/ko
Priority to US09/203,877 priority patent/US6248073B1/en
Priority to US09/447,144 priority patent/US6379304B1/en
Priority to US10/114,183 priority patent/US20030028113A1/en
Priority to US11/981,759 priority patent/US8241217B2/en
Priority to US12/006,830 priority patent/US8628474B2/en
Priority to US12/008,098 priority patent/US8469893B2/en
Priority to US13/925,346 priority patent/US20180310913A9/en
Priority to US14/154,072 priority patent/US20140128740A1/en

Links

Classifications

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    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
    • G01S15/88—Sonar systems specially adapted for specific applications
    • G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
    • G01S15/8906—Short-range imaging systems; Acoustic microscope systems using pulse-echo techniques
    • G01S15/8979—Combined Doppler and pulse-echo imaging systems
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    • A61B8/4209—Details of probe positioning or probe attachment to the patient by using holders, e.g. positioning frames
    • A61B8/4236—Details of probe positioning or probe attachment to the patient by using holders, e.g. positioning frames characterised by adhesive patches
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    • A61B8/46—Ultrasonic, sonic or infrasonic diagnostic devices with special arrangements for interfacing with the operator or the patient
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    • A61B8/463—Displaying means of special interest characterised by displaying multiple images or images and diagnostic data on one display
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    • A61B2560/04—Constructional details of apparatus
    • A61B2560/0443—Modular apparatus
    • A61B2560/045—Modular apparatus with a separable interface unit, e.g. for communication
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    • A61B8/4483—Constructional features of the ultrasonic, sonic or infrasonic diagnostic device characterised by features of the ultrasound transducer
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    • G—PHYSICS
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Definitions

  • Conventional ultrasound imaging systems typically include a hand-held scan head coupled by a cable to a large rack-mounted console processing and display unit .
  • the scan head typically includes an array of ultrasonic transducers which transmit ultrasonic energy into a region being imaged and receive reflected ultrasonic energy returning from the region.
  • the transducers convert the received ultrasonic energy into low-level electrical signals which are transferred over the cable to the processing unit.
  • the processing unit applies appropriate beam forming techniques such as dynamic focusing to combine the signals from the transducers to generate an image of the region of interest.
  • Typical conventional ultrasound systems can have transducer arrays which consist of 128 ultrasonic transducers.
  • Each of the transducers is associated with its own processing circuitry located in the console processing unit.
  • the processing circuitry typically includes driver circuits which, in the transmit mode, send precisely timed drive pulses to the transducer to initiate transmission of the ultrasonic signal. These transmit timing pulses are forwarded from the console processing unit along the cable to the scan head.
  • beam forming circuits of the processing circuitry introduce the appropriate delay into each low-level electrical signal from the transducers to dynamically focus the signals such that an accurate image can subsequently be generated.
  • FIG. IA A schematic block diagram of an imaging array 18 of N piezoelectric ultrasonic transducers 18(1)-18(N) as used in an ultrasound imaging system is shown in FIG. IA.
  • the array of piezoelectric transducer elements 18(1)-18(N) generate acoustic pulses which propagate into the image target (typically a region of human tissue) or transmitting media with a narrow beam.
  • the pulses propagate as a spherical wave with a constant velocity.
  • Acoustic echoes in the form of returning signals from image points P or reflectors are detected by the same array 18 of transducer elements or another receiving array and can be displayed in a fashion to indicate the location of the reflecting structure P.
  • the acoustic echo from the point P in the transmitting media reaches each transducer element 18(1)-18(N) of the receiving array after various propagation times.
  • the propagation time for each transducer element is different and depends on the distance between each transducer element and the point P. This holds true for typical ultrasound transmitting media, i.e. soft bodily tissue, where the velocity of sound is assumed (or relatively) constant.
  • the received information is displayed in a manner to indicate the location of the reflecting structure.
  • the pulses can be transmitted along a number of lines-of-sight as shown in FIG. IA. If the echoes are sampled and their amplitudes are coded as brightness, a grey scale image can be displayed on a CRT.
  • An image typically contains 128 such scanned lines at 0.75° angular spacing, forming a 90° sector image. Since the velocity of sound in water is 1.54 x IO 5 cm/sec, the round-trip time to a depth of 16 cm will be 208 ⁇ s . Thus, the total time required to acquire data along 128 lines of sight (for one image) is 26.6 ms. If other signal processors in the system are fast enough to keep up with this data acquisition rate, two-dimensional images can be produced at rates corresponding to standard television video. For example, if the ultrasound imager is used to view reflected or back scattered sound waves through the chest wall between a pair of ribs, the heart pumping can be imaged in real time.
  • the ultrasonic transmitter is typically a linear array of piezoelectric transducers 18(1)-18(N) (typically spaced half-wavelength apart) for steered arrays whose elevation pattern is fixed and whose azimuth pattern is controlled primarily by delay steering.
  • the radiating (azimuth) beam pattern of a conventional array is controlled primarily by applying delayed transmitting pulses to each transducer element 18 (1) -18 (N) in such a manner that the energy from all the transmitters summed together at the image point P produce a desired beam shape. Therefore, a time delay circuit is needed in association with each transducer element 18(1)-18(N) for producing the desired transmitted radiation pattern along the predetermined direction. For a given azimuth angle, as can be seen in FIG.
  • the single-focus method employs a single pulse focused at mid-range of the image line along a particular line of sight.
  • the azimuth focus depth can be electronically varied, but remains constant for any predetermined direction.
  • zone-focus operation multiple pulses, each focused at a different depth (zone) , are transmitted along each line of sight or direction.
  • the array of transmitters is focused at M focal zones along each scan direction, i.e., a series of M pulses is generated, P 0 , P 17 ... , P M-1 , each pulse being focused at its corresponding range R 0 , R 1# ...
  • the pulses are generated in a repeated sequence so that, after start up, every Mth pulse either begins a look down a new direction or corresponds to the initial pulse P 0 to repeat the series of looks down the present direction.
  • a programmable time-delay circuit is needed in association with each transducer element to produce beam patterns focused at different focal zones.
  • the same array 18 of transducer elements 18(1)-18(N) can be used for receiving the return signals.
  • the reflected or echoed beam energy waveform originating at the image point reaches each transducer element after a time delay equal to the distance from the image point to the transducer element divided by the assumed constant speed of the waveform of signals in the media. Similar to the transmitting mode, this time delay is different for each transducer element.
  • these differences in path length should be compensated for by focusing the reflected energy at each receiver from the particular image point for any given depth.
  • the delay at each receiving element is a function of the distance measured from the element to the center of the array and the viewing angular direction measured normal to the array. It should be noted that in ultrasound, acoustic pulses generated by each transducer are not wideband signals and should be represented in terms of both magnitude and phase.
  • the beam forming and focusing operations involve forming a sum of the scattered waveforms as observed by all the transducers, but in this sum, the waveforms must be differentially delayed so that they will all arrive in phase and in amplitude in the summation.
  • FIGs. 2A-2C show schematic block diagrams of three different conventional imaging or beam focusing techniques.
  • a non-programmable physical lens acoustic system 50 using an acoustic lens 51 is shown in FIG. 2A.
  • dynamic focusing systems where associated signal processing electronics are employed to perform real-time time delay and phase delay focusing functions are respectively shown in FIGs. 2B and 2C.
  • FIG. 2B shows a time delay system 52 using time delay elements 53
  • FIG. 2C shows a phase delay system 54 using phase delay elements 55.
  • the signal processing elements 53, 55 are needed in association with each receiving transducer element, thus defining processing channels, to provide time delay and focus incident energy from a field point to form an image. Accordingly, a beam forming circuit is required which can provide a different delay on each processing channel, and to further vary that delay with time.
  • the receiving array varies its focus continually with depth to perform dynamic focusing.
  • each received pulse is digitized in a conventional manner.
  • the digital representation of each received pulse is a time sequence corresponding to a scattering cross section of ultrasonic energy returning from a field point as a function of range at the azimuth formed by the beam. Successive pulses are pointed in different directions, covering a field of view from -45° to +45°.
  • time averaging of data from successive observations of the same point (referred to as persistence weighting) is used to improve image quality.
  • an electronic circuit capable of providing up to 10 to 20 ⁇ s delay with sub-microsecond time resolution is needed for the desired exact path compensation.
  • a delay line is inherently matched to the time-delay function needed for dynamic focusing in a lensless ultrasound system.
  • each processing channel/transducer element requires each processing channel/transducer element to include either a 480-stage delay line with a clock period programmable with a 25ns resolution or a 480-stage tapped delay line clocked at 40MHz in conjunction with a programmable 480-to-one time-select switch to set the appropriate delay.
  • a simple variable-speed clock generator has not been developed to date.
  • the area associated with the tap select circuit is proportional to N 2 , thus such a circuit would require a large amount of microchip area to realize an integrated tap architecture.
  • the fine delay can be achieved by modifying the phase of AC waves received by each receiving processing channel and implemented by heterodyning the received waves from each receiving transducer element with different phases of a local oscillator, i.e., creating analog phase shifting at each processing channel.
  • a tap select which connects any received down-conversion mixer output to any tap on a coarsely spaced, serially connected delay line.
  • the tap select is essentially a multiposition switch that connects its input to one of a number of output leads. One output lead is provided for each tap on the delay line. Therefore, each mixer output can be connected to a few coarsely spaced taps on a delay line, and all the tap outputs can be summed together coherently.
  • a delay line with delay resolution less than one microsecond is needed.
  • the conventional technique described heretofore involves heterodyning the received signals with an oscillator output by selecting a local oscillator frequency so as to down convert the output to an IF frequency. This down converted signal is then applied to another mixer. By selecting the proper phase angle of the second oscillator, the phase of the intermediate frequency waves produced by the second heterodyning is controlled. The output of the second mixer is then connected through a tap select to only one, or at most a few, coarsely spaced taps on a delay line during the focal scanning along each direction.
  • the aforementioned approximation technique is used due to the fact that given an image that is somewhat out of focus, the image can be focused in an economically feasible manner by utilizing readily available techniques such as analog mixers and RC networks. Unfortunately, the mixer approximation method suffers from image misregistration errors as well as signal loss relative to the ideally- focused (perfect delay) case.
  • Modern ultrasound systems require extensive complex signal processing circuitry in order to function. For example, hundreds of delay-and-sum circuits are needed for dynamic beam forming. Also, pulsed or continuous Doppler processors are needed for providing two-dimensional depth and Doppler information in color flow images, and adaptive filters are needed for clutter cancellation.
  • Each of these applications requires more than 10,000 MOPS (million operations per second) to be implemented.
  • Even state-of- the-art CMOS chips only offer several hundred MOPS per chip, and each chip requires a few watts of electric power.
  • an ultrasound machine with a conventional implementation requires hundreds of chips and dissipates hundreds of watts of power. As a result, conventional systems are implemented in the standard large rack-mounted cabinets.
  • Another drawback in conventional ultrasound systems is that the cable connecting the scan head to the processing and display unit is required to be extremely sophisticated and, hence, expensive. Since all the beam forming circuitry is located in the console, all of the low-level electrical signals from the ultrasonic transducers must be coupled from the scan head to the processing circuitry. Because the signals are of such a low level, they are extremely susceptible to noise, crosstalk and loss. With a typical transducer array of 128 transducers, the cable between the scan head and the processing and display console is required to contain 128 low-noise, low-crosstalk and low-loss coaxial cables. Such a cable requires expensive materials and extensive assembly time and is therefore very expensive.
  • the present invention is directed to a portable ultrasound imaging system and method.
  • the imaging system of the invention includes a hand-held scan head coupled to portable processing circuitry by a cable.
  • the scan head includes a housing which houses the array of ultrasonic transducers which transmit the ultrasonic signals into the region of interest being imaged and which receive reflected ultrasonic signals from the region of interest and which convert the received ultrasonic signals into electrical signals.
  • the housing of the scan head also contains the beam forming circuitry used in the imaging system of the invention to combine the electrical signals from the ultrasonic transducers into an electronic representation of the region of interest.
  • the electronic representation of the region of interest is forwarded over an interface via the system cable to data processing and display circuitry which uses the representation to generate an image of the region of interest.
  • the portable processing circuitry is implemented in the form of a lap-top computer which can include an integrated keyboard, a PCMCIA standard modem card for transferring image data and a flip-top flat panel display, such as an active matrix LCD.
  • the lap-top computer and, therefore the entire system, can be powered by a small lightweight battery.
  • the entire system, including scan head, cable and computer is therefore very lightweight and portable.
  • the total weight of the system preferably does not exceed ten pounds .
  • the interior of the scan head can also include a Faraday shield to shield the electronics of the scan head from interference from extraneous RF sources.
  • the system also includes an interface unit between the scan head and the lap-top computer.
  • the system cable is connected to the interface unit.
  • Another cable couples the interface unit to the computer.
  • the interface unit performs control and signal/data processing functions not performed by the computer. This reduces the overall processing load on the computer.
  • CMOS complementary metal-oxide-semiconductor
  • the beam forming circuitry used to introduce individual delays into the received ultrasonic signals can be implemented on a single chip for a 64- element array. Thus, two chips are used for 128-element systems.
  • the pulse synchronizing circuitry used to generate transducer driving pulses can also be implemented on a chip.
  • high voltage driver circuits used in the transmit mode to drive the transducers and preamplifying circuits and gain control circuits used in a receive mode to condition the electrical signals from the transducers can also be integrated on single chips.
  • control circuits such as multiplexer circuits for selecting signals from the transducers and other such control circuits can be formed on single chips .
  • the signal processing circuitry in the scan head is implemented in low-power, high-speed CMOS technology.
  • the integrated circuitry can also be adapted to be operated at lower voltages than conventional circuitry.
  • the power dissipated in the integrated circuitry and, consequently, the thermal effects caused thereby are substantially lower than those of conventional circuits.
  • the total power dissipated in the scan head is less than two watts. This allows the temperature of the scan head to be maintained below 41°C. With such low power dissipation and temperature, the circuits can be implemented in the relatively small volume of the scan head housing without suffering any degradation in performance due to thermal effects. The patient being examined also suffers no harmful thermal effects. Also, because the system requires comparatively little power, it can be powered by a battery located in the data processor and display unit.
  • individual delays are typically introduced into each individual transmitted ultrasonic pulse and into each signal from each transducer indicative of received reflected ultrasonic energy. These individual delays are used to ensure that the image of the region of interest is properly focused.
  • the form or pattern of delays introduced into each transducer element are affected by the shape of the array and the desired region scan pattern. For example, in phased arrays, different individual beam steering delays are introduced into each pulse and/or each returning signal for every scan line to produce a properly focused image of a curved region.
  • Linear and curve linear arrays are typically flat or curved. The arrays can be used to perform linear scanning in which a uniform pattern of delays is introduced to all the transducers. The delays are the same for each scan line. Curved arrays have different delay patterns for each scan line.
  • the present invention is also capable of performing trapezoidal region scans.
  • a linear array is used in a sub- aperture scanning process.
  • the transducer array can include 192 adjacent transducers arranged in a line.
  • only a small portion of the transducers, e.g., 64, are used to generate and receive signals.
  • the transducers at opposite ends of the linear array are used to perform the phased-array scanning process to produce a curved image region at opposite ends of the overall trapezoidal-shaped scan region. Since the phased-array approach is used at the ends of the array, different delay patterns must be introduced for each individual scan line. Between the phased-array portions, linear scanning is used.
  • the trapezoidal scanning embodiment of the invention involves a combination of phased array scanning at both ends of the region and linear scanning in the middle of the region.
  • electronic circuitry capable of providing up to 10-20 ⁇ s delay with sub-microsecond time resolution is needed to provide precise signal path compensation.
  • this wide range of delays with fine resolution is provided by a dual-stage programmable tapped delay line using CCD technology.
  • the first stage introduces a fine delay and the second stage introduces a coarse delay.
  • the delays are controlled by tapping clock frequencies, the fine delay being controlled by a higher clock frequency than the coarse delay.
  • the fine delay clock frequency is set at eight times the ultrasound signal frequency
  • the coarse delay clock frequency is set at one-tenth the fine delay clock frequency.
  • the clock frequencies are separately controllable to facilitate varying the ultrasound signal frequency to vary imaging depth.
  • the frequency of the ultrasound signals is variable to allow for imaging at varying depths .
  • This can be accomplished by internal or external adjustment of transducer signal driving frequency.
  • the system of the invention accommodates different scan heads having arrays which operate at different frequencies.
  • the scan head of the invention can be provided with a facility for changing arrays based on the desired operating frequency.
  • the delay processing circuits utilize a single charge-coupled device delay line with a programmable input sampling selection circuit. The programmable input sampling selection circuit allows nonuniformly sampled imaging signals to be loaded into the programmable delay line to provide the required variable delay.
  • each delay processing circuit includes a programmable input sampling circuit and a programmable delay unit.
  • the programmable sampling circuit converts a continuous-time input waveform into a sequence of discrete-time analog sample data, which can be uniformly or nonuniformly spaced, and which are loaded into the programmable delay unit.
  • a control circuit is included to provide programmable delay to each selected sampled data.
  • a summation circuit is incorporated for summing the sampled, delayed data from each of the delay units to produce a focused image.
  • the control circuit used to control the delay of each sample includes a counter and a storage circuit, which can be a shift register or a memory circuit.
  • the shift register can be formed using CCD technology or other logic circuit technology.
  • the storage circuit is loaded with a series of data values which define the delays used for each focus point along a scan line.
  • counter outputs are compared one at a time to values stored in the shift register. A matched value results in a sample being taken of the signal.
  • the shift register also stores a value that addresses the appropriate stage of the programmable delay line depending upon the predetermined delay for the sample.
  • this delay tap value is stored as a series of data bits with the corresponding value used to provide sampling delay as described above.
  • the two values are combined into a single data word comprising nine data bits, three for the sample delay selection and six for the delay tap selection in the delay line.
  • each scan line includes 512 focus points.
  • the shift register is a 512-stage 9-bit shift register.
  • four bits can be used for sample delay selection and seven for the delay top selection, resulting in a 512-stage 11-bit shift register being used.
  • the 9-bit data words are compressed to permit more efficient storage of the data.
  • each individual delay instead of storing each individual delay, only the differences in delay between adjacent focus points are stored. Each first difference requires fewer bits to store than does the actual absolute delay value.
  • second differences i.e., the difference between adjacent first differences, is stored at each register location. This requires even fewer bits.
  • a processor of the invention reads each difference and integrates it to generate an actual delay value which is used to control both the sampling and tapping of the delay line.
  • a single summing stage is used to perform the integration.
  • a two-stage adder is used.
  • a process referred to as sub-aperture scanning can be implemented.
  • processing circuits are shared by the transducers such that the total number of processing circuits is fewer than the number of transducer elements.
  • the array can include 128 transducer elements but only 64 processing channels.
  • a multiplexing process is used whereby only a portion of the 128 transducers, i.e., a "sub-aperture," is used at one time.
  • a multiplexing circuit is used to route signals from the active transducers to the processing circuitry.
  • 64 transducers are used at once, and they are serviced by the 64 channels of processing circuitry.
  • a next group of transducers is activated to collect more data.
  • a sliding scanning process is used in which each successive group of 64 elements slides over one element, resulting in overlapping sub-aperture scanning regions.
  • a spatial windowing process is used to reduce image clutter, i.e., energy in the image obtained through the side lobes rather than the main lobe of the array response.
  • image clutter i.e., energy in the image obtained through the side lobes rather than the main lobe of the array response.
  • a dynamically varying spatial window or a truncated non-varying spatial window can be used. However, it has been found that the truncated window is easier to implement.
  • the same set of delays is downloaded to memory for the sets of elements.
  • the digital words representing the individual delays are effectively rotated through the memory and control circuits of each processing channel. That is, for the first, group of elements, delay sets numbered 1-64 are loaded into processing channels 1-64, respectively. For the next set, delay sets 1-64 are loaded into processing channels 2-64, 1, respectively. For the next set, delays 1-64 are loaded into channels 3-64, 1-2, respectively, and so forth.
  • This rotational multiplexing of delay data values substantially enhances the efficiency of the invention since the amount of memory required to store all the delays is substantially reduced. The amount of hardware required is also reduced.
  • an adaptive beam forming circuit is used instead of the dual- stage delay line to provide the required delays at the required resolution.
  • a feedback circuit senses summed received signals from a tapped delay line and generates correction signals.
  • the correction signals control individual multiplier weights in the beam forming circuitry to adjust the summed signal and eliminate the effects of clutter and interference from the image.
  • the summed signal is forwarded over the system cable to the data processing and display subsystem of the imaging system.
  • the data processing subsystem includes, among other things, demodulation, log compression and scan conversion circuitry for converting the polar coordinates of received ultrasonic signals to rectangular coordinates suitable for further processing such as display.
  • the scan conversion process of the present invention provides a higher quality image and requires far less complex circuitry than that of prior systems.
  • each point on the (x,y) coordinate system is computed from the values of the four nearest neighbors on the polar (r,0) array by simple linear interpolation. This is accomplished by use of a finite state machine to generate the (x,y) traversal pattern, a bi-directional shift register to hold the (r,0) data samples and a large number of digital logic and memory units to control the process and ensure that the correct samples of (r,0) data arrive for interpolation at the right time for each (x,y) point since the (x,y) data points are received asynchronously.
  • the image data is scan converted, it is post processed in accordance with its eventual intended presentation format.
  • the data can be digitized and formatted for presentation on a display.
  • the (x,y) data values can be presented to a video compression subsystem which compresses the data to allow for data transmission to remote sites by modem or other known communication means.
  • the ultrasound imaging system of the invention also allows for imaging of moving objects by including a pulsed Doppler processing subsystem.
  • Data from the beam forming circuitry is forwarded to the pulsed Doppler processor to generate data used to image the moving object.
  • the pulsed Doppler processor can be used to produce color flow map images of blood flowing through tissue.
  • the data processing and display unit can be a single small battery-operated unit. It can be hand-held or worn clipped to the user or in the user's pocket. This, in conjunction with the hand ⁇ held scan head of the invention, makes the ultrasound system of the invention completely portable.
  • the ultrasound imaging system of the invention has several advantages over prior conventional systems. Because much of the signal processing circuitry is integrated on small chips, the signal processing can be carried out in the scan head.
  • the system includes a small hand-held scan head, a small cable and a portable data processing and display unit such as a lap-top computer or hand-held computer with integrated liquid crystal or other flat panel display and keypad.
  • the image data gathered at a remote site can be transferred by modem or wireless cellular link or other known means to a hospital for evaluation. Treatment instructions can then be relayed back to the operator where the patient can be administered treatment immediately.
  • Another preferred embodiment of the invention involves the above described circuits and methods for a two- dimensional transducer array device.
  • the transducer device provides focusing in a second dimension and can employ a coarser spacing between the rows of a multi-linear array, for example.
  • Another preferred embodiment of the invention involves the use of an ultrasound transducer device in an electronic stethoscope.
  • This system provides both audio information to the user as well as an ultrasound imaging capability.
  • Another preferred embodiment of the invention involves the use of an ultrasound transducer device in a skinpatch. This can be used for cardiac monitoring by positioning the transducer device to transmit and receive between the ribs of a patient.
  • Another preferred embodiment of the invention incorporates the processing and control circuitry described herein in a distal end of an ultrasound internal probe or imaging catheter. This provides a more flexible and less expensive imaging probe that is useful for both diagnosis and treatment.
  • FIGs. IA and IB respectively show a block diagram of a conventional imaging array as used in an ultrasound imaging system and associated transmitting pulse patterns of a single pulse and multiple pulses in a zone-focused mode.
  • FIGs. 2A-2C respectively show block diagrams of three different conventional imaging or beam focusing techniques involving optical lens, time delay and phase delay operations.
  • FIG. 3 is a schematic pictorial view of a preferred embodiment of the ultrasound imaging system of the present invention.
  • FIG. 4 is a schematic functional block diagram of a preferred embodiment of the ultrasound imaging system of the invention.
  • FIG. 5 is a schematic functional block diagram of a preferred embodiment of the ultrasound scan head of the present invention.
  • FIG. 6 shows an operational block diagram of an array of the beam forming and focusing circuits in accordance with the present invention.
  • FIG. 7 shows a more detailed operational block diagram of an array of the beam forming and focusing circuits in accordance with the present invention.
  • FIG. 8 shows an operational block diagram of an alternative embodiment of the present invention in which each of the beam forming and focusing circuits incorporates a latching circuit.
  • FIG. 9 shows a schematic block diagram of an exemplary embodiment of the latching circuit used in accordance with the present invention.
  • FIG. 10 shows an operational block diagram of an alternative embodiment of the present invention in which the selected outputs of each beam forming and focusing circuit are applied to respective multiplier circuits.
  • FIG. 11 shows an operational block diagram of an alternative embodiment of the present invention in which a plurality of beam forming and focusing circuits of the present invention are arranged for operation in a transmission mode.
  • FIG. 12 is a schematic functional block diagram of one preferred embodiment of adaptive beam forming circuitry in accordance with the present invention.
  • FIG. 13 shows a schematic block diagram of an alternative embodiment of an array of beam forming and focusing circuits in accordance with the present invention using a programmable sample selection circuit and a programmable delay unit.
  • FIG. 14A shows a schematic diagram of an exemplary embodiment of a memory controlled programmable sample selection circuit used in accordance with the present invention.
  • FIG. 14B contains timing diagrams for the sample selection circuit of FIG. 14A.
  • FIG. 15 is a schematic detailed block diagram of an alternative preferred embodiment of memory and control circuitry in accordance with the invention.
  • FIG. 16 shows a schematic block diagram of an embodiment of the beam forming circuits of FIG. 13, in which CCD programmable delay lines are employed.
  • FIG. 17 is a schematic detailed block diagram of another alternative preferred embodiment of memory and control circuitry in accordance with the invention.
  • FIG. 18 is a schematic detailed block diagram of another alternative preferred embodiment of memory and control circuitry in accordance with the invention.
  • FIG. 19 shows a block diagram of an alternative embodiment of the present invention in which the selected outputs of each of the beam forming and focusing circuits are applied to respective multiplier weighting circuits.
  • FIG. 20 shows a block diagram of an alternative embodiment of the present invention in which the multiplier weighting circuit is placed to the input of the delay unit.
  • FIG. 21 shows a block diagram of an alternative implementation of the present invention, in which a finite- impulse response (FIR) filter for time-domain interpolation is placed following the delay units.
  • FIG. 22 shows a block diagram of a FIR filter implementation in which fixed-weight multipliers are used for input sample interpolation.
  • FIR finite- impulse response
  • FIG. 23 shows a block diagram of an alternative FIR filter implementation in which programmable multipliers are used for input sample interpolation.
  • FIG. 24 is a schematic diagram showing the scan conversion process of the invention.
  • FIG. 25 is a schematic functional block diagram of a pulsed Doppler processing unit in accordance with the present invention.
  • FIG. 26 is a schematic block diagram of a color flow map chip implementation using dual pulsed Doppler processors in accordance with the present invention.
  • FIG. 27 is a schematic functional block diagram of an alternative preferred embodiment of the ultrasound imaging system of the invention.
  • FIG. 28 is a plot comparing truncated non-varying spatial windows and dynamic spatial windows used during sub-aperture scanning in accordance with the present invention.
  • FIGs. 29A and 29B are schematic pictorial views of two user-selectable display presentation formats used in the ultrasound imaging system of the invention.
  • FIG. 30A is a schematic illustration of the relationship between a linear ultrasound transducer array and a rectangular scan region in accordance with the present invention.
  • FIG. 30B is a schematic illustration of the relationship between a curved ultrasound transducer array and a curved scan region in accordance with the present invention.
  • FIG. 30C is a schematic illustration of the relationship between a linear ultrasound transducer array and a trapezoidal scan region in accordance with the present invention.
  • FIG. 30D is a schematic illustration of a phased array scan region.
  • FIG. 31 is a schematic functional block diagram of a circuit board in accordance with the present invention.
  • FIG. 32 is a schematic partial cross-sectional diagram of one embodiment of a linear scan head in accordance with the present invention.
  • FIG. 33 is a schematic side cross-sectional view of the scan head of FIG. 31.
  • FIG. 34 is a schematic partial cross-sectional view of a scan head using a curve transducer array in accordance with the present invention.
  • FIG. 35 is a schematic cross-sectional diagram of an internal ultrasonic probe in accordance with the present invention.
  • FIG. 36 is a top-level flow diagram illustrating the logical flow of the software used to control the operation of the present invention.
  • FIG. 37 is a perspective view of a two dimensional transducer array in accordance with the invention.
  • FIG. 38 is a schematic illustration of an electronic ultrasound stethoscope in accordance with the invention.
  • FIGS. 39A and 39B illustrate an ultrasound transducer patch system in accordance with the invention.
  • FIGS. 40A and 40B illustrate an ultrasound probe or catheter in accordance with the invention.
  • FIG. 3 is a schematic pictorial view of the ultrasound imaging system 10 of the present invention.
  • the system includes a hand-held scan head 12 coupled to a portable data processing and display unit 14 which can be a lap-top computer.
  • the data processing and display unit 14 can include a personal computer or other computer interfaced to a cathode ray tube (CRT) for providing display of ultrasound images.
  • the data processor display unit 14 can also be a small, lightweight, single-piece unit small enough to be hand-held or worn or carried by the user.
  • the hand-held display is less than 1000 cm 3 in volume and preferably less than 500cm 3 .
  • FIG. 3 shows an external scan head, the scan head of the invention can also be an internal scan head adapted to be inserted through a lumen into the body for internal imaging.
  • the head can be a transesophogeal probe used for cardiac imaging.
  • the scan head 12 is connected to the data processor 14 by a cable 16.
  • the system 10 includes an interface unit 13 (shown in phantom) coupled between the scan head 12 and the data processing and display unit 14.
  • the interface unit 13 preferably contains controller and processing circuitry including a digital signal processor (DSP) .
  • DSP digital signal processor
  • the interface unit 13 performs required signal processing tasks and provides signal outputs to the data processing unit 14 and/or scan head 12.
  • the hand-held housing 12 includes a transducer section 15A and a handle section 15B.
  • the transducer section 15A is maintained at a temperature below 41°C so that the portion of the housing that is in contact with the skin of the patient does not exceed this temperature.
  • the handle section 15B does not exceed a second higher temperature preferably 50°C.
  • the hand-held scan-head occupies a volume of less than 1000cm 3 and preferably less than 500cm 3 , and is less than twenty centimeters in length along it's major axis.
  • FIG. 4 is a schematic functional block diagram of one embodiment of the ultrasound imaging system 10 of the invention.
  • the scan head 12 includes an ultrasonic transducer array 18 which transmits ultrasonic signals into a region of interest or image target 11, such as a region of human tissue, and receives reflected ultrasonic signals returning from the image target.
  • the scan head 12 also includes transducer driver circuitry 20 and pulse synchronization circuitry 22.
  • the pulse synchronizer 22 forwards a series of precisely timed and delayed pulses to high voltage driver circuits in the drivers 20. As each pulse is received by the drivers 20, the high-voltage driver circuits are activated to forward a high-voltage drive signal to each transducer in the transducer array 18 to activate the transducer to transmit an ultrasonic signal into the image target 11.
  • Ultrasonic echoes reflected by the image target 11 are detected by the ultrasonic transducers in the array 18.
  • Each transducer converts the received ultrasonic signal into a representative electrical signal which is forwarded to preamplification circuits 24 and time-varying gain control (TGC) circuitry 25.
  • the preamp circuitry 24 sets the level of the electrical signals from the transducer array 18 at a level suitable for subsequent processing, and the TGC circuitry 25 is used to compensate for attenuation of the sound pulse as it penetrates through human tissue and also drives the beam forming circuits 26 (described below) to produce a line image.
  • the conditioned electrical signals are forwarded to the beam forming circuitry 26 which introduces appropriate differential delay into each of the received signals to dynamically focus the signals such that an accurate image can be created.
  • the signals delayed by the beam forming circuitry 26 are summed to generate a single signal which is forwarded over the cable 16 to the data processor and display unit 14.
  • the details of the beam forming circuitry 26 and the delay circuits used to introduce differential delay into received signals and the pulses generated by the pulse synchronizer 22 will be described below in detail.
  • the dynamically focused and summed signal is forwarded to an A/D converter 27 which digitizes the summed signal. Digital signal data is then forwarded from the A/D 27 over the cable 16 to buffer memories 29 and 31. It should be noted that the A/D converter 27 is not used in an alternative embodiment in which the analog summed signal is sent directly over the system cable 16. The A/D converter 27 is omitted from further illustrations for simplicity.
  • Data from buffer memory 31 is forwarded through demodulation and log compression circuitry 40A to scan conversion circuitry 28 in the data processing unit 14.
  • the scan conversion circuitry 28 converts the digitized signal data from the beam forming circuitry 26 from polar coordinates (r,0) to rectangular coordinates (x,y) . After the conversion, the rectangular coordinate data is forwarded to post signal processing stage 30 where it is formatted for display on the display 32 and/or for compression in the video compression circuitry 34.
  • the video compression circuitry 34 will be described below in detail.
  • Digital signal data is forwarded from buffer memory 29 to a pulsed or continuous Doppler processor 36 in the data processor unit 14.
  • the pulsed or continuous Doppler processor 36 generates data used to image moving target tissue 11 such as flowing blood.
  • a color flow map is generated.
  • the pulsed Doppler processor 36 forwards its processed data to the scan conversion circuitry 28 where the polar coordinates of the data are translated to rectangular coordinates suitable for display or video compression.
  • a control circuit preferably in the form of a microprocessor 38 controls the operation of the ultrasound imaging system 10.
  • the control circuit 38 controls the differential delays introduced in both the pulsed synchronizer 22 and the beam forming circuitry 26 via a memory 42 and a control line 33.
  • the differential delays are introduced by programmable tapped CCD delay lines to be described below in detail.
  • the delay lines are tapped as dictated by data stored in the memory 42.
  • the microprocessor 38 controls downloading the coarse and fine delay line tap data from memory 42 to on-chip memories in both the pulsed synchronizer 22 and the beam forming circuitry 26.
  • the delays are controlled by delay processing circuitry which includes programmable input sampling circuits coupled to programmable delay units as described in detail below.
  • the microprocessor 38 also controls a memory 40 which stores data used by the pulsed Doppler processor 36 and the scan conversion circuitry 28. It will be understood that memories 40 and 42 can be a single memory or can be multiple memory circuits.
  • the microprocessor 38 also interfaces with the post signal processing circuitry 30 and the video compression circuitry 34 to control their individual functions.
  • the video compression circuitry 34 as described below in detail compresses data to permit transmission of the image data to remote stations for display and analysis via a transmission channel.
  • the transmission channel can be a modem or wireless cellular communication channel or other known communication means.
  • the portable ultrasound imaging system 10 of the invention can preferably be powered by a battery 4 .
  • the raw battery voltage out of the battery 44 drives a regulated power supply 46 which provides regulated power to all of the subsystems in the imaging system 10 including those subsystems located in the scan head 12.
  • power to the scan head is provided from the data processing and display unit 14 over the cable 16.
  • FIG. 5 is a detailed schematic functional block diagram of one embodiment of the scan head 12 used in the ultrasound imaging system 10 of the invention.
  • the scan head 12 includes an array of ultrasonic transducers labeled in FIG. 3 as 18- (1) , 18-
  • Each transducer 18(1)-18(N) is coupled to a respective processing channel 17(1)-17(N) .
  • Each processing channel 17(1)-17(N) includes a respective pulse synchronizer 22(1)-22(N) which provides timed activation pulses to a respective high voltage driver circuit 20(1)-20(N) which in turn provides a driving signal to a respective transducer 18(l)-18(N) in the transmit mode.
  • Each processing channel 17(1)-17(N) also includes respective filtered preamplification circuits 24 (1) -24 (N) which include voltage clamping circuits which, in the receive mode, amplify and clamp signals from the transducers 18(1)-18(N) at an appropriate voltage level.
  • the time varying gain control circuitry (TGC) 25 (1) -25 (N) controls the level of the signals, and the beam forming circuitry 26(1)-26(N) performs dynamic focusing of the signals by introducing differential delays into each of the signals as described below in detail .
  • the outputs from beam forming circuits 26(1)-26(N) are summed at a summing node 19 to generate the final focused signal which is transmitted over the cable 16 to the data processor and display unit 14 for subsequent processing.
  • one embodiment of the beam forming and focusing circuit 26 can be integrated on a single microchip and utilizes cascaded charge-coupled device (CCD) tapped delay lines to provide individual coarse and fine delays resulting in a wide range of delays with fine time resolution.
  • CCD charge-coupled device
  • This embodiment of the beam forming system of the invention referred to herein as charge domain processing (CDP) circuitry, includes a plurality of processing circuits which, in a receiving mode, differentially delay signals representative of image waveforms received as reflected ultrasonic energy from the target object in order to generate a focused image.
  • CDP charge domain processing
  • the processing circuits differentially delay signals, which are to be transmitted as ultrasonic energy to a target object by the array 18 of transducers 18 (1) -18 (N) , in order to generate a focused directional beam.
  • Each of the processing circuits includes a first delay line having a plurality of delay units operable in the receiving mode for receiving an image waveform and converting same into sampled data such as charge packets.
  • the first delay line receives the imaging signals and converts them into sampled data such as charge packets.
  • a selection control circuit is operable for reading the sampled data from a selected first delay unit of the first delay line so as to correspond to a selected first time delay to accommodate fine delay resolution of the image waveform or imaging signals.
  • a second delay line having a plurality of delay units is operable for sensing the sampled data from the selected first delay unit.
  • the control circuit is further operable for reading the sampled data from a selected second delay unit of said second delay line so as to correspond to a selected second delay time to accommodate coarse delay resolution of the image waveform or imaging signals.
  • a summation circuit is provided for summing the sampled data from each of the selected second delay units in each of the processing circuits in order to produce a focused image.
  • an output circuit is provided for converting the sampled data from each of the selected second delay units in each of the processing circuits into signals representative of the focused directional beam.
  • each beam forming circuit 26 in accordance with the present invention provides a different time delay on each processing channel, and further varies that delay with time.
  • the signals which are added in phase to produce a focused signal are then forwarded to the data processor and display unit 14.
  • the overall control of delay can involve very fine time resolution as well as a large range of delays.
  • this set of delays is achieved by a combination of a coarse delay in each channel to approximately compensate for direction, and a fine delay for each channel which combines the functions of focusing and refining the original coarse correction.
  • the beam forming circuitry 26 shown in operational block diagram form in FIG.
  • each of the beam forming circuits 26 is respectively arranged in a predetermined one of the N- parallel processing channels 17(1)-17(N) , one for each of the array of transducer elements 18(1)-18(N) .
  • Each beam forming circuit 26 includes two cascading tapped delay lines 56(1)-56(N), 58 (1) -58 (N) .
  • Each circuit 26 receives as an input a signal from a TGC circuit 25 (see FIG. 3) .
  • the first delay line 56 in each channel provides a fine time delay for its received signal, while the cascaded second delay line 58 provides a coarse time delay.
  • Each fine delay line has an associated programmable tap-select circuit 57(1)-57(N), and each coarse delay line has a programmable tap-select circuit 59(1)-59(N), both of which will be described in more detail hereinafter.
  • the tap- select circuits are operable for effecting a variable delay time as a function of tap location.
  • both the fine 56 and coarse 58 tapped delay lines are charge-coupled device (CCD) tapped delay lines.
  • CCD charge-coupled device
  • Exemplary programmable CCD tapped delay lines are described in, for example, Beynon et al. , Charge-coupled Devices and Their Applications, McGraw-Hill (1980) , incorporated herein by reference.
  • the input signals to each of the processing channels are converted to a sequence of charge packets for subsequent propagation through the fine and coarse delay lines.
  • a delayed sample is either destructively or nondestructively sensed from the selected tap of the fine delay line 56.
  • the delayed sample is in turn input to the front end of the corresponding coarse delay line 58.
  • the selected delay samples thereafter propagate through the coarse delay line, and are again destructively or nondestructively sensed at a properly selected tap location corresponding to a predetermined time delay designated in accordance with the operation of the ultrasound imaging system 10.
  • the sensed sampled data from the coarse delay line of each processing channel is simultaneously summed by a summation circuit 19 to form the output beam.
  • the programmable tap-select circuits 57(1)-57(N) for the fine delay lines each include respective fine tap select circuits 60(1)-60(N) and fine tap select memory units 62(1)-62(N) .
  • the programmable tap-select circuits 59(1)-59(N) for the coarse delay lines each include respective coarse tap select circuits 64 (1) -64 (N) and coarse tap select memory units 66(1)-66(N) .
  • the fine and coarse delay lines have differing clock rates.
  • the fine delay line is clocked at a higher rate than the coarse delay line and is therefore capable of providing a much finer delay time than that of the coarse delay line.
  • each circuit 26 has a 32-stage fine tapped delay line clocked at 40MHz and a 32-stage coarse-tapped delay line clocked at 2MHz.
  • Such a configured circuit can provide up to a 16 ⁇ s delay with a programmable 25ns delay resolution.
  • a local memory of 5-bit wide by 64-stage is adequate for providing the dynamic focusing function for a depth up to 15cm.
  • a single delay structure were used, it would require a local memory of 640-bit wide by 1280-stage long.
  • the fine delay line taps are changed continuously by the microprocessor 38 via the memory 42 (see FIG. 4) during each echo receiving time to provide dynamic focusing.
  • the fine tap select circuit 60 in the form of a digital decoder, and the local fine tap select memory 62 are used to select the desired tap position of the fine delay line 56.
  • the microprocessor instructs the memory 42 to download a data word to memory 62 to provide a digital address representative of the selected tap position to the select circuit 60 for decoding.
  • the select circuit 60 effects the sampling of data from the selected tap.
  • a 5-bit decoder is used to provide a 32-tap selection.
  • the tap position of the coarse delay line 58 is set once before each echo return and is not changed during each azimuth view direction.
  • the coarse tap select circuit 64 in the form of a digital decoder, is used in conjunction with the local coarse tap select memory 66 to select the desired tap position of the coarse delay line.
  • FIG. 8 shows an operational block diagram of an alternative embodiment of the beam forming circuitry 26 of the present invention in which each circuit 26 includes a respective latching circuit 70(1)-70(N) that generates a tap setting signal to each of the fine tap select circuits 60(1)-60(N) .
  • the tap setting signal is provided to the fine tap select circuits, the tap selection will be fixed at the last tap of the fine tap delay lines (i.e. focusing point) , thus the dynamic focusing function is not operable.
  • This operation is controlled by the imaging system in situations where, for example, the imaging point is at a distance from the transducer elements which does not require a precise fine delay time. In this manner, the size of the fine tap select memory 62 is reduced.
  • FIG. 9 An exemplary embodiment of the latching circuit 70 in accordance with the present invention is shown in FIG. 9.
  • the latch when the latch is set high by the microprocessor 38, digital data from the memory 62 will pass through the CMOS passing transistors, and the defined transistor inverter provides an input to the appropriate tap select circuit (decoder) 60 so as to implement the dynamic focusing function.
  • the latch when the latch is set low, the passing transistors are disabled, and thus the inverter output will be latched to the last data address in the memory, i.e., the last tap select position.
  • each processing circuit includes two cascaded programmable tapped delay lines (each 16-stages long) , two 4-bit CMOS decoders and a 4x64-bit local memory for storing the tap locations.
  • the prototype is configured with 10 processing channels, each of which includes the processing circuit of the present invention fabricated on a single silicon microchip.
  • Each processing circuit can provide up to lO ⁇ s of programmable delay with a 25ns delay resolution.
  • the beam forming chip operates such that at each azimuth viewing angle, echo return signals from an image point at a given range resolution received by a transducer element are sampled by the corresponding processing channel.
  • Each processing circuit provides ideally compensated delays to each received return signal.
  • the chip area associated with each processing channel is only 500x2000 ⁇ m 2 . It follows that the dynamic beam forming electronics for a 64-element receiver array can be integrated in a single microchip with chip area as small as 64mm 2 , which corresponds to at least three to four order of magnitude size reduction compared to conventional devices.
  • the fine/coarse tapping architecture of the present invention accommodates a 12 ⁇ s delay with a 25ns resolution with the two cascaded CCD tapped delay lines.
  • the architecture includes a first 16-stage long delay line clocked at 40MHz and a second 32-stage long delay line clocked at 2 MHz.
  • the shorter delay lines and the simplicity of the tapping circuit associated with these shorter delay lines allows all of the image-generating electronics to be integrated on a single chip.
  • a single chip performs the electronic focus function for a 128- element array with more than two orders of magnitude reduction in chip area, power consumption and weight when compared with conventional implementations.
  • An operational block diagram of another alternative embodiment of the beam forming circuitry 26 of the present invention is shown in FIG.
  • the configuration of the multipliers 80 will accommodate the use of apodization techniques, such as incorporating a conventionally known Hamming weighting or code at the receiving array to reduce the sidelobe level and generate better quality imagery.
  • apodization techniques such as incorporating a conventionally known Hamming weighting or code at the receiving array to reduce the sidelobe level and generate better quality imagery.
  • latch circuits 70(1)-70(N) may be included in association with each of the beam forming circuits 26(1)-26(N) in order to control the latching of the tap select position for the fine delay lines 56(1)- 56 (N) .
  • Conventional apodization and Hamming weighting techniques are described in, for example, Gordon S. Kino, Acoustic Waves: Devices, Imaging, and Analog Signal Processing, Prentice-Hall, Inc. (1987) , which is incorporated herein by reference.
  • FIG. 11 shows an operational block diagram of the cascaded dual tapped CCD delay lines used in pulse synchronizers 22(1)-22(N) to introduce delay into individual transmitted signals in the transmit mode of the ultrasound system 10 of the present invention.
  • Each pulse synchronizer circuit 22(1)-22(N) includes two cascading tapped delay lines 56 (1) ' -56 (N) ' and 58 (1) ' -58 (N) ' .
  • the first delay line 56' in each processing channel provides a fine time delay for the signals to be transmitted, while the cascaded second delay line 58' provides a coarse time delay.
  • Each fine delay line has an associated programmable fine tap select circuit 60 (1) ' -60 (N) ' , which receive tap select addresses from respective fine tap select memory units 62 (1) ' -62 (N) ' .
  • Each coarse delay line has an associated programmable coarse tap select circuit 64(1)'- 64 (N) ' , which receive tap select addresses from respective fine tap select memory units 66 (1) ' -66 (N) ' .
  • the tap-select circuits are operable for effecting a variable delay time as a function of tap location.
  • the input signals to each processing channel are converted into a sequence of sampled data for initial propagation through the respective fine tapped delay line 56.
  • the input signals to each of the processing channels are converted to a sequence of charge packets for subsequent propagation through the fine and coarse delay lines.
  • a delayed sample is either destructively or nondestructively sensed from the selected tap of the fine delay line 56.
  • the delayed sample is in turn input to the front end of the corresponding coarse delay line 58.
  • the selected delay samples thereafter propagate through the coarse delay line, and are again sensed at a properly selected tap location corresponding to a predetermined time delay designated in accordance with the operation of the microprocessor 38 of the ultrasound imaging system 10.
  • the sensed sampled data from each of the coarse delay lines 58(1)-58(N) are then converted and transmitted as ultrasonic pulse signals by the corresponding transducer elements 18 (1) -18 (N) .
  • the fine and coarse delay lines of each pulse synchronizer circuit have differing clock rates.
  • the fine delay line can be clocked at either a higher or lower rate than that of the coarse delay line in order to accomplish the desired beam forming and focusing.
  • an adaptive beam forming imaging (ABI) technique is used in both the beam forming circuits 26 and the pulse synchronizer circuits 22 to introduce the appropriate delays to produce a focused image.
  • the adaptive beam forming technique improves image quality and spatial resolution by suppressing artifacts due to scattering sources and clutter in the sidelobes of the transducer array response.
  • This adaptive beam forming circuitry can also be implemented on a single chip.
  • ABI is a model-based approach to image reconstruction derived from superresolution techniques.
  • ABI offers improvements in resolution and reduction in sidelobes, clutter, and speckle.
  • Superresolution algorithms modified for imaging include the two-dimensional maximum likelihood method (MLM) and two-dimensional multiple-signal classification (MUSIC) .
  • MLM maximum likelihood method
  • MUSIC two-dimensional multiple-signal classification
  • ABI incorporates models for the desired backscatter (amplitude and phase) , providing better detection performance than conventional imaging methods.
  • FIG. 12 is a schematic functional block diagram depicting one embodiment of adaptive beam forming circuits 426 located in the scan head 412 in accordance with the present invention.
  • individual multiplier weights of the finite impulse response (FIR) filter are controlled by a feedback loop, in such a way as to reduce clutter and interference or finite impulse response (FIR) filters.
  • the adaptive circuits are used to remove clutter and interference such as that caused by ultrasonic signal in the sidelobes of the array pattern to produce an image with much higher accuracy and resolution.
  • Each processing channel 428 (1) -428 (N) of the beam forming circuits 426 receives a signal from a respective time-varying gain control (TGC) circuit 25 at a respective tapped delay line 430.
  • TGC time-varying gain control
  • the beam forming circuits 426 includes N processing channels 428, one for each transducer in the array 18. Signals tapped off of each tapped delay line 430 are received by a set of weighted multiplying D/A converters 432. Each processing channel k includes M weighted multipliers 432, labelled 432 J -432 kM . The weights of the multipliers 432 are set to generate an output signal from each processing channel which is summed at a summing node 419. The summed signal is forwarded over the system cable 416 to the system control circuit such as the microprocessor 438 in the data processing and display unit 414. The microprocessor 438 analyzes the signal for known characteristics of such effects as clutter, sidelobes and interference.
  • the microprocessor 438 In response to detecting such effects, the microprocessor 438 generates control signals used to drive the multiplier weights 432 to adjust the signals to eliminate these effects from the output signal and forwards the control signals to the multipliers via the system cable 416 on lines 440.
  • the adaptive beam forming circuitry comprises a feedback circuit which alters received signals from a tapped delay line of each channel prior to summation of the signals. The summed signal is sensed and correction signals based on the sensing are forwarded in the feedback loop to the multipliers to correct the summed signal.
  • the ABI results in an image of much higher resolution and overall quality than is obtainable in prior systems.
  • the ABI technique results in at least two to three times better resolution than that provided by conventional imaging techniques.
  • a resolution of about 1 mm can be obtained in conventional ultrasound.
  • a lateral resolution of approximately 300 ⁇ m is obtained in conventional ultrasound.
  • FIG. 13 is a detailed block diagram of an alternative embodiment of the beam forming circuits of the invention to those of FIGs. 6 and 12.
  • the beam forming circuits 226 can be used for dynamic beam forming and scanning in the receive mode.
  • the beam forming circuits 226 include N parallel processing channels 217 (1) -217 (N) , one for each element 18 in the ultrasound transducer array (see FIG. 5) .
  • Each channel 217 (1) -217 (N) includes a respective delay unit 202 (1) -202 (N) , a respective programmable input sampling circuit 204 (1) -204 (N) , respective local memory and control circuitry 206 (1) -206 (N) for storing and generating proper timing for the sampling circuit 204 (1) -204 (N) and for storing and selecting the proper delay in the delay circuit 202 (1) -202 (N) for the sampled image data from the sampling circuit 204 (1) -204 (N) .
  • the beam forming circuits 226 also include a central memory 203 which stores all of the delay values needed for all of the processing channels 217 (1) -217 (N) .
  • the central memory 203 downloads delay data values to the memory and control circuits 206 (1) -206 (N) for all of the processing channels 217 (1) -217 (N) .
  • the delay values stored in each local memory 206 (1) -206 (N) are used to control the sample selection performed by each respective sample selection circuit 204 (1) -204 (N) and the sample delay effected by each respective programmable delay unit 202 (1) -202 (N) .
  • each imaging scan line requires a specific set of delays for all of the processing channels, such as in the case of phased array beam forming.
  • new delay value sets are downloaded to the local memories 206 (1) -206 (N) before each scan line is executed. Due to the compactness of each delay unit 202 (1) -202 (N) and the simplification of its corresponding sample and control circuits 204 (1) -204 (N) and 206(1)-
  • this approach allows the beam forming electronics of a 128-element receiver array to all be integrated on a single chip.
  • Returned echoes received by a transducer 18(1)-18(N) are first amplified in a preamplification circuit 24(1)-24(N) and a TGC circuit 25(1)-25(N) (see FIG. 5) and then applied to the input of a corresponding respective sampling circuit 204 (1) -204 (N) .
  • the sampling rate, f s , of this circuit 204 (1) -204 (N) is chosen to be higher than the clock rate f c , of the corresponding delay unit 202 (1) -202 (N) , i.e., in one clock period of the delay unit 202 (1) -202 (N) , there are f s /f c possible samples.
  • one of these f s /f c possible samples is selected and then loaded into the delay unit 202(1)- 202 (N) .
  • uniformly or nonuniformly sampled data can be selected from the returned echoes and loaded into the delay unit 202 (1) -202 (N) .
  • the selection circuit 204 (1) -204 (N) is used to select one of the eight possible samples and to load it into the respective delay unit 202 (1) -202 (N) .
  • a control circuit is incorporated within each delay unit 202 (1) -202 (N) such that a programmable delay with a maximum delay of M/f c can be provided to each sampled data loaded into the delay unit, where M is the number of delay stages in a delay line of the delay unit 202 (1) -202 (N) , as described below in connection with FIG. 15.
  • FIG. 14A is a schematic block diagram of an exemplary embodiment of a memory controlled programmable sample selection circuit 204 of the present invention
  • FIG. 14B illustrates timing diagrams for the sampling process.
  • the sampling rate f s is assumed to be eight times faster than the clock rate f c of the delay time 202, i.e., eight sample data items can be taken from the input waveform during a given clock period l/f c of the delay line 202.
  • eight evenly spaced timing windows are defined by the sampling frequency f s within the period of the delay clock l/f c .
  • the memory and control circuitry 206 includes a three- bit BCD counter 216 which is clocked to count at the sampling frequency f s .
  • the three outputs 218 from the counter 216 provide inputs to a 3-to-8 decoder 220, which provides a high-level output on one of its eight output lines 222 when enabled to indicate the decoded decimal value of the BCD inputs.
  • An 8-to-l MUX selects one of the decoder outputs to provide the sample select signal on line 1126 to the sampling NMOS transistor 214.
  • the line selected by the MUX 224 is controlled at its select lines by the three data outputs 228 of a memory 210. As shown in FIG. 14B, if the memory output word is (0,0,0), a single pulse is provided in the sample select signal on line 226 at the first sampling window. If the memory word is (0,0,1), the single pulse is provided at the second sampling window, and so forth.
  • the gate of the NMOS transistor 214 is connected to the sample select signal.
  • the drain is connected to the input waveform (returned echoes) , and the source is connected to the delay line 202 to provide the sampled signal data.
  • the eight 3-bit selecting memory words are stored in addressable locations in the memory 210.
  • a location of the memory 210 is addressed via address lines 232 to output the selected 3-bit selection word on lines 228 according to the desired sampling window.
  • the control circuitry 230 sets the address lines to the appropriate address according to the required sampling window location.
  • the control circuitry 230 also sends out an enable signal on line 234 for every period of the delay clock to enable the outputs of the decoder 220, MUX 224 and memory 210 such that the pulse of the sample selection signal on line 1126 is located at the appropriate window. Since the control circuits 230 can select a memory address for every cycle of the delay, the spacing between samples can be precisely controlled to be uniform or nonuniform or have any desired pattern.
  • control circuits 230 include their own internal storage circuits which holds the sequence of addresses output by the control circuits 230 to generate the sample pulse during the appropriate timing windows.
  • the address sequence is downloaded to the storage circuit from the central memory 230 of the beam forming circuits 226 before each scan line is executed.
  • the storage circuit can be a memory such as a RAM, or it can be a shift register. In either case, the storage circuit is clocked at the delay line clock rate f c to output the address required to sample data during the correct timing window.
  • FIG. 15 is a detailed schematic block diagram of an alternative preferred form of the memory and control circuitry 206A to that shown in FIG. 14A.
  • This alternative form of the memory and control circuit 206A includes a storage circuit such as shift register 205. In this embodiment, the shift register 205 shifts out a 3-bit pre- stored word on every cycle of the clock of the delay unit
  • the number of words stored in the shift register 205 for each scan line is equal to the number of focus points along each scan line. In one preferred embodiment, there are 512 focus points and, hence, 512 3-bit words. That is, the shift register 205 is a 512-stage 3-bit register.
  • the memory and control circuitry 206A also includes a 3-bit BCD counter 207 which is clocked at the selection sampling rate f s .
  • the counter 207 outputs 3-bit BCD words in sequence as it is clocked by the clock signal at the f s rate.
  • the sampling rate f s is eight times the delay clock rate f c ; therefore, for each word on the output lines 209 of the shift register 205, the eight 3-bit BCD words 0 10 through 7 10 are output on the output lines 211.
  • the outputs 209 from the shift register 205 and the outputs 211 from the counter 207 are forwarded to a comparison circuit 213 which compares the two 3-bit words to determine if they are identical. When they are identical, a match is indicated by the comparison circuit 213 outputting a positive pulse on output line 1115.
  • the pulse is applied to the sampling NMOS transistor 214 to sample the returned echo signals from the appropriate acoustic transducer 18.
  • the discrete-time sampled analog data is forwarded to the appropriate corresponding delay unit 202.
  • the positive pulse on line 1115 occurs when one of the 3-bit BCD words from the counter 207 matches the 3-bit word from the shift register 205. This will occur during one of the eight possible timing windows into which the delay line clock rate f c is divided. Hence, the 3-bit word stored in the shift register 205 determines the window during which the returning echo data will be sampled. Therefore, to control the delays, a predetermined pattern of 3-bit words is stored in the shift register 205 before execution of the particular scan line by downloading from the central memory 203.
  • FIG. 16 is a detailed schematic block diagram of a preferred embodiment of the processing channels
  • each delay unit 202 (1) -202 (N) includes an M- stage programmable tapped CCD delay line 221 (1) -221 (N) . At each stage of delay, an output is provided; therefore, for each delay line 221 (1) -221 (N) , there are M-parallel outputs.
  • each delay line 221 (1) -221 (N) is controlled by a digital parallel decoder 237 (1) -237 (N) with M outputs.
  • One of the M selectable outputs is selected according to the decoded decimal value on the BCD input lines 239 from the memory and control circuit 206.
  • a 6-to-64 decoder 237 (1) -237 (N) can be used to provide an output selection for a 64-stage CCD delay line 221 (1) -221 (N) .
  • a discrete-time analog sample from the sample select circuit 204 (1) -204 (N) is delayed by the delay line 221 (1) -221 (N) and, hence, provided at the output of the stage selected by the decoder 237 (1) -237 (N) .
  • the delay time for each sampled data loaded into the delay line can be continuously changed to provide dynamic focusing.
  • the sampled and delayed data from all channels 217 (1) -217 (N) is summed in summing circuit 219.
  • the input lines 239 to the decoder 237 are shown coming from the memory and control circuit 206.
  • FIG. 17 is a detailed schematic block diagram of an embodiment of the memory and control circuit 206B which generates the decoder input lines 239.
  • FIG. 17 The circuit of FIG. 17 is identical to that of FIG. 15 except for the generation of the decoder input line signals 239.
  • a preferred 512-stage 9-bit parallel shift register 205A is used in a fashion identical to that of the register 205 in FIG. 15 to generate the 3-bit word on lines 209 used in the comparison circuit 213 to generate the sampling pulse in the desired timing window.
  • a 6-bit word is also output simultaneously on lines 239 and forwarded to the delay unit 202. As described above, this 6-bit word is used as an input to the decoder 237 described above to select an appropriate stage of the tapped CCD delay line 221 to introduce the appropriate delay into the sampled signal.
  • the sampling and delay control words are downloaded to the shift register 205A from the central memory 203 prior to the execution of each scan line.
  • 512 9-bit digital words are downloaded before the execution of each scan line.
  • the register 205A is clocked at the delay unit clock rate f c , 9-bit digital words are output in succession on lines 239 and 209, one 9-bit word at a time.
  • the 3-bit word on lines 209 controls the timing window during which the returned echoes are sampled, and the 6-bit word on lines 239 controls the amount of delay introduced into the sample by the programmable delay unit 202.
  • FIG. 18 is a detailed block diagram of a variation on the circuit shown in FIG. 17.
  • the alternative memory and control circuit 206C of FIG. 18 reduces the amount of memory space needed in the circuit 206C.
  • 2-bit words can be used.
  • the difference between adjacent delays and/or the second difference between the first differences is stored.
  • the second difference is stored, only two bits are required to store the required delay information.
  • only 2-bit words need be downloaded from the central memory 203 and stored by the shift register 205B.
  • the 512-stage shift register is only two bits wide.
  • the register 205B is clocked at the rate of the delay clock f c .
  • the 2-bit word is output by the register 205B to an integration circuit 225 which can include a dual-stage adder circuit used to recover the actual delays from the stored first and second difference.
  • the integration step generates a 6-bit word on lines 239A, which is used as the control inputs to the decoder 237 in the programmable delay unit 202.
  • the three additional bits generated on lines 209A are used as described above in the comparison circuit 213 to generate a sampling pulse at the appropriate timing window.
  • FIG. 19 is a schematic block diagram of a modification of the circuitry of FIG. 13 in which a multiplier 250 (1) -250 (N) is included at the output of each programmable delay unit 202 (1) -202 (N) .
  • This implementation allows the use of apodization, such as by incorporating a Hamming weighting at the receiver array to reduce the sidelobe level and generate better quality imagery.
  • the weighting function of the multiplicand of each multiplier is provided by an on-chip buffer memory contained in memory and control circuits 206 (1) -206 (N) .
  • the outputs of all the multipliers 250 (1) -250 (N) are summed together at summing circuit 219 to form a beam output.
  • the apodization can be performed either at the input or at the output of the delay unit 202 (1) -202 (N) .
  • FIG. 20 an input weighted delay structure is shown.
  • the minimum delay resolution is determined by the sampling rate f s .
  • FIG. 21 Another implementation which provides an effective delay time smaller than t c is shown in FIG. 21.
  • a finite-impulse-response (FIR) filter 252 (1) -252 (N) is added to the output of the programmable delay circuit 202 (1) -202 (N) .
  • the FIR filter 252 (1) -252 (N) can be used to generate time-domain interpolated image samples and effectively achieve delay resolution smaller than t c . For example, if four interpolated samples are generated by the FIR filter 252 (1) -252 (N) , the delay resolution is then t c /4.
  • FIG. 22 contains a detailed schematic block diagram of one exemplary embodiment of an interpolation FIR filter 252 in accordance with the invention with fixed-weighted multipliers 254.
  • a multiplier requires two inputs, and the output of a multiplier is the product of the two inputs.
  • the multiplicand is fixed and only one input is needed. Its output is the input multiplied by the same multiplicand.
  • An M-stage delay line 202 is used to hold and shift sampled and delayed returned echoes. At each stage of delay, there is a bank of Q fixed-weight multipliers 254, i.e., there are MxQ multipliers 254.
  • the multipliers 254 can be viewed as forming a two-dimensional array having Q rows and M columns.
  • Each multiplier 254 i;j can be identified by a coordinate i, j, where i is the row of multipliers and j is the delay stage of the delay line 202, or column of the array.
  • all the multipliers 254 on the same column share a common input, which corresponds to one of the input samples. All the multipliers 254 on the same row share a common output, which corresponds to one of the interpolated samples. It follows then, at every clock, there are Q interpolated samples.
  • a sample select circuit 256 can be placed at the parallel output ports to select one of the interpolated samples and then applies it to the summing unit 219.
  • FIG. 23 shows the schematic block diagram of another exemplary embodiment of the interpolation FIR filter 352 with programmable multipliers 354.
  • an M-stage delay line 202 is used to hold and shift sampled and delayed returned echoes.
  • all the multipliers 354 k share a common output which corresponds to the interpolated sample of the inputs. Time-domain interpolated samples can be generated based on the programmed weights.
  • the ultrasound signal is received and digitized in its natural polar (r, ⁇ ) form.
  • this representation is inconvenient, so it is converted into a rectangular (x,y) representation for further processing.
  • the rectangular representation is digitally corrected for the dynamic range and brightness of various displays and hard-copy devices.
  • the data can also be stored and retrieved for redisplay.
  • the (x,y) values must be computed from the (r,0) values since the points on the (r,0) array and the rectangular (x,y) grid are not coincident.
  • each point on the (x,y) grid is visited and its value is computed from the values of the four nearest neighbors on the (r,0) array by simple linear interpolation. This is accomplished by use of a finite state machine to generate the (x,y) traversal pattern, a bidirectional shift register to hold the (r,0) data samples in a large number of digital logic and memory units to control the process and ensure that the correct asynchronously received samples of (r,0) data arrive for interpolation at the right time for each (x,y) point.
  • This prior implementation can be both inflexible and unnecessarily complex.
  • Only a single path through the (x,y) array is possible. This means that full advantage of different ultrasound scan frequencies and, hence, imaging depths, cannot be taken. That is, different data are forced into the same format regardless of physical reality.
  • Equations 1 and 2 permit us to begin with any two successive Farey fractions and iterate through all the rest within the slice.
  • FIG. 24 A simple example of using Farey fractions of order 10 to generate all the (x,y) display points within the 46° - 54° arc on a 10 x 10 grid is shown in FIG. 24.
  • the data processing and display unit 14 is programmed to carry out the scan conversion process.
  • the ultrasound imaging system 10 of the present invention also includes a continuous or pulsed Doppler processor 36 which allows for generation of color flow maps.
  • a continuous or pulsed Doppler processor 36 which allows for generation of color flow maps.
  • the generic waveform 111 for pulsed Doppler ultrasound imaging is shown in FIG. 25.
  • the waveform consists of a burst of N pulses with as many as J depth samples collected for each pulse in the burst.
  • FIG. 25 also shows a block diagram of the pulsed Doppler signal processor 36 for this imaging technique, where the returned echoes received by each transducer are sampled and coherently summed prior to in-phase and quadrature demodulation at 113.
  • the demodulated returns are converted to a digital representation at sample-and-hold circuits 115 and A/D converters 117, and then stored in a buffer memory 119 until all the pulse returns comprising a coherent interval are received.
  • the N pulse returns collected for each depth are then read from memory, a weighting sequence, v(n) , is applied to control Doppler sidelobes, and a N-point FFT is computed at 121.
  • v(n) a weighting sequence
  • v(n) a weighting sequence
  • v(n) a weighting sequence
  • v(n) a weighting sequence
  • a N-point FFT is computed at 121.
  • This pulsed-Doppler processor (PDP) device has the capability to compute a matrix-matrix product, and therefore has a broad range of capabilities.
  • the device computes the product of two real valued matrices by summing the outer products formed by pairing columns of the first matrix with corresponding rows of the second matrix.
  • the Doppler filtering is accomplished by computing a Discrete Fourier Transform (DFT) of the weighted pulse returns for each depth of interest. If we denote the depth-Doppler samples g(k,j) , where k is the Doppler index, 0 ⁇ k ⁇ N-l, and j is the depth index, then
  • N-l 3 * i..-j ⁇ ( W r lk n f i,nj + W i lk n f r,n (6)
  • the indices of the double- indexed variables may all be viewed as matrix indices . Therefore, in matrix representation, the Doppler filtering can be expressed as matrix product operation. It can be seen that the PDP device can be used to perform each of the four matrix multiplications thereby implementing the Doppler filtering operation.
  • the PDP device 36 of the invention includes a J- tage CCD tapped delay line 110, J CCD multiplying D/A converters (MDACs) 112, J x K accumulators 114, J x K Doppler sample buffer 517, and a parallel-in-serial out (PISO) output shift register 118.
  • the MDACs share a common 8-bit digital input on which elements from the coefficient matrix are supplied.
  • the tapped delay line 110 performs the function of a sample-and-hold, converting the continuous-time analog input signal to a sampled analog signal.
  • the device 36 functions as follows: either the real or imaginary component of the returned echo is applied to the input of the tapped delay line 110.
  • the video is sampled at the appropriate rate and the successive depth samples are shifted into the tapped delay line 110.
  • each element in the first column of the transform coefficient matrix W is sequentially applied to the common input of the MDACs 112.
  • the products formed at the output of each MDAC 112 are loaded into a serial-in-parallel-out (SIPO) shift register 521.
  • SIPO serial-in-parallel-out
  • J x K products computed in this fashion represent an outer product matrix. These products are transferred from the SIPOs to CCD summing wells which will accumulate the outer product elements from subsequent PRIs. The process is repeated until all pulse returns (rows of F) have been processed.
  • each group of K accumulators 114 holds the K Doppler samples for a specific depth cell.
  • the Doppler samples are simultaneously clocked into the accumulator output PISO shift registers 519. These registers act as a buffer to hold the J x K depth-Doppler samples, so processing can immediately begin on the next coherent interval of data.
  • the accumulator shift registers 521 are clocked in parallel transferring all the depth samples for a given Doppler cell into the device output PISO shift register 118. Samples are serially read out of the PDP device in range order, which is the desired order for flow-map display. A prototype PDP-A device for 16-depth samples has been fabricated.
  • the PDP-A can be used to process returns of a burst waveform with as many as 16 range samples collected for each pulse in the burst.
  • the capability of detecting weak moving targets in the presence of a strong DC clutter has been successfully demonstrated by the prototype PDP device.
  • FIG. 26 A two-PDP implementation for color flow mapping in an ultrasound imaging system is shown in FIG. 26.
  • the top PDP component 120 computes all the terms of the form w r f r and w ⁇ as shown in equations 5 and 6, while the bottom component 122 computes terms of the form -w ⁇ and r fi.
  • the outputs of each component are then summed to alternately obtain g r and gi-
  • the imaging system of the invention also includes video compression circuitry 34 which conditions the data and transforms it into a compressed format to permit it to be transferred to a remote location.
  • the video data compression circuitry is of the type described in U.S.
  • FIG. 27 is a schematic functional block diagram of an alternative preferred embodiment of the ultrasound imaging system of the invention.
  • a multiplexer 319 is added to the scan head 312 between the ultrasonic transducer array 318 and the drivers 20 and preamplification circuitry 24.
  • signals are processed from only a portion of the transducer array 318 at any given time. For example, with a 128-element array 318, in one embodiment, only 64 elements will be processed at a time.
  • the multiplexer 319 is used to route the 64 signals to the preamplification 24 and subsequent circuits.
  • the multiplexer 319 is also used to route the driver pulses from the drivers 20 to the 64 elements of the array 318 currently being driven.
  • circuit complexity is substantially reduced since processing channels need only be provided for the number of elements which are being processed, in this example, 64. Images are formed in this embodiment by scanning across the transducer array 318 and selectively activating groups of adjacent elements to transmit and receive ultrasonic signals .
  • image quality can be degraded by the introduction of image clutter caused by energy in the image obtained through the side lobes rather than the main lobe of the array response.
  • spatial windowing filters are applied to the array processing to eliminate or reduce the energy from the side lobes.
  • One type of window varies dynamically in width according to the number of active elements.
  • Another window is a non-varying truncated window.
  • FIG. 28 is a plot showing the response of both types of windows.
  • the spatial window is designed to match the maximum number of sub-aperture array elements and is not dynamically varied with a change in the number of active elements.
  • the rationale for this implementation is that the reduction in the received (or transmitted) energy using dynamic-spatial windowing produces poorer quality images compared with images obtained using a truncated, non- varying spatial window. For both cases, the reduction in image clutter is nearly equal. Consequently, using a truncated, non-varying spatial window is advantageous because it is simpler to implement and produces better quality images. For the example shown in FIG.
  • FIGs. 29A and 29B are schematic pictorial views of display formats which can be presented on the display 32 of the invention. Rather than storing a single display format as is done in prior ultrasound imaging systems, the system of the present invention has multiple window display formats which can be selected by the user.
  • FIG. 29A shows a selectable multi-window display in which three information windows are presented simultaneously on the display. Window A shows the standard B-scan image, while window B shows an M-scan image of a Doppler two-dimensional color flow map.
  • Window C is a user information window which communicates command selections to the user and facilitates the user's manual selections.
  • FIG. 29B is a single-window optional display in which the entire display is used to present only a B-scan image.
  • the display can show both the B-mode and color doppler scans simultaneously by overlaying the two displays or by showing them side-by-side using a split screen feature.
  • FIGs. 30A-30D are schematic diagrams illustrating the relationship between the various transducer array configurations used in the present invention and their corresponding scan image regions.
  • FIG. 30A shows a linear array 18A which produces a rectangular scanning image region 307A. Such an array typically includes 128 transducers. For each scan line, a set of delays is introduced which define the focus points for the image. Because the array is linear and the region is rectangular, the delays for each scan line are typically identical. Hence, in accordance with the present invention, delay values need only be downloaded from the central memory 203 to the local memory and control circuits 206 (1) -206 (N) once for the entire image. Alternatively, the linear array 18A can be used as a phased array in which different beam steering delay values are introduced for each scan line.
  • FIG. 3OB is a schematic diagram showing the relationship between a curved transducer array 18B and the resulting sectional curved image scan region 307B.
  • the array 18B typically includes 128 adjacent transducers.
  • the delays introduced for each scan line can be identical or they can be varied to perform a phased array scanning process.
  • FIG. 30C shows the relationship between a linear transducer array 18C and a trapezoidal image region 307C.
  • the array 18C is typically formed from 192 adjacent transducers, instead of 128.
  • the linear array is used to produce the trapezoidal scan region 307C by combining linear scanning as shown in FIG. 30A with phased array scanning.
  • the 64 transducers on opposite ends of the array 18C are used in a phased array configuration to achieve the curved angular portions of the region 307C at its ends.
  • the middle 64 transducers are used in the linear scanning mode to complete the rectangular portion of the region 307C.
  • the trapezoidal region 307C is achieved using the sub-aperture scanning approach described above in which only 64 transducers are active at any one time.
  • adjacent groups of 64 transducers are activated alternately. That is, first, transducers 1-64 become active. Next, transducers 64-128 become active. In the next step, transducers 2-65 are activated, and then transducers 65-129 are activated. This pattern continues until transducers 128-192 are activated. Next, the scanning process begins over again at transducers 1-64.
  • FIG. 30D shows a short linear array of transducers 18D used to perform phased array imaging in accordance with the invention.
  • the linear array 18D is used via phased array beam steering processing to produce the angular slice region 307D shown in FIG. 30D.
  • FIG. 31 is a schematic functional block diagram of a circuit board in accordance with the invention.
  • the circuit board 1000 is preferably a multi-layer circuit board about two-by-four inches in dimension. It is preferably double sided and is populated using surface- mount technology.
  • the circuitry can functionally be divided into a transmission circuit 1010 and receiver circuit 1020.
  • the transmission circuit 1010 includes a pulse synchronizer circuit 1022 coupled to a high voltage driver/pulser circuit 1024.
  • the driver/pulser 1024 is connected through a transmit/receive (T/R) switch 1016 to a multiplexer module 1018.
  • T/R transmit/receive
  • the pulser 1024 generates a series of high voltage pulses under the control of the delay processing circuitry of the pulse synchronizer circuit 1022.
  • the pulses are transferred to the array of transducers 18 via the T/R switch 1016 and multiplexer 1018 to generate the ultrasonic signals.
  • the T/R switch 1016 operates to ensure that the high voltage pulses of the pulser 1024 do not reach the sensitive receive circuitry 1020. It provides, via a diode protection structure, overvoltage protection to the pre-amp TGC circuits in the receive circuit 1020.
  • the T/R switch 1016 includes isolation electronics used during sub- aperture scanning to isolate unused transducer elements from used elements. The circuitry also prevents crosstalk between processing channels caused by spurious signals.
  • the receiver circuit 1020 includes a pre-amp and TGC circuit module 1022, a beam former module 1026 and an optional analog-to-digital converter 1027.
  • the pre-amp and TGC 1022 is represented by two chips 1022- 1, 1022-2. Each of the pre-amp and TGC chips process half of the channels used at a given time. The number of actual chips representing the pre-amp and TGC circuit 1022 is driven by the fabrication process. Preferably, the pre-amp and TGC circuit 1022 is fabricated as a single chip.
  • the beam forming module 1026 can include the beam forming circuitry described above in connection with any of the embodiments.
  • the module 1026 preferably is formed on a single chip and contains all the circuitry necessary to perform the beam forming functions described above.
  • FIG. 32 is a cross-sectional schematic diagram of one embodiment of a linear scan head shown partially in cross section.
  • the scan head 1030 is enclosed by a plastic housing 1032.
  • a circuit board 1000A is held in place within the housing 1032 by supporting members 1034.
  • the circuit board 1000A connects to a bus connector 1036, which is connected by a flexible ribbon cable or printed flex cable 1037 to a linear array of transducers 1038.
  • a coax cable connector 1035 couples the scan head 1030 to external electronics. Alternatively, a connector for twisted pair conductors can be used.
  • FIG. 33 is another cross-sectional view of the scan head 1030 of FIG. 32.
  • the supporting members 1034 hold two double sided circuit boards 1000A, 1000B. Two or more boards can be single or double sided, and stacked side-by-side or offset to maximize use of the available space, depending upon the specific application.
  • the circuit boards are separated by a heat conducting layer 1045 which acts as a heat sink for the circuitry.
  • a heat conductor filler can also be inserted within the housing
  • the supporting members 1034 are preferably fabricated from a low friction material such as teflon to facilitate the insertion and removal of the circuit boards 1000A, 1000B.
  • Each side of the circuit boards can preferably process 64 channels of information from the transducers 1038. Therefore, as illustrated, two double sided circuit boards 1000A, 1000B can support 256 transducers.
  • FIG. 34 is a preferred embodiment of a curved transducer scan head shown partially in cross section.
  • the scan head 1040 is formed by a plastic housing 1042. Note that the handle section can have an external ribbing to provide a better gripping surface and optionally can be used to vent heat from the housing.
  • a circuit board 1000A is held in place by teflon support members 1044.
  • the circuit board 1000A is connected to a coax connector 1035 (or a twisted pair connector) and a bus connector 1046.
  • the bus connector 1046 is connected to a curved array of transducers 1048 by a printed flex cable 1047.
  • FIG. 35 is a schematic diagram of an insertable ultrasonic probe shown partially in cross section.
  • the probe 1060 is defined by a plastic housing 1062 divided into an elongate probe for insertion into a lumen or body cavity and a handle section to be gripped by an operator.
  • FIG. 36 is a block diagram of the software required to operate the ultrasonic devices described herein. Illustrated is ultrasonic scanner 1072 and a user display 1078.
  • a signal processing module 1074 provides hardware specific control such as control of digital signal processors, custom chips and system timing.
  • the user display 1078 is driven by a graphical user interface (GUI) 1076, such as those compatible with windows operating systems.
  • GUI graphical user interface
  • a virtual control panel 1075 provides an interface between the graphical user interface 1076 and the hardware interface 1074.
  • a typical display provides the user with the capability to freeze a frame of data, print a frame of data, or archive a frame of data to a disk.
  • the user can also highlight a region for color doppler imaging and audio doppler processing.
  • the user can also manually vary the received data as a function of depth. Preferably, there are eight depth zones.
  • the user can also vary the number of transmission focal zones (from 1-8 zones) , vary the image contract and the image brightness.
  • a B-mode is provided to adjust brightness or conventional image display.
  • a C-mode is provided to control color doppler flow either as an overlay or as a side-by-side image.
  • An M-mode is provided to control time- varying doppler images in an independent image mode.
  • An audio doppler mode can be set to either on or off to supplement the B-mode and C-mode displays.
  • the user can also set up the transducer array to determine image display size and shape. Selections are based on whether the transducer array is a curved-linear, linear or phased array.
  • the user can also enter and display patient information.
  • the patient data is then is then used to label the displays.
  • the computer used to provide display of the images can be programmed with a software module to display patient management and imaging data in a Windows format.
  • the user is presented with a variety of pull down menus operated with a mouse.
  • the user can also set up the imaging mode based on the particular application of the scanner.
  • the user can adjust the image depth and transmission power automatically based on whether the imaging is for cardiac, radiologic, obstetric, gynecological, or for peripheral vascular applications.
  • the user can also set the image depth and transmission manually for custom applications.
  • the transducer section 606 of the housing 600 contains three rows 608, 610 and 612 of transducers.
  • the rows 608, 610 and 612 can be of different lengths.
  • rows 608 and 612 can be shorter than the middle row 610 (e.g. the middle row can be 1.5 times the length of the shorter row) .
  • the spacing between adjacent rows can also be the same or greater than the spacing between transducers within any given row. The coarser inter-row spacing can provide effective focusing of the ultrasound signal emitted by the transducer array.
  • each row of transducers can be connected to the chip carrier or circuit board in the housing using one or more flex cables.
  • Another preferred embodiment of the invention relates to a portable ultrasound stethoscope system 700 illustrated in Fig. 38.
  • This system incorporates a transducer array, synchronizing and driver circuitry for the array and beam forming circuitry in the acoustic sensor housing 704, or chestpiece, of the stethoscope.
  • the sensor housing 704 of the stethoscope is connected to two earpieces 712 to provide audio information to the user.
  • a central tube 705 connects housing 704 to Y- connector 707.
  • the earpieces 712 are mounted on tubes 706, 708 that extend from Y-connector 707.
  • a connector housing 702 connects the stethoscope to the cable 710.
  • the connector housing 702 can be integrally formed or attached to Y-connector 707 or it can be attached to housing 704.
  • a transducer mounted in the Y-connector 707 can be used to generate audio that is delivered along tubes 706, 708 to earpieces 712.
  • the stethoscope can be used to provide standard acoustic information, electronic audio information, and/or ultrasound information.
  • the beam forming circuitry in the sensor housing 704 of the stethoscope generates a spatial representation of a region of interest that is delivered along cable 710 to a hand-held display device 714 such as a personal digital assistant .
  • the display housing 714 contains a processor for generating ultrasound images as described previously herein, preferably an M-mode display or a Doppler display.
  • the user can generate simultaneous audio and image data of the region of interest which can be stored in memory or transferred by modem along cable 720 to a separate system.
  • Power can be provided by a battery within the display housing 714, within the sensor housing 704, or within the connector housing 702.
  • the housing 714 can include a flat panel display 716 such as a liquid crystal display and a user interface 718 such as a keypad or mouse control.
  • a transducer element or array 802 is secured to a patient's skin 810 with a patch 805.
  • the patch 805 can have an adhesive border 806 to secure the patch 805 to the skin of the patient.
  • the array 802 is connected by cable 808 or wireless connection to a body worn housing 804 which can record and/or transmit the data to another receiver location.
  • the patch can have a single transducer element, or a single or multilinear array as described previously, or can have an annular array 812 as depicted in the patch 814 of Fig. 39B.
  • the patch can include beam forming and focusing circuitry as described previously in the present application.
  • System 900 includes a flexible shaft 902 having a proximal end 905 connected to housing 904 and a distal end 907. Processing circuitry as described previously is located within housing 904. Housing 904 is connected to a user interface 906 and a display 908 with cable 910. The distal end 907 of the probe shaft includes a distal section 912 in which the transducer array 918 and a chip carrier or circuit board assembly 916 are located.
  • the chip carrier 916 is connected to a cable 920 that delivers control signals to the pulse synchronizer, driver circuits, and beam forming and focussing circuits as described previously in the application and delivers the summed electrical representation of the region of interest to the processing circuitry in the housing 904.
  • the outer wall 922 of the shaft is sealed to isolate internal components from the working environment .
  • the transducer array can be radially directed, or alternatively, can be distally directed along the catheter axis.
  • a lumen 914 can be optionally included to provide for use with a fiber optic viewing system, a guidewire, or other treatment or surgical instruments.

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Abstract

L'invention concerne un système (10) d'imagerie ultrasonique portatif, comprenant une tête de balayage (12) couplée par un câble (16) à un processeur (14) de données et une unité d'affichage portatifs, alimentés par batterie. Le boîtier (12) de la tête de balayage loge une pluralité de transducteurs ultrasoniques et les circuits associés, en particulier les circuits de synchronisation des impulsions utilisés dans le mode transmission pour transmettre des impulsions ultrasoniques et les circuits formant les faisceaux utilisés dans le mode réception pour focaliser dynamiquement les signaux ultrasoniques réfléchis arrivant de la zone d'intérêt à reproduire en images.
PCT/US1996/011166 1995-06-29 1996-06-28 Systeme d'imagerie ultrasonique portatif WO1997001768A2 (fr)

Priority Applications (15)

Application Number Priority Date Filing Date Title
JP9504611A JPH11508461A (ja) 1995-06-29 1996-06-28 携帯式超音波撮像システム
AU63446/96A AU700274B2 (en) 1995-06-29 1996-06-28 Portable ultrasound imaging system
US08/981,427 US5964709A (en) 1995-06-29 1996-06-28 Portable ultrasound imaging system
EP96922638A EP0835458A2 (fr) 1995-06-29 1996-06-28 Systeme d'imagerie ultrasonique portatif
US08/773,647 US5904652A (en) 1995-06-29 1996-12-24 Ultrasound scan conversion with spatial dithering
US08/971,938 US5957846A (en) 1995-06-29 1997-11-17 Portable ultrasound imaging system
KR19970709973A KR19990028651A (fr) 1995-06-29 1997-12-29
US09/203,877 US6248073B1 (en) 1995-06-29 1998-12-02 Ultrasound scan conversion with spatial dithering
US09/447,144 US6379304B1 (en) 1995-06-29 1999-11-23 Ultrasound scan conversion with spatial dithering
US10/114,183 US20030028113A1 (en) 1995-06-29 2002-04-02 Ultrasound scan conversion with spatial dithering
US11/981,759 US8241217B2 (en) 1995-06-29 2007-10-31 Portable ultrasound imaging data
US12/006,830 US8628474B2 (en) 1995-06-29 2008-01-04 Portable ultrasound imaging system
US12/008,098 US8469893B2 (en) 1995-06-29 2008-01-08 Portable ultrasound imaging system
US13/925,346 US20180310913A9 (en) 1995-06-29 2013-06-24 Portable ultrasound imaging system
US14/154,072 US20140128740A1 (en) 1995-06-29 2014-01-13 Portable ultrasound imaging system

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US08/496,805 US5839442A (en) 1995-06-29 1995-06-29 Portable ultrasound imaging system
US08/496,804 US5590658A (en) 1995-06-29 1995-06-29 Portable ultrasound imaging system
US08/496,805 1995-06-29
US08/496,804 1995-06-29
US08/599,816 US5690114A (en) 1995-06-29 1996-02-12 Portable ultrasound imaging system
US08/599,816 1996-02-12

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08/599,816 Continuation-In-Part US5690114A (en) 1995-06-29 1996-02-12 Portable ultrasound imaging system

Related Child Applications (5)

Application Number Title Priority Date Filing Date
US08/981,427 A-371-Of-International US5964709A (en) 1995-06-29 1996-06-28 Portable ultrasound imaging system
US08/773,647 Continuation-In-Part US5904652A (en) 1995-06-29 1996-12-24 Ultrasound scan conversion with spatial dithering
US08/971,938 Continuation US5957846A (en) 1995-06-29 1997-11-17 Portable ultrasound imaging system
US09/123,991 Continuation US6106472A (en) 1995-06-29 1998-07-28 Portable ultrasound imaging system
US13/925,346 Continuation US20180310913A9 (en) 1995-06-29 2013-06-24 Portable ultrasound imaging system

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WO1997001768A2 true WO1997001768A2 (fr) 1997-01-16
WO1997001768A3 WO1997001768A3 (fr) 1997-01-30

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JP (2) JPH11508461A (fr)
AU (1) AU700274B2 (fr)
CA (1) CA2225622A1 (fr)
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WO (1) WO1997001768A2 (fr)

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TW381226B (en) 2000-02-01
WO1997001768A3 (fr) 1997-01-30
AU6344696A (en) 1997-01-30
CA2225622A1 (fr) 1997-01-16
AU700274B2 (en) 1998-12-24

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