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WO1997040527A1 - Process for producing a doped area in a semiconductor substrate - Google Patents

Process for producing a doped area in a semiconductor substrate Download PDF

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Publication number
WO1997040527A1
WO1997040527A1 PCT/DE1997/000707 DE9700707W WO9740527A1 WO 1997040527 A1 WO1997040527 A1 WO 1997040527A1 DE 9700707 W DE9700707 W DE 9700707W WO 9740527 A1 WO9740527 A1 WO 9740527A1
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WO
WIPO (PCT)
Prior art keywords
trench
main surface
doped
semiconductor substrate
substrate
Prior art date
Application number
PCT/DE1997/000707
Other languages
German (de)
French (fr)
Inventor
Ulrike GRÜNING
Volker Lehmann
Reinhard Stengl
Hermann Wendt
Herbert Schäfer
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1997040527A1 publication Critical patent/WO1997040527A1/en

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H01L21/30608—Anisotropic liquid etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063—Electrolytic etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
    • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Definitions

  • the semiconductor technology is based on the production of doped regions in crystalline semiconductor substrates.
  • dopant is introduced into the semiconductor substrate, so that the electrical properties change.
  • the crystalline structure of the semiconductor substrate remains essentially unchanged in the doped regions.
  • Doped areas are usually produced by diffusion or implantation.
  • the dopant introduced is then electrically activated in a tempering step. Since the diffusion in the semiconductor substrate is essentially isotropic, doped regions produced by diffusion have a lateral extent which is essentially equal to or greater than their depth. The depth of doped areas created by implantation depends on the energy with which the implantation takes place. Doped areas with a depth of up to approximately 5 ⁇ m can be produced by implantation.
  • doped regions are required which have a greater depth than width.
  • Such doped areas are often referred to as vertical doping.
  • such doped regions should have a depth corresponding to the thickness of the semiconductor substrate.
  • the invention is based on the problem of specifying a method for producing a doped region in a semiconductor substrate, with which doped regions of great depth can be produced. This problem is solved by a method according to claim 1. Further refinements of the invention emerge from the remaining claims.
  • a trench is produced in a main surface of a semiconductor substrate.
  • a doped layer is then grown epitaxially.
  • dopant is added so that the doped layer grows up in situ.
  • the doped layer fills the trench.
  • the part of the doped layer arranged in the trench forms the doped region.
  • the dimensions of the doped region depend exclusively on the geometry of the trench.
  • the application of the method can be used particularly advantageously for the production of doped regions with great depth.
  • doped regions with a depth of 5 ⁇ m to 500 ⁇ m, for example 200 ⁇ m and a width of 0.2 ⁇ m to 40 ⁇ m, for example 1 ⁇ m can be realized.
  • the ratio of depth to width is greater than 1.
  • the doped region Since the trench is filled by the doped layer, which is grown epitaxially, the doped region has essentially the same crystal structure as the semiconductor substrate.
  • doped regions both of the same conductivity type as the substrate and of the opposite conductivity type as the substrate can be produced.
  • the dopants are built into the doped layer and electrically activated during epitaxial growth of the doped layers.
  • Tempering step for electrical activation of the dopants is therefore not necessary in the method according to the invention.
  • Parts of the doped layer located on the main surface of the semiconductor substrate can be removed by anisotropic etching or chemical / mechanical polishing.
  • the trench has any cross section parallel to the main surface.
  • the trench can have a circular, square, rectangular, elongated, strip-shaped or annular cross section parallel to the main surface.
  • the trench is made, for example, by anisotropic etching using a mask.
  • the trench is produced by electrochemical etching.
  • the semiconductor substrate is brought into contact with an electrolyte with the main surface.
  • the semiconductor substrate is connected to the electrolyte as an anode.
  • minority charge carriers move in the semiconductor substrate to the main surface in contact with the electrolyte.
  • a space charge zone forms on this surface. Since the field strength in the area of depressions in the surface is greater than outside it, the minority charge carriers preferably move to these points. This leads to a structuring of the surface. The deeper an initially small unevenness becomes due to the etching, the more minority charge carriers move there because of the increased field strength and the stronger the etching attack at this point. In this way, holes grow in the main surface of the semiconductor substrate.
  • Holes that cross the entire semiconductor substrate can be produced by means of electrochemical etching.
  • the arrangement of the holes can be predetermined by providing the main surface with recesses on which the etching attack begins with electrochemical etching.
  • the depressions are formed, for example, by masked etching with an alkaline etching. In order to produce strip-shaped or ring-shaped trenches, these depressions are arranged in such a way that adjacent holes grow together during electrochemical etching.
  • the electrochemical etching takes place in a fluoride-containing, acidic electrolyte.
  • the epitaxy process is preferably carried out in a parameter range in which the epitaxy is limited by the surface reaction. This ensures that the doped layer grows uniformly on the entire surface, that is to say both in the area of the main surface and in the trench.
  • the epitaxial process in the temperature range between 700 ° and 900 °, preferably 850 ° C., in the pressure range between 1 and 20 torr, preferably 10 torr, with at least water is preferably carried out on a semiconductor substrate which comprises monocrystalline silicon at least in the region of the main surface ⁇ substance and dichlorosilane process gas performed.
  • the dopant is added in the form of diborane, phosphorus or arsine.
  • the dopant is added from a storage container which contains diluted dopant in a carrier gas, for example H2 or Ar.
  • a proportion of the dopant of 100 ppm in a gas mixture the flow rate of the gas mixture is set in the range between 0.5 sccm and 6 sccm, preferably 3 sccm.
  • the epitaxy takes place with limited surface reaction.
  • the trench preferably has a slightly conical cross section. This means that the side walls of the trench are tilted a few degrees against the normal of the main surface. This tilt angle is preferably 0.01 ° to 3 °. This ensures a void-free filling of the trench.
  • the method can advantageously be used in the production of power components with deep-reaching doped areas and / or many adjacent low-doped pn junctions.
  • Figure 1 shows a substrate with trenches.
  • FIG. 2 shows the substrate with an epitaxially grown first doped layer and an epitaxially grown second doped layer.
  • Figure 3 shows the substrate after removing the on the
  • Main surface arranged parts of the first doped layer and the second doped layer.
  • a substrate 1 made of, for example, n-doped, monocrystalline silicon is brought into contact with an electrolyte with a main surface 2.
  • the substrate 1 has depressions which are formed, for example, with the aid of a photoresist mask and subsequent alkaline etching with KOH.
  • the electrolyte contains fluoride and is acidic. It contains a hydrofluoric acid concentration of 1 to 50 percent by weight, preferably 6 percent by weight.
  • An oxidizing agent for example hydrogen peroxide, can be added to the electrolyte to suppress the development of hydrogen bubbles on the main surface 2 of the substrate 1.
  • a voltage of, for example, 3 volts is applied between the substrate 1 and the electrolytes.
  • the substrate 1, which has a specific resistance of 5 ⁇ cm, for example, is connected as an anode.
  • the substrate 1 is illuminated from a surface opposite the main surface 2.
  • a current density of 10 mA / cm * ⁇ is set in the substrate 1 by the illumination.
  • trenches 3 are etched into the main surface 2 (see FIG. 1).
  • the trenches 3 have an essentially circular cross section in the region of the main surface 2.
  • the trenches 3 In the area of the main surface 2, the trenches 3 have a diameter of, for example, 1 ⁇ m.
  • the trenches 3 are produced with a depth of, for example, 200 ⁇ m.
  • the trenches 3 have slightly conical side walls which are tilted by 0.1 ° with respect to the normal to the main surface 2 (this tilting is not shown in the figures).
  • a first doped layer 4 is grown on the main surface 2 and the surface of the trenches 3.
  • the epitaxial process is carried out, for example, at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane. Phosphon or arsine from a gas mixture containing H2 or Ar and 100 ppm dopant is added as a dopant with a flow rate of 3 sccm.
  • the first doped layer 4 is n + -doped with a dopant concentration of 10 ⁇ 7 cm " 3.
  • the first doped layer 4 is grown in a layer thickness of, for example, 0.2 ⁇ m. Since the epitaxy process is in the parameter range used is surface reaction limited, the first doped layer 4 grows with an essentially constant layer thickness.
  • a second doped layer 5 is grown on the first doped layer 4 in a further epistemic process.
  • the second epitaxial process is carried out at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane.
  • diborane from a gas mixture containing H2 or Ar and 100 ppm diborane is added at a flow rate of 3 sccm.
  • the second doped layer 5 is p + -doped with a dopant concentration of, for example, 10- 1 - 7 cm " 3.
  • the second doped layer 5 is grown in a layer thickness of, for example, 0.3 ⁇ m.
  • the first doped layer 4 and the second doped layer 5 completely fill the trenches 3 (see FIG. 2).
  • the second main surface of the substrate 1 is then exposed outside the trenches 3 by chemical / mechanical polishing (see FIG. 3).
  • p + -doped regions 5 'and n + -doped regions 4' are formed in the region of the trenches 3.
  • the crystal quality in the p + -doped regions 5 'and in the n + -doped regions 4' is comparable to the crystal quality of the substrate 1.
  • the n + -doped regions 4 'and the p + -doped regions 5' and the parts of the substrate 1 arranged in between form a dense sequence of pn junctions.
  • the p + -doped regions 5 'and the ⁇ -doped regions 4 "extend deeper into the substrate 1 than corresponds to their lateral dimensions.
  • the exemplary embodiment described can be modified in that the n + -doped layer 4 completely fills the trenches 3 or that the n + -doped layer 4 is omitted and the p + -doped layer 5 is grown on the surface of the trenches 3 and the trenches 3 completely filled.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • General Chemical & Material Sciences (AREA)

Abstract

This invention concerns a process for producing a doped area in a semiconductor substrate (1) by producing a trench (3) which is filled in with an epitaxially grown, doped semiconductor layer (4, 5). The process is suitable for producing more deeply doped areas, so-called "vertical doping", as well as many little doped p-n junctions as they are for example needed in new power components.

Description

Beschreibungdescription

Verfahren zur Herstellung eineε dotierten Gebietes in einem HalbleitersubstratMethod for producing a doped region in a semiconductor substrate

Die Halbleitertechnolgie basiert auf der Herstellung dotier¬ ter Gebiete in kristallinen Halbleitersubstraten. Dabei wird Dotierstoff in das Halbleitersubstrat eingebracht, so daß sich die elektrischen Eigenschaften ändern. Die kristalline Struktur des Halbleitersubstrats bleibt jedoch in den dotier¬ ten Gebieten im wesentlichen unverändert.The semiconductor technology is based on the production of doped regions in crystalline semiconductor substrates. In the process, dopant is introduced into the semiconductor substrate, so that the electrical properties change. However, the crystalline structure of the semiconductor substrate remains essentially unchanged in the doped regions.

Die Herstellung von dotierten Gebieten erfolgt üblicherweise durch Diffusion oder Implantation. Anschließend wird der ein- gebrachte Dotierstoff in einem Temperschritt elektrisch akti¬ viert. Da die Diffusion im Halbleitersubstrat im wesentlichen isotrop erfolgt, weisen durch Diffusion hergestellte dotierte Gebiete eine laterale Ausdehnung auf, die im wesentlichen gleich oder größer als deren Tiefe ist. Die Tiefe von durch Implantation hergestellten dotierten Gebieten hängt von der Energie ab, mit der die Implantation erfolgt. Durch Implanta¬ tion können dotierte Gebiete mit einer Tiefe bis etwa 5 μm hergestellt werden.Doped areas are usually produced by diffusion or implantation. The dopant introduced is then electrically activated in a tempering step. Since the diffusion in the semiconductor substrate is essentially isotropic, doped regions produced by diffusion have a lateral extent which is essentially equal to or greater than their depth. The depth of doped areas created by implantation depends on the energy with which the implantation takes place. Doped areas with a depth of up to approximately 5 μm can be produced by implantation.

Für verschiedene technische Anwendungen, zum Beispiel für Leistungsbauelemente, speziell Leistungs-MOSFETs, oder für mikromechanische Anwendungen, werden dotierte Gebiete benö¬ tigt, die eine größere Tiefe als Breite aufweisen. Derartige dotierte Gebiete werden vielfach auch als vertikale Dotierun- gen bezeichnet. Im Grenzfall sollen derartige dotierte Gebie¬ te eine Tiefe entsprechend der Dicke des Halbleitersubstratε aufweisen.For various technical applications, for example for power components, especially power MOSFETs, or for micromechanical applications, doped regions are required which have a greater depth than width. Such doped areas are often referred to as vertical doping. In the limiting case, such doped regions should have a depth corresponding to the thickness of the semiconductor substrate.

Der Erfindung liegt das Problem zugrunde, ein Verfahren zur Herstellung eines dotierten Gebietes in einem Halbleiter¬ substrat anzugeben, mit dem dotierte Gebiete großer Tiefe herstellbar sind. Dieses Problem wird gelöst durch ein Verfahren gemäß Anspruch 1. Weitere Ausgestaltungen der Erfindung gehen aus den übri¬ gen Ansprüchen hervor.The invention is based on the problem of specifying a method for producing a doped region in a semiconductor substrate, with which doped regions of great depth can be produced. This problem is solved by a method according to claim 1. Further refinements of the invention emerge from the remaining claims.

In dem Verfahren wird in einer Hauptfläche eines Halbleiter¬ substrats ein Graben erzeugt. Anschließend wird eine dotierte Schicht epitaktisch aufgewachsen. Bei dem Epitaxieprozeß wird Dotierstoff zugegeben, so daß die dotierte Schicht insitu do- tiert aufwächst. Die dotierte Schicht füllt den Graben auf. Der im Graben angeordnete Teil der dotierten Schicht bildet das dotierte Gebiet. Die Abmessungen des dotierten Gebietes hängen in diesem Fall ausschließlich von der Geometrie des Grabens ab. Die Anwendung des Verfahrens ist zur Herstellung von dotierten Gebieten mit großer Tiefe besonders vorteilhaft einsetzbar. Insbesondere können dotierte Gebiete mit einer Tiefe von 5 um bis 500 μm, zum Beispiel 200 μm, und einer Weite von 0,2 μm bis 40 μm, zum Beispiel 1 μm, realisiert werden. Dabei ist das Verhältnis von Tiefe zu Weite (Aspektverhältnis) größer 1.In the method, a trench is produced in a main surface of a semiconductor substrate. A doped layer is then grown epitaxially. In the epitaxial process, dopant is added so that the doped layer grows up in situ. The doped layer fills the trench. The part of the doped layer arranged in the trench forms the doped region. In this case, the dimensions of the doped region depend exclusively on the geometry of the trench. The application of the method can be used particularly advantageously for the production of doped regions with great depth. In particular, doped regions with a depth of 5 μm to 500 μm, for example 200 μm and a width of 0.2 μm to 40 μm, for example 1 μm, can be realized. The ratio of depth to width (aspect ratio) is greater than 1.

Da der Graben von der dotierten Schicht, die epitaktisch auf¬ gewachsen wird, aufgefüllt wird, weist das dotierte Gebiet im wesentlichen dieselbe Kristallstruktur wie das Halbleiter- Substrat auf.Since the trench is filled by the doped layer, which is grown epitaxially, the doped region has essentially the same crystal structure as the semiconductor substrate.

In dem erfindungsgemäßen Verfahren können dotierte Gebiete sowohl desselben Leitfähigkeitstyps wie das Substrat als auch vom entgegengesetzten Leitfähigkeitstyp wie das Substrat her- gestellt werden.In the method according to the invention, doped regions both of the same conductivity type as the substrate and of the opposite conductivity type as the substrate can be produced.

Da Epitaxieprozesse bei Temperaturen deutlich oberhalb 500°C durchgeführt werden, werden die Dotierstoffe beim epitakti¬ schen Aufwachsen der dotierten Schichten in die dotierte Schicht eingebaut und elektrisch aktiviert. Ein separaterSince epitaxial processes are carried out at temperatures significantly above 500 ° C., the dopants are built into the doped layer and electrically activated during epitaxial growth of the doped layers. A separate one

Temperschritt zur elektrischen Aktivierung der Dotierstoffe ist daher in dem erfindungsgemäßen Verfahren nicht erforder¬ lich.Tempering step for electrical activation of the dopants is therefore not necessary in the method according to the invention.

Auf der Hauptfläche des Halbleitersubstrats befindliche Teile der dotierten Schicht können durch anisotropes Ätzen oder chemisch/mechanisches Polieren entfernt werden.Parts of the doped layer located on the main surface of the semiconductor substrate can be removed by anisotropic etching or chemical / mechanical polishing.

Der Graben weist parallel zur Hauptfläche einen beliebigen Querschnitt auf. Insbesondere kann der Graben parallel zur Hauptfläche einen kreisförmigen, quadratischen, rechteckigen, länglichen, streifenförmigen oder ringförmigen Querschnitt aufweisen.The trench has any cross section parallel to the main surface. In particular, the trench can have a circular, square, rectangular, elongated, strip-shaped or annular cross section parallel to the main surface.

Der Graben wird zum Beispiel durch anisotropes Ätzen unter Verwendung einer Maske hergestellt. Alternativ wird der Gra¬ ben durch elektrochemisches Ätzen hergestellt.The trench is made, for example, by anisotropic etching using a mask. Alternatively, the trench is produced by electrochemical etching.

Beim elektrochemischen Ätzen wird das Halbleitersubstrat mit der Hauptfläche mit einem Elektrolyten in Kontakt gebracht. Das Halbleitersubstrat wird gegenüber dem Elektrolyten als Anode geschaltet. Dadurch bewegen sich Minoritätsladungsträ¬ ger im Halbleitersubstrat zur der mit dem Elektrolyten in Kontakt stehenden Hauptfläche. An dieser Fläche bildet sich eine Raumladungszone aus. Da die Feldstärke im Bereich von Vertiefungen in der Oberfläche größer ist als außerhalb da¬ von, bewegen sich die Minoritätsladungsträger bevorzugt zu diesen Punkten. Dadurch kommt es zu einer Strukturierung der Oberfläche. Je tiefer eine anfänglich kleine Unebenheit durch die Ätzung wird, desto mehr Minoritätsladungsträger bewegen sich wegen der vergrößerten Feldstärke dorthin und desto stärker ist der Ätzangriff an dieser Stelle. Auf diese Weise wachsen Löcher in der Hauptfläche des Halbleitersubstrats.In the case of electrochemical etching, the semiconductor substrate is brought into contact with an electrolyte with the main surface. The semiconductor substrate is connected to the electrolyte as an anode. As a result, minority charge carriers move in the semiconductor substrate to the main surface in contact with the electrolyte. A space charge zone forms on this surface. Since the field strength in the area of depressions in the surface is greater than outside it, the minority charge carriers preferably move to these points. This leads to a structuring of the surface. The deeper an initially small unevenness becomes due to the etching, the more minority charge carriers move there because of the increased field strength and the stronger the etching attack at this point. In this way, holes grow in the main surface of the semiconductor substrate.

Durch elektrochemisches Ätzen können Löcher, die das gesamte Halbleitersubstrat durchqueren, hergestellt werden. Die An¬ ordnung der Löcher kann dadurch vorgegeben werden, daß die Hauptfläche gezielt mit Vertiefungen versehen wird, an denen der Ätzangriff beim elektrochemischen Ätzen beginnt. Die Ver¬ tiefungen werden zum Beispiel durch maskiertes Ätzen mit ei¬ ner alkalischen Ätze gebildet. Zur Herstellung streifenför- miger oder ringförmiger Gräben werden diese Vertiefungen so angeordnet, daß benachbarte Löcher beim elektrochemischen Ät¬ zen zusammenwachsen.Holes that cross the entire semiconductor substrate can be produced by means of electrochemical etching. The arrangement of the holes can be predetermined by providing the main surface with recesses on which the etching attack begins with electrochemical etching. The depressions are formed, for example, by masked etching with an alkaline etching. In order to produce strip-shaped or ring-shaped trenches, these depressions are arranged in such a way that adjacent holes grow together during electrochemical etching.

Bei Verwendung eines Halbleitersubstrats, das mindestens im Bereich der Hauptfläche n-dotiertes monokristallines Silizium umfaßt, erfolgt das elektrochemische Ätzen in einem fluorid- haltigen, sauren Elektrolyten.When using a semiconductor substrate which comprises n-doped monocrystalline silicon at least in the region of the main surface, the electrochemical etching takes place in a fluoride-containing, acidic electrolyte.

Der Epitaxieprozeß erfolgt vorzugsweise in einem Parameterbe¬ reich, in dem die Epitaxie oberflächenreaktionslimitiert ist. Dadurch wird sichergestellt, daß auf der gesamten Oberfläche, das heißt sowohl im Bereich der Hauptfläche als auch im Gra¬ ben, gleichmäßig die dotierte Schicht aufwächst.The epitaxy process is preferably carried out in a parameter range in which the epitaxy is limited by the surface reaction. This ensures that the doped layer grows uniformly on the entire surface, that is to say both in the area of the main surface and in the trench.

Vorzugsweise wird auf einem Halbleitersubstrat, das minde- stens im Bereich der Hauptfläche monokristallines Silizium umfaßt, der Epitaxieprozeß im Temperaturbereich zwischen 700° und 900°, vorzugsweise 850°C, im Druckbereich zwischen 1 und 20 Torr, vorzugsweise 10 Torr, mit einem mindestens Wasser¬ stoff und Dichlorsilan umfassenden Prozeßgas durchgeführt. Dabei wird der Durchfluß des Wasserstoffs im Bereich zwischen 30 und 50 slm (Standardliter pro Minute) , vorzugsweise 40 slm und der Durchfluß von Dichlorsilan im Bereich zwischen 50 und 250 sccm, vorzugsweise 200 sccm (Standardkubikzentimeter) durchgeführt. Der Dotierstoff wird in Form von Diboran, Phos- ohin oder Arsin zugegeben. Der Dotierstoff wird dabei aus ei- ιem Vorratsbehälter zugegeben, der in einem Trägergas, zum Beispiel H2 oder Ar, verdünnten Dotierstoff enthält. Bei ei¬ nem Anteil des Dotierstoffes von 100 ppm in einem Gasgemisch wird der Durchfluß des Gasgemisches im Bereich zwischen 0,5 sccm und 6 sccm , vorzugsweise 3 sccm , eingestellt. Bei die¬ sen Prozeßparametern erfolgt die Epitaxie oberflächenreakti- onslimittiert. Vorzugsweise weist der Graben einen leicht konischen Quer¬ schnitt auf. Das heißt, die Seitenwände des Grabens sind um wenige Grad gegen die Normale der Hauptfläche verkippt. Vor- zugsweise beträgt dieser Verkippungswinkel 0,01° bis 3°. Da¬ durch wird ein lunkerfreies Auffüllen des Grabens sicherge¬ stellt.The epitaxial process in the temperature range between 700 ° and 900 °, preferably 850 ° C., in the pressure range between 1 and 20 torr, preferably 10 torr, with at least water is preferably carried out on a semiconductor substrate which comprises monocrystalline silicon at least in the region of the main surface ¬ substance and dichlorosilane process gas performed. The flow of hydrogen in the range between 30 and 50 slm (standard liters per minute), preferably 40 slm, and the flow of dichlorosilane in the range between 50 and 250 sccm, preferably 200 sccm (standard cubic centimeter). The dopant is added in the form of diborane, phosphorus or arsine. The dopant is added from a storage container which contains diluted dopant in a carrier gas, for example H2 or Ar. With a proportion of the dopant of 100 ppm in a gas mixture, the flow rate of the gas mixture is set in the range between 0.5 sccm and 6 sccm, preferably 3 sccm. With these process parameters, the epitaxy takes place with limited surface reaction. The trench preferably has a slightly conical cross section. This means that the side walls of the trench are tilted a few degrees against the normal of the main surface. This tilt angle is preferably 0.01 ° to 3 °. This ensures a void-free filling of the trench.

Das Verfahren ist vorteilhaft einsetzbar bei der Herstellung von Leistungsbauelementen mit tief reichenden dotierten Ge¬ bieten und/oder vielen einander benachbarten niedrig dotier¬ ten pn-Übergängen.The method can advantageously be used in the production of power components with deep-reaching doped areas and / or many adjacent low-doped pn junctions.

Im folgenden wird die Erfindung anhand eines Ausfuhrungsbei- spiels und der Figuren näher erläutert.The invention is explained in more detail below on the basis of an exemplary embodiment and the figures.

Figur 1 zeigt ein Substrat mit Gräben.Figure 1 shows a substrate with trenches.

Figur 2 zeigt das Substrat mit einer epitaktisch aufgewachse- nen ersten dotierten Schicht und einer epitaktisch aufgewachsenen zweiten dotierten Schicht.FIG. 2 shows the substrate with an epitaxially grown first doped layer and an epitaxially grown second doped layer.

Figur 3 zeigt das Substrat nach Entfernen der auf derFigure 3 shows the substrate after removing the on the

Hauptfläche angeordneten Teile der ersten dotierten Schicht und der zweiten dotierten Schicht.Main surface arranged parts of the first doped layer and the second doped layer.

Ein Substrat 1 aus zum Beispiel n-dotiertem, monokristallinem Silizium wird mit einer Hauptfläche 2 mit einem Elektrolyten in Kontakt gebracht. In der Hauptfläche 2 weist das Substrat 1 Vertiefungen auf, die zum Beispiel mit Hilfe einer Foto¬ lackmaske und anschließender alkalischer Ätzung mit KOH ge¬ bildet werden.A substrate 1 made of, for example, n-doped, monocrystalline silicon is brought into contact with an electrolyte with a main surface 2. In the main surface 2, the substrate 1 has depressions which are formed, for example, with the aid of a photoresist mask and subsequent alkaline etching with KOH.

Der Elektrolyt ist fluoridhaltig und sauer. Er enthält eine Flußsäurekonzentration von 1 bis 50 Gewichtsprozent, vorzugs¬ weise 6 Gewichtsprozent. Dem Elektrolyten kann ein Oxidati¬ onsmittel, zum Beispiel Wasserstoffsuperoxyd, zugesetzt wer- den, um die Entwicklung von Wasserstoffbläschen auf der Hauptfläche 2 des Substrats 1 zu unterdrücken. Zwischen dem Substrat 1 und den Elektrolyten wird eine Spannung von zum Beispiel 3 Volt angelegt. Dabei wird das Substrat 1, das zum Beispiel einen spezifischen Widerstand von 5 Ωcm aufweist, als Anode verschaltet. Das Substrat 1 wird von einer der Hauptfläche 2 gegenüberliegenden Fläche her beleuchtet. Durch die Beleuchtung wird in dem Substrat 1 eine Stromdichte von 10 mA/crn*^ eingestellt.The electrolyte contains fluoride and is acidic. It contains a hydrofluoric acid concentration of 1 to 50 percent by weight, preferably 6 percent by weight. An oxidizing agent, for example hydrogen peroxide, can be added to the electrolyte to suppress the development of hydrogen bubbles on the main surface 2 of the substrate 1. A voltage of, for example, 3 volts is applied between the substrate 1 and the electrolytes. The substrate 1, which has a specific resistance of 5 Ωcm, for example, is connected as an anode. The substrate 1 is illuminated from a surface opposite the main surface 2. A current density of 10 mA / cm * ^ is set in the substrate 1 by the illumination.

Mit diesen Prozeßparametern werden Gräben 3 in die Hauptflä¬ che 2 geätzt (s. Figur 1). Die Gräben 3 weisen im Bereich der Hauptfläche 2 einen im wesentlichen kreisförmigen Querschnitt auf. Im Bereich der Hauptfläche 2 weisen die Gräben 3 einen Durchmesser von zum Beispiel 1 μm auf. Die Gräben 3 werden mit einer Tiefe von zum Beispiel 200 μm erzeugt. Die Gräben 3 weisen leicht konische Seitenwände auf, die gegenüber der Normalen der Hauptfläche 2 um 0,1° verkippt sind (diese Ver¬ kippung ist in den Figuren nicht dargestellt) .With these process parameters, trenches 3 are etched into the main surface 2 (see FIG. 1). The trenches 3 have an essentially circular cross section in the region of the main surface 2. In the area of the main surface 2, the trenches 3 have a diameter of, for example, 1 μm. The trenches 3 are produced with a depth of, for example, 200 μm. The trenches 3 have slightly conical side walls which are tilted by 0.1 ° with respect to the normal to the main surface 2 (this tilting is not shown in the figures).

Anschließend wird ein Epitaxieprozeß durchgeführt, bei dem auf die Hauptfläche 2 und die Oberfläche der Gräben 3 eine erste dotierte Schicht 4 aufgewachsen wird. Der Epitaxiepro¬ zeß wird zum Beispiel bei 850°C, 10 Torr mit 40 slm Wasser- stoff und 200 sccm Dichlorsilan durchgeführt. Als Dotierstoff wird Phosphon oder Arsin aus einem Gasgemisch, das H2 oder Ar und 100 ppm Dotierstoff enthält, mit einem Durchfluß von 3 sccm zugegeben. Die erste dotierte Schicht 4 wird n+-dotiert mit einer Dotierstoffkonzentration von lO^7 cm"3 . Die erste dotierte Schicht 4 wird in einer Schichtdicke von zum Bei¬ spiel 0,2 μm aufgewachsen. Da der Epitaxieprozeß in dem ver¬ wendeten Parameterbereich oberflächenreaktionslimittiert ist, wächst die erste dotierte Schicht 4 mit einer im wesentlichen konstanten Schichtdicke auf.An epitaxial process is then carried out, in which a first doped layer 4 is grown on the main surface 2 and the surface of the trenches 3. The epitaxial process is carried out, for example, at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane. Phosphon or arsine from a gas mixture containing H2 or Ar and 100 ppm dopant is added as a dopant with a flow rate of 3 sccm. The first doped layer 4 is n + -doped with a dopant concentration of 10 ^ 7 cm " 3. The first doped layer 4 is grown in a layer thickness of, for example, 0.2 μm. Since the epitaxy process is in the parameter range used is surface reaction limited, the first doped layer 4 grows with an essentially constant layer thickness.

Auf die erste dotierte Schicht 4 wird in einem weiteren Epi¬ taxieprozeß eine zweite dotierte Schicht 5 aufgewachsen. Der zweite Epitaxieprozeß wird bei 850°C, 10 Torr mit 40 slm Was¬ serstoff und 200 sccm Dichlorsilan durchgeführt. Bei dem zweiten Epitaxieprozeß wird Diboran aus einem Gasgemisch, das H2 oder Ar und 100 ppm Diboran enthält, mit einer Durchfluß- rate von 3 sccm zugegeben. Die zweite dotierte Schicht 5 wird p+-dotiert mit einer Dotierstoffkonzentration von zum Bei¬ spiel 10-1-7 cm"3 . Die zweite dotierte Schicht 5 wird in einer Schichtdicke von zum Beispiel 0,3 μm aufgewachsen.A second doped layer 5 is grown on the first doped layer 4 in a further epistemic process. The second epitaxial process is carried out at 850 ° C., 10 torr with 40 slm hydrogen and 200 sccm dichlorosilane. In the second epitaxial process, diborane from a gas mixture containing H2 or Ar and 100 ppm diborane is added at a flow rate of 3 sccm. The second doped layer 5 is p + -doped with a dopant concentration of, for example, 10- 1 - 7 cm " 3. The second doped layer 5 is grown in a layer thickness of, for example, 0.3 μm.

Die erste dotierte Schicht 4 und die zweite dotierte Schicht 5 füllen die Gräben 3 vollständig auf (s. Figur 2) .The first doped layer 4 and the second doped layer 5 completely fill the trenches 3 (see FIG. 2).

Anschließend wird durch chemisch/mechanisches Polieren die zweite Hauptfläche des Substrats 1 außerhalb der Gräben 3 freigelegt (siehe Figur 3) . Auf diese Weise entstehen im Be¬ reich der Gräben 3 p+-dotierte Gebiete 5' und n+-dotierte Ge¬ biete 4'. Die Kristallqualität in den p+-dotierten Gebieten 5' und in den n+-dotierten Gebieten 4' ist vergleichbar mit der Kristallqualität des Substrats 1. Die n+-dotierten Ge- biete 4' und die p+-dotierten Gebiete 5' sowie die dazwischen angeordneten Teile des Substrats 1 bilden eine dichte Folge von pn-Obergängen. Die p+-dotierten Gebiete 5' und die ^-do¬ tierten Gebiete 4" erstrecken sich tiefer in das Substrat 1 hinein, als es ihren lateralen Abmessungen entspricht.The second main surface of the substrate 1 is then exposed outside the trenches 3 by chemical / mechanical polishing (see FIG. 3). In this way, p + -doped regions 5 'and n + -doped regions 4' are formed in the region of the trenches 3. The crystal quality in the p + -doped regions 5 'and in the n + -doped regions 4' is comparable to the crystal quality of the substrate 1. The n + -doped regions 4 'and the p + -doped regions 5' and the parts of the substrate 1 arranged in between form a dense sequence of pn junctions. The p + -doped regions 5 'and the ^ -doped regions 4 "extend deeper into the substrate 1 than corresponds to their lateral dimensions.

Das beschriebene Ausführungsbeispiel kann dadurch abgewandelt werden, daß die n+-dotierte Schicht 4 die Gräben 3 vollstän¬ dig auffüllt oder daß die n+-dotierte Schicht 4 entfällt und die p+-dotierte Schicht 5 auf die Oberfläche der Gräben 3 aufgewachsen wird und die Gräben 3 vollständig auffüllt. The exemplary embodiment described can be modified in that the n + -doped layer 4 completely fills the trenches 3 or that the n + -doped layer 4 is omitted and the p + -doped layer 5 is grown on the surface of the trenches 3 and the trenches 3 completely filled.

Claims

Patentansprüche claims 1. Verfahren zur Herstellung eines dotierten Gebietes in ei¬ nem Halbleitersubstrat,1. Process for producing a doped region in a semiconductor substrate, - bei dem in einer Hauptfläche (2) des Halbleitersubstrats (1) ein Graben (3) erzeugt wird,- in which a trench (3) is produced in a main surface (2) of the semiconductor substrate (1), - bei dem in einem Epitaxieprozeß unter Zugabe von Dotier- stoff eine dotierte Schicht (4, 5) aufgewachsen wird, die den Graben (3) auffüllt und deren im Graben (3) angeordne¬ ter Teil das dotierte Gebiet (4', 5') bildet.- in which in an epitaxial process with the addition of dopant a doped layer (4, 5) is grown, which fills the trench (3) and whose part arranged in the trench (3) contains the doped region (4 ', 5' ) forms. 2. Verfahren nach Anspruch 1, bei dem der Graben (3) eine Tiefe aufweist, die größer ist als mindestens eine lineare Ausdehnung des Grabens (3) paral¬ lel zur Hauptfläche (2).2. The method according to claim 1, wherein the trench (3) has a depth that is greater than at least one linear extension of the trench (3) parallel to the main surface (2). 3. Verfahren nach Anspruch 1 oder 2, bei dem der Graben (3) Flanken aufweist, die gegen die Norma¬ le der Hauptfläche (2) um 0,01° bis 3° geneigt sind.3. The method according to claim 1 or 2, wherein the trench (3) has flanks which are inclined to the normal surface of the main surface (2) by 0.01 ° to 3 °. 4. Verfahren nach einem der Ansprüche 1 bis 3, bei dem das Halbleitersubstrat (1) mindestens im Bereich der Hauptfläche (2) monokristallines Silizium umfaßt.4. The method according to any one of claims 1 to 3, wherein the semiconductor substrate (1) comprises at least in the region of the main surface (2) monocrystalline silicon. 5. Verfahren nach Anspruch 4, bei dem der Graben (3) durch elektrochemisches Ätzen in einem fluoridhaltigen, sauren Elektrolyten, der mit der Hauptfläche (2) in Kontakt steht und gegen den das Substrat (1) als Anode verschaltet ist, erzeugt wird.5. The method according to claim 4, wherein the trench (3) is produced by electrochemical etching in a fluoride-containing, acidic electrolyte which is in contact with the main surface (2) and against which the substrate (1) is connected as an anode. 6. Verfahren nach Anspruch 4 oder 5, bei dem der Epitaxieprozeß im Temperaturbereich zwischen 700 und 900°C, im Druckbereich zwischer 1 und 20 Torr mit einem Wasserstoff und Dichlorsilan umfassenden Prozeßgas, wobei die Durchflußrate des Wasserstoff zwischen 30 und 50 slm (Standardliter pro Minute) und die Durchflußrate des Dichlor¬ silan im Bereich zwischen 50 und 250 sccm6. The method of claim 4 or 5, wherein the epitaxial process in the temperature range between 700 and 900 ° C, in the pressure range between 1 and 20 torr with a hydrogen and dichlorosilane comprising process gas, the flow rate of hydrogen between 30 and 50 slm (Standard liters per minute) and the flow rate of the dichlorosilane in the range between 50 and 250 sccm (Standardkubikzentimeter) eingestellt wird und bei dem als Dotierstoff Diboran, Arsin oder Phosphin zugegeben wird.(Standard cubic centimeter) is set and in which diborane, arsine or phosphine is added as the dopant. 7. Verfahren nach einem der Ansprüche 1 biε 6,7. The method according to any one of claims 1 to 6, - bei dem in der Hauptfläche (2) mehrere Gräben (3) erzeugt werden, deren Abstand geringer als ihre Tiefe ist,- in which several trenches (3) are created in the main surface (2), the spacing of which is less than their depth, - bei dem die epitaktisch-aufgewachsene, dotierte Schicht (4, 5) die Gräben auffüllt und so in jedem Graben ein dotiertes Gebiet (4', 5') bildet. - In which the epitaxially grown, doped layer (4, 5) fills the trenches and thus forms a doped region (4 ', 5') in each trench.
PCT/DE1997/000707 1996-04-22 1997-04-07 Process for producing a doped area in a semiconductor substrate WO1997040527A1 (en)

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