WO1996038912A1

WO1996038912A1 - Variable delay circuit

Info

Publication number: WO1996038912A1
Application number: PCT/JP1996/001482
Authority: WO
Inventors: Hiroo Suzuki; Toshiyuki Okayasu
Original assignee: Advantest Corporation
Priority date: 1995-06-02
Filing date: 1996-05-31
Publication date: 1996-12-05
Also published as: TW307955B; DE19680525T1; KR970705234A; JPH08330921A

Abstract

A variable delay circuit using logic circuits constituted in a CMOS IC. The delay circuit comprises a plurality of cascaded logic devices LG in a CMOS IC to produce a time delay depending on the number of logic devices. A series circuit comprising an MOS transistor and a capacitor C is connected between a junction of adjacent logic devices or each output and a common potential point. A bias voltage applied to the gate of the MOS transistor is controlled to vary the resistance value between the drain and the source. In this way, the time constant of the series circuit is changed and the delay time is continuously changed.

Description

Description Variable delay circuit Technical field

The present invention relates to a variable delay circuit useful for, for example, generating various timing signals.

'Jing Technology—

For example, in an IC tester for testing various semiconductor integrated circuits (ICs), various timing signals are required to generate a test pattern given to an IC under test and various control signals. In a conventional timing signal generator for generating various timing signals, generally, a large number of delay elements are cascaded, and a desired delay time is provided between each stage of the cascade-connected delay elements or from each output side. delay circuit force ^s are used and configured to obtain a timing signal having a. For each delay element, a logic element formed as an IC such as an IC having a MOS structure (MOS · IC) is generally used. For example, a large number of cascaded logic gate elements are formed as a CMOS integrated circuit (CMOS · IC) having a CMOS (complementary MOS) structure, and the logic gate elements between the cascade-connected logic gate elements or between each stage are formed. A delay circuit for extracting a signal having a different delay time from each output side is conventionally known. The signal extracted from this delay circuit is used as various timing signals.

However, in a conventional delay circuit using a large number of logic elements, the delay time given to the input signal is determined by the number of connection stages of the logic elements, so that the delay time cannot be finely adjusted. Therefore, there is a disadvantage that the delay time cannot be set with a fine resolution. Disclosure of the invention

One object of the present invention is to provide a variable delay circuit capable of setting a delay time with fine resolution. Another object of the present invention is to provide a variable delay circuit capable of automatically maintaining a delay time at a constant value.

According to a first aspect of the present invention, there is provided a delay circuit configured to extract a signal having a different delay time ^s from each stage or from each output side of a plurality of cascaded logic elements formed as an IC. A series circuit composed of a field-effect transistor and a capacitor is connected between each stage of a plurality of connected logic elements or between each output side and a common potential point to continuously change a delay time. A variable delay circuit is provided.

In a preferred embodiment, the plurality of cascaded logic elements are formed as CMO S ICs, and a CM 0 S electric field is applied between each stage of the cascaded logic elements or between each output and a common potential point. A series circuit composed of an effect transistor and a capacitor is connected.

According to the variable delay circuit according to the first aspect, a forward bias is applied to the gate electrode of the field effect transistor connected in series with the capacitance element, and the forward bias voltage is changed, so that the The resistance value between drain and source can be changed. Therefore, it becomes equivalent to a circuit configuration in which a variable resistor is connected in series with a capacitive element. By changing the resistance value of this variable resistor, the delay time of the logical element can be finely adjusted.

According to the second aspect of the present invention, a p-type (p-channel) MOS field-effect transistor and an n-type (n-channel) MOS field-effect transistor are connected in series by connecting their drain electrodes in common. At the same time, the gate electrodes of these field effect transistors are connected in common, and the connection point is used as an input terminal, and the connection point of both commonly connected drain electrodes is used as an output terminal to constitute a polarity inversion type logic circuit. In a delay circuit that uses this logic circuit as a delay element, a variable delay circuit that controls the delay time by changing the bias voltage applied to each substrate electrode of the p-type MOS field-effect transistor and the n-type MOS field-effect transistor Is provided.

According to the variable delay circuit according to the second aspect, the delay time is continuously changed by changing the voltage applied to each substrate electrode of the p-type MOS field-effect transistor and the n-type MOS field-effect transistor. Can be done. As a result, the delay It is possible to provide a variable delay circuit that can maintain the delay time automatically at a constant value by the addition of automatic control means. Description

FIG. 1 is a circuit connection diagram showing a first embodiment of the variable delay circuit according to the present invention. FIG. 2 is a circuit connection diagram electrically equivalent to the variable delay circuit shown in FIG.

FIG. 3 is a circuit connection diagram showing a second embodiment of the variable delay circuit according to the present invention. FIG. 4 is a circuit connection diagram that is electrically equivalent to the variable delay circuit shown in FIG.

FIG. 5 is a block diagram showing an application example of the variable delay circuit shown in FIG. BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a first embodiment of the variable delay circuit according to the present invention. The variable delay circuit, generally designated by reference numeral 1, is composed of a plurality (two in this example) of logic elements LG, such as a buffer amplifier, connected in cascade between its input terminal 2 and output terminal 3. And a series circuit composed of a field effect transistor Tr and a capacitor C connected between the stages of the logic elements LG and the common potential point (ground point) G. This variable delay circuit is formed as CMOS.IC. The gate electrode of the field-effect transistor Tr is connected to a control terminal 4 provided outside the CMOS IC, and a control voltage is applied to the control terminal 4 so that the resistance value between the drain and the source of the field-effect transistor Tr is reduced. Set any resistance value.

With this configuration, the field effect transistor Tr of the variable delay circuit 1 can be regarded as a circuit element equivalent to the variable resistor VR as shown in FIG. Accordingly, the time constant of the capacitor C can be changed by changing the control voltage applied to the gate of the field-effect transistor Tr to change the resistance value between the drain and source of the field-effect transistor Tr. Therefore, the delay time between the input terminal 2 and the output terminal 3 can be continuously and finely changed. Therefore, the variable delay circuit 1 having the configuration shown in FIG. 1 is cascaded, and a delay signal is extracted from an arbitrary stage of the cascade-connected variable delay circuits. However, a slightly different delay signal can be obtained. That is, the delay time can be accurately set to the target value.

FIG. 3 shows a second embodiment of the variable delay circuit according to the present invention. In this embodiment, a p-type MOS field-effect transistor PMOS and an n-type MOS field-effect transistor NMOS are connected in series by connecting their drain electrodes D in common, and a gate electrode is formed. Gs are commonly connected, the connection point of the commonly connected gate electrode is connected to the input terminal 2, and the output terminal 3 is derived from the connection point of the commonly connected drain electrode D. This series connection circuit of the p-type MOS field-effect transistor PMOS and the n-type MOS field-effect transistor NMOS is equivalent to a polarity inversion amplifier, also called an inverter. Further, a variable delay circuit 1 is configured by connecting a capacitor C between a connection point of the commonly connected drain electrode D and a common potential point (ground point). This variable delay circuit 1 is also formed as a CMOS IC. In this embodiment, the substrate electrodes 5 and 6 of the p-type M 0 S field-effect transistor PM 0 S and the n-type M 0 S field-effect transistor NMOS are separated from the source electrode, and the substrate bias voltage is applied to the substrate electrodes 5 and 6. + V _BP and one V _BN . Here, the substrate bias voltage + V _BP and one VBN apply the voltage applied to the source of the P-type M 0 S field-effect transistor PM〇S to + VDD, and the voltage applied to the source electrode of the n-type M 0 S field-effect transistor XM 0 S Voltage is 1 Vss,

VBP = VDD + β

VBN ⁼ VSS (1).

FIG. 4 shows an electrical equivalent circuit of the variable delay circuit 1 of FIG. Assuming that the input voltage supplied to the commonly connected gate electrode G is greatly excited from 1 Vss to + VDD, the p-type MOS field-effect transistor PMOS and the n-type MOS field-effect transistor NMOS are it force regarded as a series circuit of respectively switch SW as shown in Figure 4 and the resistor ^R? can. When the substrate noise voltage + V BP and one V BN are changed, the threshold voltages of the field effect transistors PMOS and NMOS are changed, and the resistance value of the resistor R can be equivalently changed. The resistance value is in equation (1). When and are 《= 0, = 0, the minimum value is obtained. When the absolute value of 《and / 3 is increased, Control can be performed in the direction in which the resistance value increases.

As a result, . = 0, /? = 0, the time constant of the resistor R and the capacitor C connected to the output terminal 3 becomes the shortest time as the field-effect transistor turns on and off. Increasing the absolute value of? Gradually increases the time constant. Therefore, the delay time can be continuously changed from the change of the time constant.

FIG. 5 shows an application example of the variable delay circuit shown in FIG. In this example, a control circuit that automatically controls the variable delay circuit 1 shown in Fig. 3 to prevent the delay time ^s ' from changing due to temperature fluctuations and to maintain a constant delay time is added. It is.

In FIG. 5, the logic element denoted by reference numeral 10 is an in-phase amplification type (polarity non-inverting type) variable delay circuit configured by cascading two stages of the polarity inversion type variable delay circuit 1 shown in FIG. is there. N in-phase amplification type variable delay circuits 10 are cascaded to form an N-stage variable delay circuit 11. The N-stage variable delay circuit 11 is formed as CMOS · IC.

Connect the output terminal of the N-stage variable delay circuit 11 (the output terminal of the final-stage in-phase amplification type variable delay circuit 10) to one input terminal of the phase comparator 13. A pulse train CLK is applied to the input terminal 12 of the N-stage variable delay circuit 11 (the input terminal of the first-stage in-phase amplification type variable delay circuit 10). Here, it is assumed that the duration of one pulse of the pulse train CLK given to the input terminal 12 and the delay time of the N-stage variable delay circuit 11 are close to each other (the relationship is not greatly different). The other input terminal of the phase comparator 13 is connected to the input terminal 12 of the N-stage variable delay circuit 11, and the pulse train CLK supplied to this input terminal 12 is directly supplied to the phase comparator 13 to perform phase comparison. The phase of the pulse delayed by the N-stage variable delay circuit 11 is compared with the phase of the pulse that is not delayed in the device 13.

The phase comparison result output of the phase comparator 13 is smoothed by the filter 14, and the smoothed phase comparison result output is supplied to the substrate bias generator 15. to generate a bias voltage + V _BP and single V _B N, the board Baiasu voltage + V _B p and - giving each VBN to the substrate electrode 5 and 6 were derived from the phase-amplified variable delay circuit 1 0, the phase It is configured to control the delay time of the amplification type variable delay circuit 10. In this configuration, if the delay amount of the N-stage variable delay circuit 11 fluctuates in a direction to be shortened due to, for example, temperature change, the fluctuation of the delay amount appears in the phase comparison result output of the phase comparator 13. The phase comparison result output is controlled so that the absolute values of the substrate bias voltage + V _BP and 1 V _BN generated from the substrate bias generator 15 increase. By absolute value of the substrate bias voltage + V _B p and one V _BN is controlled in the direction of increasing, the delay time of each phase amplified variable delay circuit 1 0 is controlled in a direction in which a long, original delay time Is returned to.

When the delay time of the N-stage variable delay circuit 11 is shifted in the direction of increasing the delay time, the phase comparison result output of the phase comparator 13 is opposite to the previous case (in the case of shifting in the direction of decreasing the delay time). Polarity, so that the substrate bias generator 15

+ V _BP and is controlled in a direction to decrease the absolute value of the first VBN. Therefore, the change in the substrate bias voltage controls the delay time of the N-stage variable delay circuit 11 to be shortened.

As described above, in the embodiment shown in FIG. 5, since the phase comparison result of the phase comparator 13 is automatically controlled to be always a fixed value, for example, 0, the delay time of the N-stage variable delay circuit 11 is always It will be maintained at a constant value. Therefore, as shown in the figure, each output side of the N common-mode amplification type variable delay circuits 10 constituting the N-stage variable delay circuit 11 is connected to, for example, one input of a corresponding AND gate of the AND gate group G. Connected to the terminal, and through an AND gate group G, the N-stage variable delay circuit 11 constitutes an N-stage in-phase amplification type variable delay circuit 10 so that a delayed signal is extracted between any one of the stages or from the output side. With this configuration, a delay pulse having an arbitrary delay amount can be obtained, and the selected delay time can be maintained at a constant value. In FIG. 5, the other input terminal of each AND gate of the AND gate group G is connected to the control circuit, and only the AND gate to which a control signal is applied from this control circuit is in an operable state. It has been. The output of the AND gate group G is configured to be output to the outside via the OR circuit.

In each of the above embodiments, the variable delay circuit is configured as one CMOS IC. However, the present invention can be applied to a case where the variable delay circuit is configured by an integrated circuit other than the CMOS IC. Needless to say, an effect can be obtained. As described above, according to the present invention, the delay time of the delay circuit is changed by changing the time constant by using the resistance change of the field effect transistor. It can be changed continuously, and minute delay times can be set with good resolution.

Further, by adding an automatic control loop as in the embodiment shown in FIG. 5, automatic control can be performed so that the delay time of the delay circuit is always constant. In addition, a stable and fine delay time can be set. Therefore, there is obtained an advantage that a desired delay time can be obtained with high accuracy, and the delay time can be maintained at a constant value for a long period of time.

Claims

The scope of the claims

1. In a delay circuit configured to cascade a plurality of logic elements formed as a semiconductor integrated circuit and obtain a delay time according to the number of cascade connection stages of these logic elements,

A variable delay circuit, wherein a series circuit including a transistor and a capacitor is connected between at least each stage of the cascaded logic elements and a common potential point.

2. The variable delay circuit according to claim 1, wherein the semiconductor integrated circuit is CMO S IC.

3. The variable delay circuit according to claim 1, wherein the transistor is a MOS field-effect transistor.

4.A p-channel MOS field-effect transistor and an n-channel MOS field-effect transistor are connected in series by connecting their drain electrodes in common, and their gate electrodes are connected in common. The connection point is used as an input terminal, and the connection point between the drain electrode of the p-channel M0S field-effect transistor and the drain electrode of the n-channel M0S field-effect transistor is used as an output terminal to form a polarity-reversed logic circuit. In a delay circuit using a logic circuit as a delay element,

A variable delay circuit, wherein a delay time is controlled by controlling a substrate bias voltage applied to each substrate electrode of the p-channel MOS field-effect transistor and the n-channel MOS field-effect transistor.

5. A delay circuit is formed by cascade-connecting a plurality of polarity-inverted logic circuits each composed of the above-mentioned p-channel MOS field-effect transistor and n-channel MOS field-effect transistor. Substrate noise applied to each substrate electrode of circuit p-channel MOS field-effect transistor and n-channel MOS field-effect transistor 5. The variable delay circuit according to claim 4, wherein the delay time is controlled by controlling a voltage.

6. A two-stage cascaded polarity-inverted logic circuit composed of the p-channel M◦S field-effect transistor and the n-channel M0S field-effect transistor constitutes a common-mode width logic circuit, A plurality of delay circuits are configured by cascade-connecting a plurality of these in-phase amplification logic circuits, and each substrate of a p-channel MOS field-effect transistor and an n-channel M 0 S field-effect transistor of each in-phase amplification type logic circuit. 5. The variable delay circuit according to claim 4, wherein a delay time is controlled by controlling a substrate bias voltage applied to the electrode.

7. The control circuit for automatically controlling a substrate bias voltage applied to each substrate electrode of the p-channel MOS field-effect transistor and the n-channel MOS field-effect transistor of the logic circuit. 7. The variable delay circuit according to any one of claims 1 to 6.