WO1996038773A2

WO1996038773A2 - Integrated primary bus and secondary bus controller with reduced pin count

Info

Publication number: WO1996038773A2
Application number: PCT/US1996/007629
Authority: WO
Inventors: David Scott Weinmann; William Vincent Miller
Original assignee: National Semiconductor Corporation
Priority date: 1995-05-26
Filing date: 1996-05-23
Publication date: 1996-12-05
Also published as: DE69619623D1; EP0775347A3; WO1996038773A3; KR970705084A; EP0775347A2; KR100365169B1; DE69619623T2; EP0775347B1; US5790884A

Abstract

The pin count of an integrated ISA-type bus controller and PCMCIA-type bus controller is reduced by utilizing a single external bus which supports both ISA-type and PCMCIA-type devices, and by placing control over the bus with the controller that controls the device that corresponds with the input address ADD.

Description

INTEGRATED PRIMARY BUS

AND SECONDARY BUS CONTROLLER

WITH REDUCED PIN COUNT

BACKGROUND OF THE INVENTION

1. Field of the Invention.

The present invention relates to a bus controller and, more particularly, to an integrated primary bus and secondary bus controller with a substantially reduced pin count.

2. Description of the Related Art.

A bus interface unit (BIU) controller is a microprocessor peripheral device that controls data transfers across a primary bus to one or more external devices, such as a personal computer memory card industry association (PCMCIA) controller, a floppy-disk drive, or a hard-disk drive.

A PCMCIA controller, in turn, is an external device that controls data transfers across a secondary bus to one or more PCMCIA cards. As is well known, PCMCIA cards are credit-card sized devices which can be plugged into personal computers to provide additional capabilities, such as extended memory or communications support.

FIG. 1 shows a block diagram that illustrates a common primary and secondary bus structure. As shown in FIG. 1, a CPU 12 utilizes a local address bus LABUS and a local data bus LDBUS to communicate with, among other devices, a bus interface unit (BIU) 14 which, in turn, utilizes a primary address bus PABUS and a primary data bus PDBUS to communicate with a PCMCIA controller 16, a floppy-disk drive 18, and a hard-disk drive 20. A secondary address bus SAB US and a secondary data bus SDBUS are then utilized to provide communication between PCMCIA controller 16 and the PCMCIA cards.

Conventionally, BIU 14 and PCMCIA controller 16 are implemented as stand-alone chips because of, among other things, the high pin count that results from integration. For example, BIU 14 typically requires 48 address and data pins (32 address and 16 data) to communicate with CPU 12, and another 48 address and data pins to communicate with the peripheral devices connected to the primary buses PABUS and PDBUS.

Similarly, PCMCIA controller 16 also requires 48 address and data pins to communicate with BIU 14, and another 48 address and data pins to communicate with the PCMCIA cards. If the functionality of BIU 14 and PCMCIA controller 16 is then integrated into a single package, the combined BIU/PCMCIA controller would still require 144 address and data pins (48 to the local buses LABUS and LDBUS, 48 to the primary buses PABUS and PDBUS, and 48 to the secondary buses SABUS and SDBUS).

When combined with the various control pins, the total pin count can easily swell to more than 160 pins. One problem with this high a pin count is that the size of the package must be substantially increased to accommodate the pins which, in turn, substantially increases the cost of production. Thus, there is a need for a technique that allows the BIU and PCMCIA functions to be integrated within a single package that requires significantly fewer pins.

SUMMARY OF THE INVENTION In a conventional microprocessor-based computer system, data transfers across a primary bus are controlled by a bus interface unit (BIU) controller, while data transfers across a secondary bus are controlled by a personal computer memory card industry association (PCMCIA) controller which is attached to the primary bus. The BIU controller and the PCMCIA controller, in turn, each typically require 96 address and data pins to support input and output address and data buses.

In the present invention, a BIU controller and a PCMCIA controller are integrated into a single package which only requires 96 address and data pins. The pin count is reduced by utilizing a single

- 1 - external bus which supports both ISA-type and PCMCIA-type devices, and by placing control over the bus with the controller that controls the device that corresponds with the input address ADD.

An integrated bus controller in accordance with the present invention includes a bus interface unit (BIU) controller that controls data transfers over an external bus when an input address falls within the address space controlled by the BIU controller, and a first plurality of control signals are set to predefined logic states. In addition, a PCMCIA controller also controls data transfers over the external bus when the input address falls within the address space controlled by the PCMCIA controller, and a second plurality of control signals are set to predefined logic states.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principals of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block diagram that illustrates a common primary and secondary bus structure. FIG. 2 is a block diagram that illustrates an integrated bus controller 100 in accordance with the present invention.

FIGs. 3A and 3B are timing diagrams illustrating the operation of controller 100. FIG. 4 is a block diagram illustrating the integration of a processor, a DRAM controller, a BIU controller, and a PCMCIA controller.

DETAILED DESCRIPTION FIG. 2 shows a block diagram of an integrated bus controller 100 in accordance with the present invention. As shown in FIG. 2, controller 100 includes a bus interface unit (BIU) controller 110 that controls data transfers over an external data bus EDBUS when an input address ADD falls within the address space controlled by controller 110, and a first series of control signals are set to predefined logic states. Further, in accordance with the present invention, controller 100 additionally includes a personal computer memory card industry association (PCMCIA) controller 120 that also controls data transfers over the external data bus EDBUS when the input address ADD falls within the address space controlled by controller 120, and a second series of control signals are set to predefined logic states.

As shown in FIG. 2, both BIU controller 110 and PCMCIA controller 120 receive the input address ADD, and output a BIU address BAD and a PCMCIA address PAD, respectively, in response to the input address ADD. In the FIG. 2 embodiment, controller 110 forms the BIU address BAD by passing the input address ADD, while controller 120 forms the PCMCIA address PAD by either passing or remapping the input address ADD. Alternately, controller 110 can also be configured to remap the input address ADD. With respect to the first series of control signals, BIU controller 110 receives a memory/IO signal

M/IO that indicates whether the request is to memory or an I/O device, a data/code signal D/C that indicates whether the request is for data or code, a read/write signal R/W that indicates whether the request is for a read or a write, an address strobe ADS that indicates whether the current input address ADD is valid, and an access signal NDM that indicates whether the request is to a dynamic random- access-memory (DRAM) or another device.

With respect to the second series of control signals, PCMCIA controller 120 receives from BIU controller 110 an internal I/O read strobe πOR, which indicates that data is to be read from an I/O device, an internal I/O write strobe HOW, which indicates that data is to be written to an I/O device, an internal memory read strobe IMR, which indicates that data is to be read from an external memory, and an internal memory write strobe IMW, which indicates that data is to be written to an external memory.

2 - In addition, BIU controller 110 outputs the IIOR, LTOW, IMR, and LMW strobes as a BIU I/O read strobe BIOR, a BIU I/O write strobe BIOW, a BIU memory read strobe BMR, and a BIU memory write strobe BMW. Similarly, PCMCIA controller 120 outputs the IIOR, HOW, IMR, and LMW strobes as a PCMCIA I/O read strobe PIOR, a PCMCIA I/O write strobe PIOW, a PCMCIA memory read strobe PMR, and a PCMCIA memory write strobe PMW.

In operation, the M IO, D/C, and R/W signals are decoded by BIU controller 110 which, in turn, changes the logic state of either the internal I/O read strobe IIOR, the internal I O write strobe HOW, the internal memory read strobe IMR, or the internal memory write strobe IMW, depending on which operation is to be performed. When the logic state of the ADS signal indicates that the input address ADD is valid, and the logic state of the access signal NDM indicates that the request is to a DRAM, controller 100 takes no further action. However, when the logic state of the ADS signal indicates that the input address ADD is valid, and the logic state of the access signal NDM indicates that the request is to a device other than a DRAM, BIU controller 110 outputs the internal strobe IIOR, IIOW, IMR, or IMW identified by the first series of control signals approximately one clock cycle after receiving the address strobe ADS.

FIGs. 3 A and 3B show timing diagrams that illustrate the operation of controller 100. As shown in FIG. 3A, after the rising edge of a first clock pulse, the input address ADD received by BIU controller 1 10 becomes valid on the falling edge of the address strobe ADS.

When the input address ADD becomes valid, BIU controller 110 sets a first select signal SEL1 to a first logic state which, in turn, causes a multiplexer 130 to pass the BIU strobe BIOR, BIOW, BMR, or BMW that corresponds with the internal strobe IIOR, IIOW, IMR, or LMW identified by the first series of control signals as an external strobe IOR, IOW, MR, or MW.

At this point, the changed logic state of the IIOR, IIOW, IMR, or IMW strobe is not output by BIU controller 110. As a result, all of the external strobes IOR, IOW, MR, and MW are set to a logic state that indicates that the address on the bus is invalid.

Similarly, BIU controller 110 also sets the logic state of a second select signal SEL2 to a first logic state which, in turn, causes a multiplexer 140 to pass the BIU address BAD as an external address EADD.

On the rising edge of the second clock pulse, BIU controller 110 checks the logic state of the access signal NDM, and outputs the internal strobe IIOR, IIOW, IMR, or IMW when the access signal NDM indicates that a device other than a DRAM is to be accessed.

In response to the internal strobe IIOR, IIOW, IMR, or IMW, PCMCIA controller 120 determines whether the input address ADD falls within the address space controlled by PCMCIA controller 120. In addition, PCMCIA controller 120 also outputs the PCMCIA strobe PIOR, PIOW, PMR, or PMW that corresponds with the internal strobe IIOR, IIOW, LMR, or IMW identified by the first series of control signals.

If the input address ADD is not within the PCMCIA controlled address space, PCMCIA controller 120 sets a feedback signal FB to a first logic state. On the rising edge of the fourth clock pulse, BIU controller 110 checks the logic state of the feedback signal FB and, when the logic state of the feedback signal FB is in the first logic state, thereby indicating that the input address ADD is not within the address space controlled by PCMCIA controller 120, outputs the internal strobe IIOR, HOW, IMR, or IMW identified by the first series of control signals as the respective BIU strobe BIOR, BIOW, BMR, or BMW. The lowered BIU strobe BIOR, BIOW, BMR, or BMW, in turn, is passed by multiplexer 130, thereby indicating that the BIU address BAD output by multiplexer 140 is valid. On the other hand, as shown in FIG. 3B, when the input address ADD is within the PCMCIA address space, PCMCIA controller 120 sets the feedback signal FB to a second logic state prior to the fourth clock period. On the rising edge of the fourth clock pulse, BIU controller 110 checks the logic state of the feedback signal FB, and changes the logic state of the select signal SEL2 so that multiplexer

140 passes the PCMCIA address PAD as the external address EADD.

In addition, BIU controller 110 changes the logic state of the select signal SEL1 so that, on the rising edge of the fifth clock pulse, multiplexer 130 passes the PCMCIA strobe PIOR, PIOW, PMR, or PMW as the external address strobe IOR, IOW, MR, or MW, thereby indicating that the PCMCIA address PAD output by multiplexer 140 is valid.

In addition, although code is not written to the I/O devices, the logical state of the data/code signal D/C can be utilized to indicate other conditions. Thus, for example, when code is written to an I/O device, BIU controller 110 interprets this logic condition as an interrupt acknowledge and outputs an interrupt acknowledge signal INTA.

In the FIG. 2 embodiment, the internal strobes IIOR, HOW, IMR, W, and INTA output by controller 110 are utilized by both controllers 110 and 120. Alternately, both controllers 110 and 120 can be implemented to decode and output separate address strobes. Similarly, controller 120 can be implemented to decode and output the address strobes for both of the controllers. In addition to the above-described control signals, both BIU controller 110 and PCMCIA controller

120 output one of a series of chip select signals CSl-CSm and one of a series of chip enable signals CEl-CEn, respectively, in response to the input address ADD when the input address ADD falls within the address range controlled by the controller.

Each device connected to the external address bus EAB corresponds with an address range programmed into either controller 110 or controller 120. When controller 110 or controller 120 determine that the input address ADD is within the address space controlled by that controller, controllers 110 and 120 also determine which device corresponds with the input address ADD, and output the chip select signal CS or chip enable signal CE, respectively, that corresponds with the device.

Thus, in the present invention, the number of pins required to support an integrated bus controller are reduced by utilizing a single bus to support both ISA-type devices, as well as PCMCIA-type devices, and by placing control over the bus with the controller that controls the device that corresponds with the input address ADD.

In addition to integrating the functionality of a BIU controller and a PCMCIA controller, the functionality of a dynamic random-access-memory (DRAM) controller can also be integrated with a processor. FIG. 4 shows a block diagram that illustrates the integration of a processor, a DRAM controller, a BIU controller, and a PCMCIA controller.

As shown in FIG. 4, by integrating three controllers with the processor, only a single external address bus and a single external data bus are required to support the combined functionality.

The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following cc— pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER

CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-62700); U.S. patent application Serial No. 08/ , entitled "SERIAL INTERFACE CAPABLE OF OPERATING LN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC1-62800); U.S. patent application Serial No.

08/ , entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS

(DMA) CONTROLLER" (atty. docket no. NSC1-62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC1-63000); U.S. patent application Serial No.

08/ , entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING

MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSC1-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION

SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application

Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC1-63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63500); U.S. patent application

Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A

32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application Serial No.

08/ , entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no.

NSC1-63700); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND

COUNTER" (atty. docket no. NSC 1-63800); U.S. patent application Serial No. 08/ , entitled

"AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC1-63900);

U.S. patent application Serial No. 08/ , entitled "NON-ARITHMETICAL CIRCULAR

BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSCl- OOO); U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION

DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED

DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC1-64200); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC1-64300); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR GENERATING A DEMAND-BASED

GATED CLOCK" (atty. docket no. NSC1-64500); U.S. patent application Serial No. 08/ , entitled "INCREMENTOR/DECREMENTOR" (atty. docket no. NSC1-64700); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC1-64800); U.S. patent application

Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC1-64900);

U.S. patent application Serial No. 08/ , entitled "TWO TIER PREFETCH BUFFER

STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application Serial No. 08/ , entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC1-65100); U.S. patent application Serial No. 08/ , entitled "A PIPELINED

MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no.

NSC1-65200); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND

METHOD FOR EFFICIENT COMPUTATION OF A 486™ MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC1-65700); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application

Serial No. 08/ , entitled "METHOD OF IMPLEMENTLNG FAST 486™

MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC1-65900); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT

PREVENTS THECACHEFROM BEINGREADWHENTHECONTENTS OFTHECACHEARE

INVALID" (atty. docket no. NSC1-66000); U.S. patent application Serial No. 08/ , entitled

"DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application Serial No. 08/ , entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN

COUNT" (atty. docket no. NSC1-66400); U.S. patent application Serial No. 08/ , entitled

"SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC1-66500); U.S. patent application Serial No. 08/ , entitled "CLOCK GENERATION

- 5 - CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application Serial No. 08/ , entitled "CONFIGURABLE

POWER MANAGEMENT SCHEME" (atty. docket no. NSC1-66700); U.S. patent application Serial No.

08/ , entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC1-67000); U.S. patent application Serial No. 08/ , entitled "LIQUID CRYSTAL

DISPLAY (LCD) PROTECTION CIRCUIT" (atty. docket no. NSC1-67100); U.S. patent application

Serial No. 08/ , entitled "IN-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT" (atty. docket no. NSC 1-67400); U.S. patent application Serial No. 08/ , entitled "DISPLAY

CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC1-67500); U.S. patent application Serial No. 08/ , entitled

"INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK

TEST METHOD AND APPARATUS" (atty. docket no. NSC1-68000).

It should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. Thus, it is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims

WHAT IS CLAIMED IS:

1. An integrated primary and secondary bus controller for controlling data transfers over an external data bus, the external data bus supporting both ISA-type and personal computer memory card industry association (PCMCIA) type devices, the bus controller comprising: a first bus controller that controls data transfers over an external bus when an input address falls within the address space controlled by the first bus controller, and a first plurality of control signals are set to predefined logic states; and a second bus controller that controls data transfers over the external bus when the input address falls within the address space controlled by the second bus controller, and a second plurality of control signals are set to predefined logic states.

2. The controller of claim 1 wherein the first and second bus controllers dynamically determine which bus controller is in control of the external bus.

3. The controller of claim 1 wherein transfer of control of the external bus from the first bus controller to the second bus controller guarantees proper access timing.