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WO1996035229A1 - Procede de reduction localisee de la duree de vie - Google Patents

Procede de reduction localisee de la duree de vie Download PDF

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Publication number
WO1996035229A1
WO1996035229A1 PCT/GB1996/001079 GB9601079W WO9635229A1 WO 1996035229 A1 WO1996035229 A1 WO 1996035229A1 GB 9601079 W GB9601079 W GB 9601079W WO 9635229 A1 WO9635229 A1 WO 9635229A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
front surface
ions
implanted
regions
Prior art date
Application number
PCT/GB1996/001079
Other languages
English (en)
Inventor
David James Chivers
Raymond Izzard
Original Assignee
Aea Technology Plc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Aea Technology Plc filed Critical Aea Technology Plc
Priority to AU55102/96A priority Critical patent/AU5510296A/en
Publication of WO1996035229A1 publication Critical patent/WO1996035229A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/221—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities of killers

Definitions

  • the present invention relates to the production of semiconductor devices, and in particular, to the production of semiconductor devices including switching elements.
  • the minority carrier lifetime can be controlled by doping the semiconductor material out of which the devices are made so as to provide traps for the minority charge carriers in the semiconductor material.
  • suitable dopants are gold or platinum.
  • the dose levels required are much lower than those used in the fabrication of the switching and other circuit elements incorporated in the devices and conventionally the doping is achieved by depositing a coating of the noble metal on the back surface of the silicon wafer upon which the switching and other circuit elements are formed, removing the majority of the coating and thermally diffusing the remaining noble metal through the silicon wafer. This process is neither very repeatable nor easy to control.
  • An alternative method is described in a paper "Control of Minority Carrier Lifetime by Gold Implantation in Semiconductor Devices" by S. Coffa et al. J. Electrochem Soc. Vol 136 No 7 July 1989 pp 2073-2075.
  • gold is introduced into silicon wafers by means of ion implantation, which is far more controllable and well-defined than the previously described process.
  • the gold is implanted into the back face of the wafer and diffused thermally through the wafer to the front surface where it is required.
  • the gold permeates the whole of the silicon wafer and degrades the electrical properties of the silicon in regions where a short minority carrier lifetime is not necessarily required and may, in fact, be harmful.
  • a method of manufacturing a semiconductor device including a substrate having a front surface region in which electrical elements are formed wherein there are included the operations of implanting into selected regions of the front surface of the substrate ions of a material adapted to reduce the minority carrier lifetime of the substrate material and subjecting the front surface of the substrate to a pulse of thermal energy sufficient to distribute the implanted ions throughout the selected regions of the substrate but insufficient to cause deleterious diffusion of the implanted material into other regions of the substrate.
  • Suitable materials for reducing the minority carrier lifetime in silicon are the noble metals, particularly gold, and suitable ion doses are in the region of 10 11 to
  • the amount of thermal energy in the thermal pulse should not exceed 500° minutes, with a maximum temperature of about 1000°C.
  • a portion of a wafer 1 of semiconductor material has a front surface 2 and a back surface 3.
  • the front surface 2 are a number of differently doped regions 4 which form components of electrical circuit elements in the normal way.
  • the regions 4 are separated by other regions 5 in which it is desired to reduce the minority carrier lifetime of the material out of which the substrate 1 is made.
  • the front surface 2 of the wafer 1 is cleaned by methods well-known in the semiconductor art and which it is not thought necessary to describe.
  • stage (b) those regions of the front surface 2 of the substrate 1 in which it is not desired that the minority carrier lifetime of the substrate 1 should be reduced, are protected by means of a mask 6 formed on the front surface 2 of the substrate 1 by photolithographic techniques, which again are well known in the semiconductor art, and are not described herein.
  • the front surface 2 of the wafer 1 is subjected to bombardment with a beam 7 of gold ions until a desired ion dose has been implanted in the exposed regions 5 of the surface 2 of the substrate 1.
  • the ion dose is selected according to the minority carrier lifetime required, but normally the ion dose is in the range 10 H - 10 14 ions/cm 2 .
  • a suitable ion energy is of the order of 80KeV.
  • the thermal pulse is applied to front surface 2 of the substrate 1 is by a pulsed beam of radiant energy, which may be from a laser. However, the entire wafer may be heated in a muffle furnace if preferred. Finally, the mask 6 is removed, stage (e) .
  • the invention has been described specifically with reference to the use of noble metals as a means of controlling the minority carrier lifetime in silicon as a substrate material, it is applicable to other substrate materials, such as germanium.
  • other elements can be used to control the minority carrier lifetime; in general the lifetime control element can be selected from any element other than those which are being used to provide the desired changes in the electrical properties of a substrate material required to produce the semi-conductor devices under consideration.
  • suitable elements are the transition elements, or light species such as protons.
  • a selection criterion is that the ions should be capable of being implanted effectively with energies no greater than approximately 100 KeV.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thyristors (AREA)
  • Bipolar Transistors (AREA)

Abstract

Procédé permettant de réduire la durée de vie minoritaire de certaines zones d'un dispositif semi-conducteur dans lequel les surfaces avant de ces zones sont implantées avec des ions, tels que des métaux précieux, qui ont la propriété de réduire la durée de vie des porteurs minoritaires, lesdits ions étant incités à migrer sur une courte distance dans les zones implantées lorsqu'on applique une impulsion d'énergie thermique sur la surface avant du dispositif.
PCT/GB1996/001079 1995-05-06 1996-05-07 Procede de reduction localisee de la duree de vie WO1996035229A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU55102/96A AU5510296A (en) 1995-05-06 1996-05-07 Process for the localized reduction of the lifetime

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9509301.9 1995-05-06
GBGB9509301.9A GB9509301D0 (en) 1995-05-06 1995-05-06 An improved process for the production of semi-conductor devices

Publications (1)

Publication Number Publication Date
WO1996035229A1 true WO1996035229A1 (fr) 1996-11-07

Family

ID=10774133

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1996/001079 WO1996035229A1 (fr) 1995-05-06 1996-05-07 Procede de reduction localisee de la duree de vie

Country Status (3)

Country Link
AU (1) AU5510296A (fr)
GB (1) GB9509301D0 (fr)
WO (1) WO1996035229A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9209027B1 (en) 2014-08-14 2015-12-08 Infineon Technologies Ag Adjusting the charge carrier lifetime in a bipolar semiconductor device
US9349799B2 (en) 2014-08-14 2016-05-24 Infineon Technologies Ag Adjusting the charge carrier lifetime in a bipolar semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2241141A1 (fr) * 1973-08-16 1975-03-14 Licentia Gmbh
EP0506170A1 (fr) * 1991-03-28 1992-09-30 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication
WO1993005535A1 (fr) * 1991-08-28 1993-03-18 Advanced Power Technology, Inc. Procede et dispositif de la fabrication de transistors a grille isolee comportant un controle de la duree de vie du platine

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2241141A1 (fr) * 1973-08-16 1975-03-14 Licentia Gmbh
EP0506170A1 (fr) * 1991-03-28 1992-09-30 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Structure integrée comprenant un dispositif bipolaire de puissance à haute densité de courant et une diode rapide et son procédé de fabrication
WO1993005535A1 (fr) * 1991-08-28 1993-03-18 Advanced Power Technology, Inc. Procede et dispositif de la fabrication de transistors a grille isolee comportant un controle de la duree de vie du platine

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"AN IMPROVED METHOD OF MAKING HIGH SPEED SWITCHING DEVICES", RESEARCH DISCLOSURE, no. 291, 1 July 1988 (1988-07-01), pages 463, XP000074995 *
CATANIA M F ET AL: "OPTIMIZATION OF THE TRADEOFF BETWEEN SWITCHING SPEED OF THE INTERNAL DIODE AND ON-RESISTANCE IN GOLD- AND PLATINUM-IMPLANTED POWER METAL-OXIDE-SEMICONDUCTOR DEVICES", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 39, no. 12, 1 December 1992 (1992-12-01), pages 2745 - 2749, XP000323175 *
COFFA S ET AL: "Diffusion and lifetime engineering in silicon", ION IMPLANTATION TECHNOLOGY. NINTH INTERNATIONAL CONFERENCE, GAINESVILLE, FL, USA, 20-24 SEPT. 1992, vol. B74, no. 1-2, ISSN 0168-583X, NUCLEAR INSTRUMENTS & METHODS IN PHYSICS RESEARCH, SECTION B (BEAM INTERACTIONS WITH MATERIALS AND ATOMS), APRIL 1993, NETHERLANDS, pages 47 - 52, XP002010589 *
COFFA S ET AL: "Three-dimensional concentration profiles of hybrid diffusers in crystalline silicon", JOURNAL OF APPLIED PHYSICS, 1 JULY 1993, USA, vol. 74, no. 1, ISSN 0021-8979, pages 195 - 200, XP000465561 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9209027B1 (en) 2014-08-14 2015-12-08 Infineon Technologies Ag Adjusting the charge carrier lifetime in a bipolar semiconductor device
US9349799B2 (en) 2014-08-14 2016-05-24 Infineon Technologies Ag Adjusting the charge carrier lifetime in a bipolar semiconductor device

Also Published As

Publication number Publication date
GB9509301D0 (en) 1995-06-28
AU5510296A (en) 1996-11-21

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