WO1996030951A1

WO1996030951A1 - Light emitters and detectors

Info

Publication number: WO1996030951A1
Application number: PCT/GB1996/000767
Authority: WO
Inventors: Yin Sheng Tang; Clivia Marfa Sotomayor-Torres
Original assignee: The University Court Of The University Of Glasgow
Priority date: 1995-03-31
Filing date: 1996-03-29
Publication date: 1996-10-03
Also published as: GB9506735D0

Abstract

A silicon compatible light emitting or detecting device comprises a substrate (3) and a multiplicity of quantum dots (2) provided on the substrate. Each quantum dot (2) comprises a plurality of alternate silicon and silicon-germanium layers (4, 5) and has a transverse cross-sectional area of less than 8000 nm2. The regions between the quantum dots (2) are filled with a dielectric material (6) and respective electrical connections (7, 8) are made to the substrate and upper surfaces of the dots (2) to enable electrical current to flow through the dots (2).

Description

LIGHT EMITTERS AND DETECTORS

The present invention relates to light emitting and detecting devices and in particular to light emitting and detecting devices fabricated from silicon/silicon-germanium material.

In recent years, it has become apparent that there is a need for silicon-based active and passive optical devices such as light emitters and detectors which are capable of being integrated into silicon-integrated circuits. This need is driven by the increasing requirements for miniaturisation, complexity and reduced cost.

In an attempt to address this need, attention has been directed in recent years to silicon-germanium (Si/Ge) strained layer superlattices (SLS) which comprise alternating layers of silicon and germanium, each layer being only a few atoms thick. These layers are generally grown on a silicon substrate using molecular beam epitaxy (MBE) although other growth techniques are known. The principle behind SLS research is the proposition that such multiple strained layers convert the indirect bandgap of the silicon band structure to a direct bandgap via 'Brillouin zone folding' . A review of the properties of silicon-germanium superlattices is given in "Ultra thin Si_mGe_n strained layer superlattices - a step towards Si opto-electronics", H Presting et al, Se icond.Sci, Technol.7(1992) 1127-1148.

EP-A1-0535293 considers the fabrication of multiple quantum wire or dot structures in Si/Ge strained layer superlattice material but there is no disclosure of structures providing practical optical devices.

Attempts to fabricate silicon-germanium devices which are capable of acting as light emitters or detectors have to date been unsuccessful because, in practice, the silicon and germanium layers remain substantially indirect bandgap materials exhibiting poor light emission.

An alternative approach to producing a silicon compatible optical device is disclosed in US 5,293,050 which describes the provision of a multiplicity of germanium dots embedded in silicon dioxide and sandwiched between a pair of doped silicon layers. There is no indication of the technical or commercial success of the proposed design.

Another attempt to fabricate such devices has been based on porous silicon, that is silicon which has been immersed in acid to create channels or tunnels therein. However, the size and shape of the channels/tunnels is uncontrollable leading to non-reproducible structures.

This means that the emission wavelength of such structures is also not controllable. In addition, difficulties have been encountered in making metal contacts with the silicon; metal tends to diffuse resulting in unstable optical and electrical properties with time and also limited device lifetimes.

It is an object: of the present invention to overcome or at least mitigate the problems of light emitting and detecting devices currently used in combination with silicon based components. Thus it is an object of the present invention to provide light detectors and emitters which are compatible with conventional silicon based integrated circuit designs and, in particular, to provide such a device which can be integrated onto the same substrate as conventional silicon-based devices.

It is also an object of the present invention to provide a silicon based optical device which can be used at light wavelengths between lμm and 1.6μm.

It is a further object of the present invention to enable the selection of device operating wavelength, or wavelength range, by appropriately selecting the material composition of the device.

According to a first aspect of the present invention there is provided a silicon compatible light emitting or detecting device comprising a substrate, a multiplicity of quantum dots provided on the substrate and each comprising a plurality of alternate silicon and silicon-germanium layers, each quantum dot having a transverse cross- sectional area of less than 8,000nm^:, and respective electrical connections to the substrate and upper regions of the dots to enable electrical current to flow through the dots.

The plurality of layers constitute strained layer superlattice (SLS) material which during manufacturing gives rise to a number of quantum dots each of which is capable of converting light into electric current or vice versa. By varying the relative proportions of silicon and germanium in the silicon-germanium layer the operating wavelength, or wavelength range, of the device may be tuned. The silicon-germanium composition is Si,._xGe. where X is between 0.05 and 1.00 (5% to 100%). When X = 100% the layer is pure germanium.

Preferably, the transverse cross-sectional area of each quantum dot is greater than 200nm^:. More preferably, the transverse cross-sectional area is greater than 700nm², for example 2,000nm^** for dots about 50nm in diameter. Preferably, the dots have the shape of a circular cylinder having a height to diameter ratio of at least 1:1, where the diameter is between 10 and lOOn , e.g. 50nm. Preferably, the device comprises at least 10-15 silicon layers alternating with 10-15 silicon-germanium layers. Preferably, each layer has a thickness of about 2-10nm.

Preferably, the silicon-germanium layers have a composition which is 70% silicon and 30% germanium.

Preferably, the substrate is silicon and the base layer of the quantum dots is a silicon buffer or a graded silicon-germanium buffer, e.g. 200nm thick. Conveniently, the substrate is heavily doped P-type (Boron, Antimony) or N-type (Phosphorous) material.

In a preferred embodiment of the above first aspect of the present invention, a support material, for example polyimide, silicon dioxide, or silicon nitride, is disposed between the dots of the array. The support material has a dielectric constant smaller than that of the superlattice structure and is substantially electrically insulating so that electric current present within the quantum dots is substantially confined therein. The dielectric support material provides a mechanical support for an electrode layer making electrical contact with the upper surfaces of the quantum dots. In the case of silicon dioxide or silicon nitride, the support material is preferably deposited so as to have a substantially stress free configuration. According to a second aspect of the present invention, there is provided a method of fabricating a silicon compatible light emitting or detecting device, the method comprising the steps of: providing a plurality of alternate layers of silicon and silicon-germanium on a support, said alternate layers constituting a strained layer superlattice; defining on the exposed surface of the alternate layers an etch mask which leaves uncovered areas of the superlattice which are to be removed; etching through the exposed areas of the superlattice substantially down to the support to define an array of quantum dots; and making respective electrical connections to the support and to upper regions of the quantum dots to enable electric current to flow through the quantum dots.

Preferably, the plurality of alternate layers of silicon and silicon-germanium are grown using molecular beam epitaxy or metal-organic chemical vapour deposition (MOCVD) . Preferably, the support comprises a buffer layer grown on a semiconductor substrate.

Preferably, the method of the above second aspect of the present invention comprises the step of filling the spaces between the quantum dots with a dielectric support material. Where the provision of this material leads to the upper surfaces of the dots being covered by the material, the method may comprise the further step of etching away some of the dielectric material to expose an upper surface or end face of each of the dots to which electrical connections may be made, e.g. by evaporating a metal onto the upper surface of the structure. Preferably, the step of defining an etch mask comprises depositing a resist on the surface of the superlattice, which resist can be exposed using electromagnetic radiation, e.g x-rays or an electron beam. This step further comprises exposing an appropriate pattern in the resist using electromagnetic radiation or an electron beam and developing the sample to remove exposed (in the case of a positive resist) or unexposed (in the case of a negative resist) areas.

In a preferred embodiment of the method of the present invention, the resist is an electron beam sensitive resist and areas to be exposed are exposed to an electron beam exposure of between 1,000 and 2,000 μC/ cm², for a 50KeV beam and between 2,000 and 4,000μC/cm² for a lOOKeV beam. The electron beam resist is developed using an iso-propyl alcohol/mixture MiBK (iso-butyl-methylketone, e.g. in a 3:1 ratio mixture for 30 seconds. The etch mask may be defined by evaporating a suitable metal (metal alloy) , for example NiChrome (NiCr) , at a thickness of between 10 and 50nm, preferably 30nm, over the developed resist and 'lifting- off the NiChrome from the unwanted areas using acetone.

Preferably, the step of etching the superlattice material to define the quantum dots comprises using reactive ion etching. A preferred etching gas is silicon tetrachloride (SiCl.) . Suitable etch conditions are an RF power of 10 to 50 watts (at 13.56MHz), a gas flow rate of 2 to 3sccm, a pressure of 3 to 15mTorr, and a DC bias of 50 to 300volts, to give an etch rate of 20 to 25nm/min for a planar chamber etching system.

For a better understanding of the present invention and in order to show how the same may be carried into effect an embodiment of the invention will now be described with reference to the accompanying drawings, in which: Figure 1 is a diagrammatic representation of a light emitting device embodying the present invention;

Figure 2 shows an enlarged cross-section through a part of the device of Figure 1; Figures 3 (a) to (f) shows the main fabrication steps involved in producing the light emitting device shown in Figure 1;

Figure 4 shows a typical photoluminescence (PL) spectra for an array of 60nm diameter pure germanium quantum dots and for a sample of 'as grown' material;

Figure 5 is a graph of photoluminescence intensity of a 50nm dot array for a Si-Si_0f,Ge₀₂ composition;

Figure 6 shows the relationship between quantum dot diameter and normalised peak PL intensity for different Si- Si,._xGe_ superlattices;

Figure 7 is a graph of electroluminescence versus wavelength and energy for a Si-Si_tl7Ge₀₃ superlattice p-i-n quantum dot diode showing temperature dependence; and

Figure 8 shows the photoluminescence vs stress characteristic for a light emitting device of the type shown in Figures 1 and 2 where device dots are in-filled with silicon nitride;

There is illustrated in Figure 1 a light emitting device 1 comprising twenty discrete quantum dot structures 2 fabricated on a heavily N-doped (phosphorous) (>10¹⁸cm^'3) silicon substrate 3 which is oriented in the <100> direction. Each dot is in the shape of a circular cylinder having a diameter of 60nm and a height of 250nm. As shown in Figure 2 (where the vertical dimension of the dots is exaggerated for clarity) , the dots each comprise a plurality of undoped silicon layers 4 alternating with a plurality of silicon-germanium layers 5, where the silicon- germanium composition is Si_t)7Ge„,. In all there are 15 silicon layers and 15 silicon-germanium layers (not all being shown in Figure 2) , where each layer has a thickness of 6nm giving a total dot height of 180nm, which together form a strained layer superlattice quantum dot. An additional heavily doped p-type silicon layer 12 (e.g. 43nm thick) is provided on top of the quantum dots. This top layer enables electrical contacts to be formed with the dots. In practice, a practical quantum dot array will comprise many more than 12 quantum dots to produce sufficient electroluminescence for the intended application, although the dots should not generally occupy more than 25% of the surface of the device. The regions between the dots are in-filled with a polyimide dielectric material 6 which serves to isolate electrically the dots from one another forming a composite matrix. The dielectric material also provides additional mechanical strength to the device. Electrodes 7, 8 are formed on both the upper surfaces of the composite matrix and the lower surface of the substrate to allow electric current to flow through the dots when a potential is applied across the electrodes or to receive electrical current generated within the dots in response to light radiation incident on the dots.

The quantum dots are structures which are sized to confine electron quantum mechanical-type waves. The restriction of the trapped waves in all three dimensions results in changes in the band structure of the dot material which in turn results in changes in the optical properties of the material as will be described hereinbelow.

The process required to fabricate a device of the type shown in Figures 1 and 2, having dot diameters of 60nm, will now be described with reference to Figure 3. The process begins with a chip comprising an N-doped (Phosphorous) <100> oriented silicon substrate 3 on which has been grown a silicon buffer layer 9 followed by a strained layer superlattice comprising 15 silicon layers 4 alternating with 15 silicon-germanium layers 5 (Si_υ7Ge₀₃) , each layer being 6nm thick as described above. The material used to obtain the results described hereinbelow was provided by the University of Linkδping, Sweden (see Journal of Crystal Growth, 1995, Vol. 157, No 1-4, pp. 285- 294 and Journal of Crystal Growth, 1995, Vol. 157, No 1-4, pp 242-247) . An alternative superlattice material has alternating layers each 3nm thick. As described above, a further p-type silicon layer 12 is provided on top of the supperlattive structure.

The sample is first cleaned and an electron beam resist 10 is coated onto the upper surface of the strained layer superlattice by, for example, spinning. Typically, the electron beam resist is PMMA (polymethylmethacrylate) which comprises 2.5% BDH spun on as a first layer (5krpm for 60 seconds and baked at 180°C for 2hrs) followed by a second layer of 2.5% ELV (5krpm and baked for 2hrs or longer, e.g. overnight) to produce a resist layer 64nm thick. An alternative electron beam resist is HRN.

Following baking of the electron beam resist 10, areas of the resist overlying regions which are not to be etched are exposed by an electron beam. A suitable apparatus for carrying out this exposure is a modified scanning electron microscope or an electron (Phillips) Beamwriter. The electron beam exposure is set to 2000μC/cm² with a beam energy of 50KeV.

The exposed resist is then removed by developing the sample in iso-propyl alcohol (IPA) mixed with MiBK in a ratio of 3:1, for 30 seconds [Figure 3(b)]. The sample is then placed in an evacuated chamber at a pressure of less than 2 x 10^"° Torr and a 10 to 30nm layer of NiChrome 11 (90% Ni) is evaporated onto the upper surface of the sample [Figure 3 (c) ] .

In order to produce the etch mask, the remaining resist on the upper surface of the sample is removed by soaking the sample in acetone for a suitable period of time. The dissolution of the resist causes the NiChrome overlying the resist to be lifted-off, leaving only those areas of NiChrome which are directly adhered to the upper surface of the strained layer superlattice as shown in Figure 3(d) .

In order to define the quantum dots in the strained layer superlattice, the lattice is etched using a reactive ion etching machine, for example [PlasmaTech RIE80, RF frequency of 13.6MHz]. A preferred etch gas is silicon tetrachloride (SiCl₄) and suitable etch parameters are a radio frequency power of 30 watts, a gas flow rate of 2.25sccm, a pressure of 10.8mTorr and a DC bias voltage of 190 volts, giving an etch rate of 25nm/min. Etching under these conditions is carried out for a time of 10 minutes in order to ensure that the sample is etched through the strained layer superlattice to the silicon buffer layer.

Whilst a high etch rate is desirable in order to reduce fabrication time, too high a rate involves a higher RF power which will inflict damage on the dots and will reduce, or kill, optical emission.

Following the reactive ion etch, the NiChrome mask is removed using hydrochloric acid (>40% for 3 hours) to create the structure shown in Figure 3(e). The next step in the process is to in-fill the spaces between the quantum dots with a dielectric material which is both electrically insulating and which has a dielectric constant smaller than those of the quantum dot materials. The dielectric material should also have a lattice constant and a thermal expansion coefficient close to those of the Si/Si-Ge layers so as to minimise the external stress applied to the superlattice. Suitable dielectric materials include silicon dioxide (SiO_:) , silicon nitride (Si,N₄) and polyimide. Whilst SiO and Si,N may be deposited using plasma assisted chemical vapour deposition (see below) , polyimide is generally spun onto the surface of the device to an appropriate thickness and subsequently cured. Following deposition, the dielectric is etched back to expose the upper surfaces of the dots. In order to enable electrical connections to be made to the dots, a layer of indium tin oxide (ITO) 7 is grown on the surface of the device (ITO being both electrically conductive and optically transparent) and a layer of aluminium 8 is deposited on the bottom surface of the substrate to create the structure show in Figure 3(f). As an alternative to ITO, a thin layer of Ni-chrome may be evaporated onto the upper surface of the device to provide electrical contact to the upper surfaces of the dots.

To achieve light emission from arrays of 60nm dots fabricated as described above, fabricated samples of Si-Ge₁₀₀ composition were subjected to photoluminescence (PL) spectroscopy at 4K and at an excitation power (I„) density of 0.5 watts/cm². The resulting spectra are shown in Figure 4 where the spectrum (a) for the 60nm dot array is dominated by a peak (1) at an energy of about 0.77eV and the spectrum (b) for the MBE as-grown (control) material also has a peak of about 0.76-0.77eV.

Comparing spectra (a) and (b) , it can be seen that, under the same excitation power, the intensity of peak 1 has increased by several orders of magnitude for the quantum dot sample, being comparable with the optical emission strength of direct bandgap III-V compounds such as undoped GaAs under similar excitation conditions.

The PL peak 1 in Figure 4 spectrum (a) has a width of 0.05eV and arises from strongly localized excitons in the zero-dimensional (0D) structures. Similarly, Figure 5 spectrum (a) shows a graph of the photoluminescence (PL) versus wavelength (nm) of a 50nm quantum dot array made from a Si-Si„„ Ge ₂ single quantum well grown on an undoped Si substrate under the same conditions as the material from which the data shown in Figure 4 was obtained (4K, I„ 0.5w/cm²). In this case it will be seen that the PL spectrum for the dot array is also some orders of magnitude greater than the MBE as-grown material with a peak (1) at a wavelength of 1150nm corresponding to l.08eV. This peak also corresponds to the exciton no-phonon emission (X_NP) . In contrast the PL spectrum of the as-grown material (spectrum (b) in Figure 5) has a peak for X_sv at 1180nm (1.05eV) and a peak which is almost as large for X_τo (transverse optical phonon assisted excition) at 1250nm (l.OOeV). Thus, it will be seen that the photoluminescence intensity of the Si-Si₀₈Ge₀₂50nm dots provides a significantly greater value than the as-grown material with a single controllable and well defined peak at 1150nm.

Figure 6 shows the relationship between dot diameter (nm) and the normalised peak 1 emission intensity (arbitrary units) on logarithmic axes for different Si-Ge compositions. It will be seen that the relationship is substantially independent for the three compositions shown. The peak intensity increases slowly by one order of magnitude with reducing dot size to about 200nm. Further reducing the dot diameter to about 60-l00nm causes a sudden and pronounced additional increase in intensity of up to an order of magnitude. ₍ When the dot sizes are less than 60nm diameter, the peak intensity is increased by more than two orders of magnitude compared to dot diameters of 200nm or more. The quantum efficiency is correspondingly enhanced by more than two orders of magnitude in going from the as- grown material to the quantum dot arrays.

Figure 7 depicts a graph of Electroluminescence (EL) versus wavelength (nm) of one of three quantum dot p-i-n diodes from a Si-Si_t)7Ge ₃ superlattice which were measured at temperatures between 4K and 293K (room temperature) by injecting a current of lpA/50nm dot. The EL current injecting threshold for all three devices was 0.1pA/50nm dot (5mA/cm²) . It will be seen that at 4K, as with Figures 4,5, there is a sharp peak at about 1200nm and 1.05eV with the EL magnitude falling slightly with increasing temperature until room temperature where the emission wavelength increases to I300nm at 0.95eV. This is very advantageous because the recognised coupling wavelengths for low band loss fibre-optic communications are 1.31 and 1.55μm. The composition can be tuned so that the PL or EL is at one of these wavelengths or any other desired wavelength between 1.0 and 1.6μm. As has been stated above, one alternative to polyimide as an in-fill dielectric material is silicon nitride. Indeed, experimental results have shown that silicon nitride is superior to polyimide providing that the characteristics of the nitride layer are optimised. Figure 8 shows the PL intensity vs stress (in the nitride layer) characteristic for devices of the type shown in Figures 1 and 2 where the in-fill dielectric material is silicon nitride. It can be seen that the PL intensity is a maximum when the silicon nitride is substantially stress free.

It has been found that when using stress-free silicon nitride, the leakage current from the dots into the dielectric in-fill is substantially reduced in comparison to that which arises when the dielectric is polyimide. High levels of leakage current results in a charge build-up within the dielectric which in turn result in instabilities in the level of light output by the device and even the complete cessation of light emission activity. It is believed that the relatively poor results obtained with polyimide are due to the poor quality and 'charging traps' of the of the polyimide layer around the dots. In contrast, the generally high quality and uniformity of silicon nitride films, and in particular of silicon nitride films deposited by plasma enhanced chemical vapour deposition (PECVD) , results in much lower levels of leakage current and consequential improvements in the quality of light output.

The control of stress in PECVD silicon nitride films has previously been considered in technical publications produced by Plasma-Ther . Inc, St. Petersburgh, USA (see for example 'The Process', issue No.l, March 1995 issued by Plasma-Therm Inc) . The process involves the addition of helium to the deposition chamber, where the level of helium introduced determines the stress in the film. An appropriate level of helium is selected to obtain zero stress.

In order to fabricate devices with a silicon nitride in-fill layer, the process described above with reference to Figure 3 is modified by depositing a layer of silicon nitride onto the intermediate device of Figure 3(e) using PECVD. The process uses an RF frequency of 13.56MHZ, RF power of 18 to 23W, gas flows of SiH₄ at lOsccm, NH₃ at 44sccm, N_: at 25.5sccm and He at 144.5sccm (total flow 224sccm) , and a temperature of 300°C.

Possible alternatives to silicon nitride, and which enable the production of stress free in-fill layers, are silicon oxide and titanium oxide. Other alternatives include boron oxide and Lang uir-Blodgett films.

It will be apparent to the skilled person that various modifications may be made to the above described embodiment within the scope of the present invention. For example, the dots may have cross-sections other than circular, e.g. square or hexagonal, providing that the transverse cross- sectional area meets the above requirements. The sidewalls of the dots may deviate from the vertical, for example the dots may be frustoconical in shape. The number of layers in the quantum dots may vary and may be as few as three, i.e. one silicon-germanium layer sandwiched between two silicon layers.

The device structure described above may be used to provide a light detector, where light photons impinging on the dots are converted into electric current flowing between the top and the bottom electrodes.

Claims

CLAIMS :

1. A silicon compatible light emitting or detecting device comprising a substrate, a multiplicity of quantum dots provided on the substrate and each comprising a plurality of alternate silicon and silicon-germanium layers, each quantum dot having a transverse cross- sectional area of less than 8,OOOnm², and there being respective electrical connections to the substrate and upper regions of the dots to enable electrical current to flow through the dots.

2. A device according to claim 1, wherein the transverse cross-sectional area of each quantum dot is greater than 200nm².

3. A device according to claim 2, wherein the transverse cross-sectional area of each quantum dot is greater than 700nm².

4. A device according to claim 1, wherein the quantum dots are circular cylinders having a height to diameter ratio of at least 1:1 and a diameter of between 10 and lOOnm.

5. A device according to any one of the preceding claims, wherein the quantum dots each comprise at least 10 silicon layers alternating with 10 silicon-germanium layers.

6. A device according to any one of the preceding claims, wherein each said layer has a thickness of between 2 and lOnm.

7. A device according to any one of the preceding claims, wherein the silicon-germanium layers have a composition which is substantially 70% silicon and 30% germanium.

8. A device according to any one of the preceding claims, wherein the substrate is silicon and the base layer of the quantum dots is a silicon buffer or a graded silicon- germanium buffer.

9. A device according to any one of the preceding claims, wherein a support material is disposed between the quantum dots, the support material having a dielectric constant smaller than that of the superlattice structure and being substantially an electrical insulator, so that electric current and light present within the quantum dots is substantially confined therein.

10. A device according to claim 9, wherein the support material is silicon nitride or silicon oxide having a substantially stress free configuration.

11. A device according to claim 9, wherein the support material is polyimide.

12. A method of fabricating a silicon compatible light emitting or detecting device, the method comprising the steps of: providing a plurality of alternate layers of silicon and silicon-germanium on a support, said alternate layers constituting a strained layer superlattice; defining on the exposed surface of the alternate layers an etch mask which leaves uncovered areas of the superlattice which are to be removed; etching through the exposed areas of the superlattice substantially down to the support to define an array of quantum dots; and making respective electrical connections to the support and to upper regions of the quantum dots to enable electric current to flow through the quantum dots.

13. A method according to claim 11 and comprising the step of filling the spaces between the quantum dots with a dielectric support material.

14. A method according to claim 12 or 13 wherein the spaces between the quantum dots are filled with silicon nitride or silicon oxide deposited to have a substantially stress free configuration.

15. A method according to claim 13 or 14 and comprising the step of etching away some of the dielectric material to expose an upper surface or end face of each of the dots to which electrical connections may be made.