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WO1996028848A1 - Circuit de dispositif a faible brouillage electromagnetique et sa structure - Google Patents

Circuit de dispositif a faible brouillage electromagnetique et sa structure Download PDF

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Publication number
WO1996028848A1
WO1996028848A1 PCT/JP1995/000431 JP9500431W WO9628848A1 WO 1996028848 A1 WO1996028848 A1 WO 1996028848A1 JP 9500431 W JP9500431 W JP 9500431W WO 9628848 A1 WO9628848 A1 WO 9628848A1
Authority
WO
WIPO (PCT)
Prior art keywords
pad
power supply
circuit
bypass capacitor
layer
Prior art date
Application number
PCT/JP1995/000431
Other languages
English (en)
Japanese (ja)
Inventor
Yutaka Akiba
Kazuhiko Horikoshi
Toshiyuki Arai
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP52744596A priority Critical patent/JP3909086B2/ja
Priority to PCT/JP1995/000431 priority patent/WO1996028848A1/fr
Publication of WO1996028848A1 publication Critical patent/WO1996028848A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to an EMC-compatible slave device, which is increasingly important as the speed and density of ICs and LSI elements and circuits increase, and particularly relates to a device, a circuit board, and a device that require a means for suppressing unnecessary radiation noise.
  • EMC-compatible slave device which is increasingly important as the speed and density of ICs and LSI elements and circuits increase, and particularly relates to a device, a circuit board, and a device that require a means for suppressing unnecessary radiation noise.
  • a bypass capacitor with good frequency characteristics is inserted between the power supply terminal (pad) and ground terminal (pad) of LSI devices, etc., which are usually sources of noise, in order to suppress unnecessary radiation.
  • LSI devices etc.
  • When connecting a capacitor outside the LSI even if the capacitance of the bypass capacitor is sufficiently large, the current loop from the semiconductor chip to the package lead is large, so that unnecessary width radiation is large, and one measure is taken. There is a limit.
  • Japanese Patent Application Laid-Open No. 5-265757 discloses a method in which a bypass capacitor is built in an LSI to reduce the length (current length) of a current loop.
  • the wood invention converts the range variation (AC component) of the power supply pad with respect to the ground pad at the time of switching of an LSI element or the like into joule heat without using EMI countermeasure parts, and provides The goal is to provide a low EMI device that effectively suppresses unnecessary radiation while realizing the same. Disclosure of the invention
  • the present invention realizes high-density mounting by lowering the Q value of a bypass capacitor by equivalently connecting a bypass capacitor formed on the active surface of an LSI device (element) and a resistor in parallel. Heat fluctuation and absorption of potential fluctuations generated between the power supply pad and ground pad are suppressed by suppressing unnecessary radiation.
  • a circuit in which the second bypass capacitor C 2 and the resistor R are connected in series is connected to the impedance of the second bypass capacitor IZ c 2
  • for a required frequency range ( ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ 2). ( 1 ⁇ ⁇ C 2) is made sufficiently smaller than the resistor R and equivalently given by the resistor R.
  • the DC bias component is cut in a circuit, and a low Q is achieved for the AC component (high-frequency component).
  • FIG. 1 is a cross-sectional view of a low-EMI device in which a circuit is formed on the surface of an LSI device (chip), which is an example of the present invention.
  • FIG. 2 shows a plan view of the low EMI device of FIG. 1 as viewed from above the active surface.
  • Figure 3 shows the circuit model diagram formed on the surface of the LSI device (chip).
  • FIG. 4 shows a circuit model diagram in a case where constraints are provided in the circuit model of FIG.
  • Fig. 5 is an example of Kimei, and shows a process chart of the manufacturing process of a low EML device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively.
  • FIG. 6 shows another embodiment of the wood invention, and shows a manufacturing process diagram of a low EMI device, wherein (a) and (b) show a cross-sectional view and a plan view in each step, respectively.
  • FIG. 7 shows another embodiment of the present invention and shows a process chart of a manufacturing process of a low EMI device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively.
  • FIG. 8 shows another embodiment of the present invention and shows a process chart of a manufacturing process of a low EML device, and (a) and (b) show a cross-sectional view and a plan view in each step, respectively. .
  • FIG. 9 shows another embodiment of the present invention, showing a process diagram of the manufacturing process of a low-EMl device, wherein (a) and (b) are cross-sectional views in each step, and FIG. Figure is shown.
  • FIG. 10 shows another embodiment of the wood invention, showing a process chart of a manufacturing process of a low EMI device, wherein (a) and (b) show a sectional view and a plan view in each step, respectively.
  • FIGS. 11A and 11B show another example of the present invention, in which the manufacturing process of a low EML device is shown in the form of a cross-sectional view and a plan view, respectively. The figure is shown.
  • FIG. 1 is an embodiment of the present invention, and shows a cross-sectional view of a low EMI device 1 in which a circuit is formed on a surface of an LSI device (chip) by a bypass capacitor and a resistor.
  • FIG. 2 is a plan view of the low EMI device 1 shown in FIG. 1 as viewed from above.
  • the outermost surface of the LSI chip 2 is covered with a silicon oxide passivation film, and a ground pad 11 for connection to an external circuit and a power pad 12 ( (Not shown), and electrode terminals such as signal pad 13 (not shown).
  • the first insulating film 3, the first conductive film 4, the first dielectric film 5, the resistance film 6, and the like are formed on the surface of the LSI chip 2 on which the electrode terminals are formed. It has a circuit structure in which a rest film 7 of ⁇ 2, a dielectric film 8 of ⁇ 2, a third rest film 9, and a second insulation 010 are formed. In particular, by forming a circuit inside the electrode terminal, the external shape and area of the LSI chip 2 are not affected.
  • the first bypass capacitor C 1 is formed by sandwiching the first dielectric film 5 between the first conductive film 4 and the second conductive film 7, and the second bypass capacitor C 2 is formed by ⁇ 2
  • the dielectric crotch 8 is formed so as to be sandwiched between the 52 body film 7 and the third conductor film 9.
  • the resistance R is formed by sandwiching the resistance rest film 6 between the first conductor film 4 and the third conductor film 9.
  • Grounds 14 and 15 are ground chips of LSI chip 2, respectively.
  • the pads 11 and the power supply pad 12 are taken out at the shortest distance and are connected at multiple locations.
  • the current loop length, area, And the inductance component is greatly reduced to suppress potential fluctuations due to resonance and the like.
  • FIG. 3 shows a model of a circuit formed on the surface of the SI chip 2. Viewed from Grad down Dopa' de 1 1 and power pad 1 2 LSI chip 2, the second of the bus capacitor C 2 1 8 to the first bus 0 scan capacitor C 1 1 7 and resistor R 1 9 series Are connected in parallel.
  • FIG. (A) and (b) in the figure show a sectional view and a plan view, respectively.
  • FIG. 5 shows a top view of the first insulating film 3 formed on the LSI chip 2.
  • a 1-m-thick silicon oxide film is formed by CVD on the entire surface of the LSI chip 2 as a passive junction.
  • a photo process and a dry etching method are performed; 1J, and an insulating film 3 of ⁇ 1 is formed in a region excluding an electrode pad such as a ground pad 11 of the LSI chip 2.
  • the sessionion film has a multilayer structure.
  • FIG. 6 shows a process chart of the first conductive film 4 formed after the first insulating crotch 3.
  • a 500 nm thick platinum thin layer is formed on the entire surface of the LSI chip 2 as an electrode layer of the first bypass capacitor C117 by using a sputtering method.
  • the lead pattern is connected to the ground pad 11 by a photo process and reactive dry etching. 14 and the first passivation film 4 consisting of a portion on the central passivation film of the LSI chip 2 is removed.
  • FIG. 7 shows a process chart of the resistor film 6 formed after the first insulating film 4.
  • a cermet resistance material of chromium and silicon oxide was used, and the entire surface of the LSI chip 2 was formed to a thickness of 900 nm by a sputtering method as a resistance film.
  • the resist film is applied to the rectangular shape along the four sides of the LSI chip 2 by a photo process and a jet etching method to form the resistive film 6.
  • the shape of the resistive film 6 is rectangular. The shape is not limited, but the symmetrical shape is adopted to make the TS characteristics of the bypass capacitor, as viewed from the adjacent ground pad 1 ⁇ and power supply pad 12, equal.
  • FIG. 8 shows a process chart of the first dielectric film 5 formed after the resistor film 6.
  • a 200 nm thick tantalum oxide layer is formed on the entire surface of the LSI chip 2 by sputtering. Then, a resist rest film 6 and a dielectric rest film 5 of 1 are formed on the conductor film 4 of FIG. 1 except for a region of the ground pad 11 by a photo process and a wet etching method. In this case, on the four sides adjacent to the electrode pads such as the ground pad 11 of the LSI chip 2, the induction rest 5 of ⁇ 1 is formed so as to cover the conductor film 4 of 11.
  • the length of the first invitation 5 is set in consideration of the withstand voltage and the capacitance value.
  • the 50 nm process may be repeated 2 to 4 times.
  • dielectric material As a dielectric material, there is a method of increasing the specific dielectric constant by using barrier titanate BaTi03 or strontium titanate SrTi3. As a process, spin coating is used instead of sputtering in consideration of composition control and characteristic reproduction.
  • FIG. 9 shows a process diagram of the second guide rest 7 formed after the introductory rest 5 of ⁇ 1.
  • a 500 nm thick I gold layer is formed by sputtering over the entire surface of the LSI chip 2.
  • a second conductor crotch 7 is formed on the first dielectric film 5 as an electrode layer of the first bypass capacitor C 117 and the second bypass capacitor C 218 by recess and dry etching. .
  • the second conductor film 7 has a lead pad 15 for connecting to the power supply pad 12.
  • the first bypass capacitor C 117 is divided into plural parts and formed in consideration of the arrangement condition of the power supply pad 12.
  • the first conductive film 4 is used as a common ground electrode, and the second conductive film 7 forms a plurality of power electrodes.
  • FIG. 10 shows a process chart of the second dielectric film 8 formed after the second conductive film 7.
  • a 200-nm-thick oxide thin film is formed on the entire surface of the LSI chip 2 by using a sputtering method. In some cases, the 5 O nm process is repeated 2 to 4 times as a growth process. Then, a part of the resistive film 6 and the upper surface of the electrode pad such as the ground pad 11 of the LSI chip 2 are removed by a photo-etching and a jet etching method. Further, the second dielectric film 8 is formed so as to form a break 4 of ⁇ 1 and a conduction break 7 of ⁇ 2.
  • FIG. 9 shows a process chart of the third conductive film 9 formed after the second insulating film 8.
  • a 500 nm thick gold thin film is formed on the entire surface of the LS1 chip 2 by using a sputtering method. This is converted into a second bypass capacitor C218 and a resistor R19 by a photo process and a dry etching method.
  • the 3 rest 9 of the 3 It is formed so as not to protrude outside.
  • a second insulating film 10 as a passivation film is formed.
  • a 1-m-thick silicon oxide film is formed on the entire surface of the LSI chip 2 using the CVD method. This is formed in a region excluding the electrode pad such as the ground pad 11 of the LSI chip 2 by a photo process and a dry etching method.
  • the passivation film has two layers to improve moisture resistance.
  • a circuit in which a second bypass capacitor C2 and a resistor R are connected in series is connected in parallel to a first bypass capacitor C1 connected to a power supply pad and a ground pad.
  • the DC component of the bypass capacitor circuit viewed from between the power supply pad and the ground pad is not only a DC component but also a low Q with respect to the AC component (high-frequency component).
  • it has the effect of absorbing potential fluctuations generated between the pads and greatly suppressing electromagnetic radiation from the LSI device itself and the wiring connected to it.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Dispositif à faible brouillage électromagnétique à forte densité de composants, dans lequel les rayonnements inutiles sont éliminés de façon efficace par la conversion en chaleur, par effet Joule, de la fluctuation de potentiel au niveau du plot d'alimentation électrique par rapport au plot de mise à la terre, qui se produit lorsqu'on déclenche un élément LSI, etc., sans qu'il soit nécessaire d'employer aucun dispositif de protection contre le brouillage. On forme un élément à la surface du dispositif LSI, au moyen d'un procédé de couche mince. On connecte en parallèle à un premier condensateur de découplage (C1), lui-même relié aux plots d'alimentation électrique et de mise à la terre, un circuit dans lequel un deuxième condensateur de découplage (C2) et une résistance (R) sont montés en série. On rend ainsi l'impédance du condensateur (C2) suffisamment inférieure à celle de la résistance (R). La composante de courant continu du facteur de qualité du circuit du condensateur de découplage entre le plot d'alimentation électrique et le plot de mise à la terre est diminuée, et le facteur de qualité relatif à la composante de courant alternatif (haute fréquence) est faible (inférieur à 10), si bien que la fluctuation de potentiel entre les plots est absorbée. Ainsi, le rayonnement électromagnétique provenant du dispositif LSI lui-même et des fils connectés à celui-ci est éliminé dans des proportions notables.
PCT/JP1995/000431 1995-03-15 1995-03-15 Circuit de dispositif a faible brouillage electromagnetique et sa structure WO1996028848A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP52744596A JP3909086B2 (ja) 1995-03-15 1995-03-15 電子装置
PCT/JP1995/000431 WO1996028848A1 (fr) 1995-03-15 1995-03-15 Circuit de dispositif a faible brouillage electromagnetique et sa structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/000431 WO1996028848A1 (fr) 1995-03-15 1995-03-15 Circuit de dispositif a faible brouillage electromagnetique et sa structure

Publications (1)

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WO1996028848A1 true WO1996028848A1 (fr) 1996-09-19

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0993045A1 (fr) * 1998-10-07 2000-04-12 Hewlett-Packard Company Dé à circuit intégré à suppression de bruit couplé directement
JP3244623B2 (ja) 1995-12-27 2002-01-07 株式会社日立製作所 低ｅｍｉパッケージ回路及び装置
WO2007073965A1 (fr) * 2005-12-23 2007-07-05 Robert Bosch Gmbh Circuit integre a semi-conducteur
JP2010287740A (ja) * 2009-06-11 2010-12-24 Nec Corp 半導体集積回路、プリント配線基板、プリント配線基板電源回路設計装置及び方法、およびプログラム
JP2014502428A (ja) * 2010-12-07 2014-01-30 ザイリンクス インコーポレイテッド 電力分配ネットワーク

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120930U (fr) * 1976-03-11 1977-09-14
JPH03239357A (ja) * 1990-02-16 1991-10-24 Mitsubishi Electric Corp マイクロ波集積回路用キャパシタ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52120930U (fr) * 1976-03-11 1977-09-14
JPH03239357A (ja) * 1990-02-16 1991-10-24 Mitsubishi Electric Corp マイクロ波集積回路用キャパシタ

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3244623B2 (ja) 1995-12-27 2002-01-07 株式会社日立製作所 低ｅｍｉパッケージ回路及び装置
EP0993045A1 (fr) * 1998-10-07 2000-04-12 Hewlett-Packard Company Dé à circuit intégré à suppression de bruit couplé directement
SG73610A1 (en) * 1998-10-07 2002-01-15 Agilent Technologies Inc Integrated circuit die with directly coupled noise suppression and/or other device
WO2007073965A1 (fr) * 2005-12-23 2007-07-05 Robert Bosch Gmbh Circuit integre a semi-conducteur
JP2010287740A (ja) * 2009-06-11 2010-12-24 Nec Corp 半導体集積回路、プリント配線基板、プリント配線基板電源回路設計装置及び方法、およびプログラム
JP2014502428A (ja) * 2010-12-07 2014-01-30 ザイリンクス インコーポレイテッド 電力分配ネットワーク

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