WO1996018934A1

WO1996018934A1 - A further improved system logic controller for digital computers

Info

Publication number: WO1996018934A1
Application number: PCT/US1994/014446
Authority: WO
Inventors: Shyun Dii Du; Edward L. Chen; Yishao Max Huang
Original assignee: Green Logic Inc.
Priority date: 1994-12-14
Filing date: 1994-12-14
Publication date: 1996-06-20

Abstract

The present invention is a system logic controller ('SLC') (24) specially adapted for reducing and regulating electrical power consumption by a personal computer ('PC') (10). The SLC (24) includes a plurality of power management registers located in a power management unit (128). When turning the computer (10) on, storage of data into one of the power management registers by a computer program executed by the CPU (12) causes the SLC (24) to broadcast data values to various power management registers. The data broadcast to these registers establishes a specified power management operating regime for the computer (10). The SLC (24) also monitors peripheral devices included in the computer (10) and transmits a system management interrupt to the CPU (12) if an operating peripheral device is to be turned off, or if a non-operating device is to be turned on because it is being accessed by a computer program executed by the CPU (12).

Description

A FURTHER IMPROVED SYSTEM LOGIC CONTROLLER FOR DIGITAL COMPUTERS

Technical Field The present invention relates generally to the technical field of digital computers and, more particularly, to an im¬ proved, low-power system logic controller which facilitates easily regulating a computer's electrical power consumption, while concurrently permitting high computer system performance and availability.

Background Art

Presently, manufacturers of personal computers are experi¬ encing a continuing need to reduce electrical power consumption both for desk top computers and for laptop and notebook comput¬ ers. Moreover, manufacturers are also experiencing a continuing demand for low-power laptop and notebook computers that provide performance equalling that of desktop computers. Patent Cooperation Treaty ("PCT") International Patent Application no. PCT/US94/04241 filed 18 April 1994, discloses a system logic controller ("SLC") for digital computers which facilitates efficiently managing a computer's electrical power consumption. The disclosure of PCT Application No. PCT/US94/04241 is hereby incorporated by reference as though fully set forth here. Present personal computers include an integrated circuit ("IC") central processing unit ("CPU") that is coupled by a high speed CPU bus having both CPU address lines and CPU data lines to various other ICs included in the computer. Such personal computers conventionally also include a slower speed I/O bus for exchanging signals with I/O cards that may be installed in the computer. Between the high-speed CPU bus and the slower-speed I/O bus, these computers generally incorporate a SLC IC which performs various functions essential to the computer's operation, including interfacing between the high-speed CPU bus and the slower speed I/O bus. More specifically, in the instance of IBM Personal Computers and clone personal computers which utilize Intel X86 IC microprocessors, the high-speed bus may be called a VESA Local Bus ("VLB"), and the slower speed I/O bus is generally either an Industry Standard Architecture ("ISA") b or an Extended Industry Standard Architecture ("EISA") bus.

A SLC included in such a personal computer is coupled to t CPU address lines, CPU data lines, and CPU control lines includ in the VLB, and to analogous signal lines in the I/O bu Accordingly, the system logic controller includes a CPU interfa controller for exchanging signals with the CPU bus. Usually, t system logic controller also includes a DRAM controller f generating RAS and CAS signals which are required to acce dynamic random access memory ("DRAM") included in the compute and for periodically refreshing the data stored in the DRAM. T system logic controller also includes an I/O bus controller whi exchanges with I/O cards signals that are required to effect da transfers between an I/O device and the system logic controll and/or the DRAM. A system logic controller also includes peripheral controller which performs a variety of functions al required to effect data transfers between the system log controller and/or DRAM and I/O devices such as hard and flop disk drives. The functions performed by the peripheral contro ler include receiving and storing interrupts, and effecti direct memory access ("DMA") data transfers between I/O devic and the DRAM. The peripheral controller also includes a clo into which the current date and time are stored when the comput is initialized, and by which the computer subsequently kee time. The peripheral controller included in the system log controller IC also includes counters which provides timi signals required for the DRAM controller's periodic refreshi of data stored in the DRAM. A book entitled "Intel's Architecture, Designing Portable Application" by Desmond Yue copyright 1993 by McGraw-Hill, Inc. provides a more thorough a detailed description of various facilities provided by and t various operation performed by a system logic controller.

A SLC capable of providing advanced power manageme features generally includes a number of control registers th must be properly programmed when the computer is first turned to establish a power management regime for the computer's pow management features. Writing a computer program that configur a computer's power management features when it is first turn on is a cumbersome task because it requires that the computer programmer possess a detailed understanding of all the computer's hardware power management features including details of the SLC's operation in effecting electrical power management. Activating all the power management features provided by a modern SLC using a software power management routine executed by an IC CPU may require that such a computer program routine store various data into two (2) dozen or more registers that are included within the SLC, and that such data must be stored into those registers in a particular sequence.

Furthermore, a modern energy efficient computer will, over time, operate in several different power management regimes. For example, if a portable computer is being used in an office environment where electrical power consumption is an insignifi- cant concern, then the computer user may want the computer to provide the highest performance and availability possible. Conversely, if the computer is being operated on battery power where there is no convenient source of electrical energy, then the computer user may want to choose a power management regime for the computer that will maximize the time the computer operates without recharging its batteries, even though perfor¬ mance and availability may be noticeably reduced.

Furthermore, within each of the two preceding power management regimes, i.e. a regime which provides maximum perfor- mance and a regime which minimizes the computer's electrical power consumption, the computer may operate in distinctly different modes depending upon its instantaneous operation. For example within any power management regime a computer may operate in: l. a Full System Speed Mode in which the IC CPU runs at its maximum speed, without timing-out peripheral devices, e.g. a Personal Computer Memory Card Interna¬ tional Association ("PCMCIA") controller and its associated sockets, a keyboard controller, a video display, a floppy disk drive, a hard disk drive and a

Super I/O Chip including its COM and LPT ports, or with only long time-out intervals based on peripheral activity; 2. a System Doze Mode in which the IC CPU runs at slower "doze" speed;

3. a System Sleep Mode which halts IC CPU operation, an in which peripheral devices must be timed-out o turned off before halting IC CPU operation;

4. a Five Volts Suspend Mode in which the IC CPU and al system peripheral devices are turned off; and

5. a Zero Volt Suspend Mode which turns off electrica power to virtually the entire computer. Consequently, software executed by the IC CPU for establishin one of several different power management regimes when a compute is first turned on must be capable of storing several differen values into each of the two (2) dozen or more power managemen registers depending upon the particular characteristics of eac power management regime.

In implementing conventional computer power managemen strategies, a power management routine executed by the IC CP must periodically monitor peripheral devices to assess whethe a peripheral device's operation may be suspended. Similarly, i it becomes necessary to access a peripheral device whos operation has been suspended, the power management routine mus resume that peripheral device's operation. Generally, suspendin the operation of a peripheral device and resuming its operatio respectively require that the power management routine execute by the IC CPU perform a unique sequence of operations in turnin off electrical power to a peripheral device, and in turnin electrical power back on. Writing a computer program tha detects a need to execute a power-on or a power-off sequence o operations for a peripheral device is a cumbersome task. Finally, coupling power management signals out of a SLC t effect power management control of peripheral devices include in the personal computer encounters a ubiquitous pin coun limitation which is always present in IC design. However, thi universal problem is particularly severe in designing ICs whic not only exchange digital data with peripheral devices, bu moreover must also control power consumption by such devices. Consequently, an advanced electrical power management SLC whic requires fewer pins to perform the standard functions that mus be performed by any SLC makes available IC pins for signals that couple power management signals to other parts of the digital computer.

Present personal computers which include an Intel IC microprocessor may, in fact, employ one of two different types of real-time clock ICs. Even though the real-time clock IC chip may, in fact, be manufactured by a company other than Intel, Inc. or Motorola, Inc., they are colloquially identified as the Intel real-time clock and the Motorola real-time clock. These names are applied colloquially to such real-time clock IC chips to indicate that the chip's operates either in accordance with a protocol for timing signals of an eight (8) bit wide bus used for Intel early microprocessors, or in accordance with a protocol for timing signals for an eight (8) bit wide bus used early for Motorola microprocessors. Additionally, there are real-time clock IC chips which are electronically programmable to operate either in accordance with the Intel bus timing protocol, or in accordance with the Motorola bus timing protocol.

Originally, real-time clock IC chips connected directly to what was then a high-speed, eight (8) bit wide CPU bus of early IC microprocessors. However, because present IC microprocessors now employ thirty-two (32) bit wide buses which operate at speeds up to twenty times faster than the CPU bus speeds for early microprocessors, presently real-time clock IC chips connect to the eight (8) or sixteen (16) bit wide I/O bus which originates at the system logic controller IC. Standard signal lines for the eight(8) or sixteen (16) bit wide I/O bus originating at the system logic controller includes a bus address latch enable ("BALE") signal line. A protocol for exchanging data between the system logic controller IC and a device connected to the I/O bus specifies that the system logic controller transmit a signal, i.e. a pulse, on the BALE signal line during every data transfer cycle of the I/O bus. That is, the system logic controller IC must transmit a signal on the BALE signal line when sending an address to a device connected to the I/O bus, and must also send a subsequent signal on the BALE signal line when exchanging data with, i.e. reading data from or writing data to, the addressed device. However, the bus cycle for a real-time clock ICs operatin in accordance with the Intel protocol consists of two phases: a address phase and a data-transfer phase. The address phas precedes the data-transfer phase. During the address phase, a address placed on data lines AD₀-AD, is latched into the rea time clock on the falling edge of an address strobe ("AS" signal. During the data-transfer phase of the bus cycle, th AD₀-ADτ data lines function as a bidirectional data bus dependin upon whether data is being read from or written to the real-tim clock IC. While the AS signal required by the real time cloc during its first phase is equivalent to the signal on the BAL signal line of the I/O bus, the conventional BALE signal i incompatible with the AS signal during the second phase of th real-time clock ICs operation. Thus, to accommodate real-tim clock ICs operating in accordance with the Intel protocol present system logic controllers include a separate output signa pin which is dedicated to providing the unique AS signal whic is required when reading from or writing to a real-time clock I that operates in accordance with the Intel protocol.

Disclosure of Invention

An object of the present invention is to provide a SLC whic is easily programmed to perform electrical power management fo a digital computer. Another object of the present invention is to provide a SL which is easily programmed to provide different power managemen regimes.

Another object of the present invention is to provide a SL having several different power management operating modes whic are easily programmed to provide different operating regimes.

Another object of the present invention is to provide a SL which facilitates detecting operating conditions that warran changing between different power management operating modes.

Another object of the present invention is to provide system logic controller IC that can perform more functions usin fewer pins.

Briefly, the present invention is an improved system logi controller for use in a digital computer which includes a centra processing unit. In a computer in accordance with the present invention, the central processing unit is coupled to a CPU bus, that includes CPU address lines and CPU data lines, and to which the system logic controller is also coupled. The system logic controller includes both a CPU data interface controller and a power management unit which is specifically adapted for regulat¬ ing electrical power consumption by the digital computer.

The power management unit includes a plurality of power management control registers that receive control data used by the system logic controller in regulating electrical power consumption by the digital computer. A power management data storage array, located within the system logic controller, stores different sets of control data which may be transferred into the plurality of power management control registers. The system logic controller also includes a means for broadcasting a particular set of the control data from the power management data storage array to the plurality of power management control registers in response to a command from the central processing unit. Storage of the power management data into the power management control registers establishes a selected power manage¬ ment operating regime for the digital computer's operation. This ability to broadcast, entirely within the SLC in response to a single instruction from the IC CPU, a set of pre-established data values for establishing a particular power management operating regime for the digital computer removes this responsibility completely from the computer program executed by the IC CPU, and thereby greatly simplifies the writing of that computer program.

The preferred digital computer includes one or more devices; e.g. a display, a hard disk drive, a floppy disk drive, and/or PCMCIA sockets; whose operation may be suspended and/or resumed by a computer program executed by the central processing unit. A computer program executed by the central processing unit must address each such device in reading data from and/or writing data to the device. To facilitate monitoring the activity of these devices, the system logic controller includes a plurality of power management timers which respectively generate a power management time-out condition upon expiration of a pre-estab¬ lished time interval. An auto-event monitoring logic circuit, located within the SLC, detects addressing of the device by computer program executed by the central processing unit. If t auto-event monitoring logic circuit detects that the device h been addressed, the system logic controller establishes a n time at which a particular one of the power management time that is associated with the addressed device will generate power management time-out condition.

The central processing unit included in the digital comput responds to a system management interrupt generated by the syst logic controller by executing a power management routine. If o of the power management timers included in the system log controller experiences a power management time-out condition, t system logic controller sets a bit in a device power-off regist that is included in the system logic controller, and generat a system management interrupt. The power management routi executed by the central processing unit responds to the syst management interrupt first by reading the device power-o register, and then by identifying the device that is to be turn off from the bits that are set in that register. The pow management routine then executes a sequence of operations whi is unique to that particular device to turn off the device' electrical power thereby reducing the digital computer's electri cal power consumption.

The power management unit of the system logic controll also includes a means for monitoring the device's operati status, and for preserving a record of that status. Thus, t means for monitoring the device's operating status indicates i the device is operating, or if the operation of the device h been suspended. If a computer program executed by the centr processing unit addresses the device while the device's operati status monitoring means indicates that the device's operation h been suspended, then the system logic controller sets a bit a device power-on register included in the system logic contro ler, and transmits a system management interrupt to the centr processing unit. The central processing unit responds to t system management interrupt by executing the power manageme routine which first reads the device power-on register, and th identifies the particular device that is to be turned on from t bits that are set in that register. The power management routine then executes a sequence of operations which is unique to that particular device to turn on the device's electrical power thereby restoring the device to operation. The system logic controller in accordance with the present invention also employs an improved method for exchanging data with a real-time clock IC which operates in accordance with the Intel protocol that is coupled to the system logic controller by an I/O bus included in the digital computer. The improved method for exchanging data with the real-time clock IC eliminates any need for using a separate pin on the system logic controller for supplying an AS signal to only the real-time clock IC. As described above, the system logic controller in accordance with the present invention generates the I/O bus including standard signal lines that operates in accordance with a bus protocol in which, during each exchange of data via the I/O bus, a signal normally occurs on a BALE signal line included in the I/O bus during every I/O bus data transfer cycle. However, if the system logic controller in accordance with the present invention accesses the real-time clock IC, during the first I/O bus data transfer cycle the system logic controller transmits a signal to the real-time clock IC via the BALE signal line in accordance with the protocol for the I/O bus while concurrently suppressing transmission both of an I/O read ("IOR") and of an I/O write ("IOW") signal. However, contrary to the protocol for the I/O bus, during the immediately successive I/O bus data transfer cycle to only the real-time clock IC the system logic controller suppresses transmission of a signal to the real-time clock IC via the BALE signal line while concurrently transmitting the appropriate I/O read ("IOR") or I/O write ("IOW") signal. Accordingly, the system logic controller in accordance with the present invention exchanges data with an Intel protocol real-time clock IC using only the standard signal lines normally included in the I/O bus thereby eliminating any need for a separate pin to provide a unique AS signal required only by a real-time clock IC operating in accordance with the Intel protocol.

These and other features, objects and advantages will be understood or apparent to those of ordinary skill in the art from the following detailed description of the preferred embodimen as illustrated in the various drawing figures.

Brief Description of Drawings FIG. 1 is a functional block diagram depicting a digita computer that incorporates a system logic controller in accor dance with the present invention, and which illustrates PCMCI sockets preferably included in such a digital computer;

FIG. 2 is a functional block diagram depicting variou functional units included in the system logic controlle illustrated in FIG. 1 including a power management unit;

FIG. 3 is a table listing various registers included in th power management unit of a system logic controller in accordanc with the present invention; FIG. 4 is a functional block diagram illustrating auto-even monitoring system including several timed interrupt generator and auto-event decode logic circuit that is included in the powe management unit illustrated in FIG. 2;

FIG. 5 is a functional block diagram depicting a auto-even decode logic circuit included in the of FIG. 4; and

FIG. 6 is a timing diagram depicting electrical signals fo a real-time clock IC which operates in accordance with the Inte protocol.

Best Mode for Carrying Out the Invention

FIG. 1 is a functional block diagram depicting a digita computer identified by the general reference character 10. Th computer 10 includes an IC CPU 12 that is coupled to a high spee CPU bus 14, e.g. a VLB, having both CPU address lines 16 and CP data lines 18. The CPU bus 14, which also includes CPU contro signal lines 22, couples the CPU 12 to a IC system logi controller 24. The CPU address lines 16 of the CPU bus 14 als couple the CPU 12 to a DRAM 26. A DRAM address and control bu 32, which includes both DRAM address lines 34 and DRAM contro signal lines 36, couples the system logic controller 24 to th DRAM 26.

I/O bus data lines 42 and I/O bus control signal lines 4 couple the system logic controller 24 to a first section 46 o an I/O bus 48, e.g. an ISA bus. A buffer 52 included in the computer 10 couples signals directly between the CPU address lines 16 and CPU data lines 18 of the CPU bus 14 and the first section 46 of the I/O bus 48. A single IC super I/O chip 54, which provides electronic circuits for a serial port, a parallel port, a floppy disk controller, and an interface for an IDE hard disk drive (none of which are illustrated in FIG. 1) , is also coupled to the first section 46 of the I/O bus 48. A bidirectional I/O bus section isolation buffer 56 couples the first section 46 of the I/O bus 48 to a second section 58 of the I/O bus 48 to which I/O cards (not illustrated in FIG. 1) may be coupled. The I/O bus control signal lines 44 also couple the system logic controller 24 to an IC keyboard controller 62 and to an IC read only memory ("ROM") BIOS 64. The keyboard controller 62 and the ROM BIOS 64 are also coupled to the second section 58 of the I/O bus 48.

To reduce electrical power consumption within the computer 10, those circuits within the system logic controller 24 which do not interface directly with the I/O bus data lines 42 and the I/O bus control signal lines 44 of the I/O bus 48 operate with only three (3) volts of electrical power. Conversely, those circuits within the system logic controller 24 which interface directly with the I/O bus data lines 42 and the I/O bus control signal lines 44 of the I/O bus 48 operate with five (5) volts of electrical power. To permit achieving an even greater reduction in electrical power consumption, the computer 10 preferably includes a 3V/5V buffer 66 that is coupled between the second section 58 of the I/O bus 48 and a 3V extension 68 of the I/O bus 48. The computer 10 also includes PCMCIA sockets 72 that are coupled to the system logic controller 24 by the first section 46 of the I/O bus 48, and by a PCMCIA control signal bus 74.

To facilitate regulation of electrical power consumption by a computer program executed by the CPU 12, the computer 10 includes a direct port access buffer 82 that is coupled to the system logic controller 24 by the CPU address lines 16 of the CPU bus 14, and by direct port access control signal lines 84. A plurality of electrical power control signal lines 86 couple the direct port access buffer 82 to various peripheral devices of t computer 10 such as a display and any backlighting for t display, the hard disk, the floppy disk, a modem, etc. storing appropriate data into the direct port access buffer 82 a computer program executed by the CPU 12 may suspend t operation of such peripheral devices of the computer 10, restore them to operation thereby regulating electrical pow consumption by the peripheral devices.

The computer 10 also includes a battery powered real-ti clock IC 92 which the computer program executed by the CPU reads upon initialization, i.e. "booting", to obtain the prese date and the time. The computer program executed by the CPU 1 subsequently stores the date and time data read from t real-time clock IC 92 into the DRAM 26.

System Logic Controller 24

Referring now to the block diagram of FIG. 2 which illu trates various functional units included in the system log controller 24, the system logic controller 24 includes a C interface controller 102 that is coupled to the CPU address line 16, to the CPU data lines 18, and to the CPU control signal lin 22 of the CPU bus 14. The system logic controller 24 al includes a DRAM controller 104 that is coupled to the DR address lines 34 and to the DRAM control signal lines 36. T I/O bus control signal lines 44 are coupled to an ISA b controller 106 included in the system logic controller 24, whil the I/O bus data lines 42 are coupled to a ISA bus address/da buffer 108. The system logic controller 24 includes a peripher controller 112. A PCMCIA controller 122 included in the syst logic controller 24 is coupled to the PCMCIA control signal b 74, while a direct port access controller 126 included in a pow management unit 128 of the system logic controller 24 is coupl to the direct port access control signal lines 84.

Within the system logic controller 24, SLC data lines 13 and SLC address lines 134 couple signals between the C interface controller 102 and the ISA bus address/data buffer 10 while SLC control lines 136 couple signals between the C interface controller 102 and the ISA bus controller 106. The S address lines 134 couple signals from the CPU interface control¬ ler 102 to the DRAM controller 104, while the SLC data lines 132 couple signals between the CPU interface controller 102 and the peripheral controller 112. Thus, for example, the CPU 12 may read the date and time from the real-time clock IC 92 and then store them into memory locations within the DRAM 26. Analogous¬ ly, via the SLC data lines 132 and the SLC control lines 136, the peripheral controller 112 may periodically increment the contents of the memory location in the DRAM 26 into which the time data has been stored. The SLC control lines 136 also couple signals between the CPU interface controller 102 and the peripheral controller 112 to permit transmission of interrupts from the peripheral controller 112 to the CPU 12, and to permit the computer program executed by the CPU 12 to control the operation of the peripheral controller 112. Periodically, the peripheral controller 112 transmits a timing signal to the DRAM controller 104 over a DRAM refresh timing signal line 138 which causes the DRAM controller 104 to refresh data stored in the DRAM 26. The SLC control lines 136 and the SLC data lines 132 couple signals between the CPU interface controller 102 and the power management unit 128 including the direct port access controller 126. The SLC control lines 136 couple control signals between the CPU interface controller 102 and the PCMCIA controller 122 as does an extension of the I/O bus control signal lines 44 that is located within the system logic controller 24.

The power management unit 128 included in the system logic controller 24 provides a variety of functions which facilitate power reduction within the computer 10. For example, in addition to other features disclosed in greater detail herein, the power management unit 128 supports CPU clock modulation, detects if the CPU bus is idle, includes analog-to-digital converters for monitoring battery voltage in a battery powered computer 10 and for monitoring the temperature of the CPU 12, and shadows write only registers. Specifically with regard to the direct port access buffer 82, the power management unit 128 provides a cost- effective method by which a computer program executed by the CPU 12 may store non time-critical power regulation data into or read non time-critical power regulation data from the direct por access buffer 82.

Power Management Register Broadcast FIG. 3 lists various registers among those included in th power management unit 128. Data written to or read from th various registers listed in FIG. 3, by a power management routin executed by the CPU 12 direct the management of electrical powe consumption by the computer 10. Of particular significance amon the various registers listed in FIG. 3 is register 208H, i.e. Power Management Default Values Control Register. Durin initialization of the computer 10 immediately after it has bee turned on, a basic input-output system ("BIOS") routine execute by the CPU 12 commands the system logic controller 24 to selec among several default power management regimes for the compute 10 by writing a numerical value to register 208H. The numerica value written to register 208H selects among the following powe management regimes: Power Management Off, Standard Powe Management, or Extended Power Management. For example, writin the binary value "00" into register 208H selects the Powe Management Off Regime which disables all power managemen features provided by the system logic controller 24 thus insurin the highest performance and availability levels offered by th computer 10. Writing the binary value "01" into register 208 selects the Standard Power Management Regime which, whil maintaining a high level of performance and availability for th computer 10, enables advanced power management features of th system logic controller 24 thus reducing electrical powe consumption if the computer 10 becomes idle. Selecting extende power management by writing the binary value "10" into th register 208H enables aggressive power conservation by the syste logic controller 24 if the computer 10 becomes idle, while stil providing acceptable levels of performance and availability. Both the Standard Power Management and Extended Power Managemen Regimes are respectively capable of providing all five operatin modes described above, i.e. the Full System Speed Mode, th System Doze Mode, the System Sleep Mode, the Five Volts Suspen Mode, and the Zero Volt Suspend Mode. In response to writing a particular numerical value into the register 208H to select a particular power management regime, the system logic controller 24 broadcasts prescribed numerical values from a power management data storage array 140, included in the power management unit 128 and illustrated in FIG. 2, to the various registers listed in FIG. 3 other than register 208H. The power management data storage array 140 is preferably a read only memory ("ROM") fabricated as part of the system logic controller 24. The three vertical columns of numbers along the right hand side of FIG. 3 list numerical values broadcast from the power management data storage array 140 to the various registers listed in FIG. 3 depending upon whether the numerical value written by the BIOS routine to the register 208H specifies respectively the Power Management Off Regime, the Standard Power Management Regime, or the Extended Power Management Regime. The precise numerical values stored in the power management data storage array 140 and listed in these three (3) columns are determined empirically by ana-lysis of a computer 10 which incorporates the system logic controller 24. Thus, if the binary value "01" is written to register 208H thereby selecting the Standard Power Management Regime, the system logic controller 24 broadcasts the value 04h from the power management data storage array 140 to register 20H, i.e. to the Doze Clock Divider Value Register. The system logic controller 24 uses the numerical value present in register 20H in determining a reduced frequency for the clock signal supplied to the CPU 12 while the computer 10 operates in the Doze Mode. Analogously, if the binary value "10" is written to the register 208H selecting the Extended Power Management Regime, the system logic controller 24 broadcasts the value 04h to register 21H, i.e. to the Turbo Clock Divider Value Register. The system logic controller 24 uses the numerical value present in register 21H to determine a reduced frequency for the clock signal supplied to the CPU 12 while the computer 10 operates in the Full System Speed Mode, but the CPU 12 does not operate at a slower clock frequency, i.e. while the CPU 12 operates in a non-turbo condition of the Full System Speed Mode. In response to writing either a binary value "01" or "10 into register 208H, the system logic controller 24 store numerical values into registers B1H and B2H. The numerica values stored into registers B1H and B2H establish threshol levels for output values generated respectively by genera purpose analog-to-digital converters ("ADCs") 0 and 1 include in the system logic controller 24. (Not illustrated in any o the FIGs.) If, for example, the output value generated by ADC exceeds the threshold level value present in register B1H and th system logic controller 24 is operating either in the standar or in the Extended Power Management Regime, the system logi controller 24 then transmits a System Management Interrup ("SMI") to the CPU 12. Writing binary values "01" or "10" int register 208H, also stores a value into register B6H whic specifies the sampling frequency for general purpose ADCs 0 an 1, i.e. how frequently ADCO and ADCl respectively perform a analog to digital conversion.

The numerical value stored into register B8H by the syste logic controller 24 in response to writing any of the thre permitted values to register 208H determines whether an exces sively high temperature for the CPU 12 causes the system logi controller 24 to transmit a SMI to the CPU 12, and also specifie a threshold level for generating such a SMI. Moreover, if th temperature of the CPU 12 exceeds the threshold specified b register B8H while the computer 10 operates in the Full Syste Speed Mode of either the Standard or Extended Power Managemen Regimes, then the CPU 12 receives the non-turbo clock at th frequency determined by the numerical value present in registe 21H. The numerical value stored into register BAH by writing an of the three permitted values to register 208H specifies a interval of time between successive samplings of the temperatur of the CPU 12.

Writing either a binary value "01" or "10" into registe 208H to establish either the Standard or Extended Power Manage ment Regimes causes the system logic controller 24 to store on or the other of the numerical values specified in FIG. 3 int register 200H, i.e. the SMI Mode Control Register. The numerica values specified in FIG. 3 for the SMI Mode Control Registe enable generation of SMIs by the system logic controller 24. Writing a binary value "00" into register 208H stores a numerical value into register 200H which inhibits generation of SMIs by the system logic controller 24 thereby establishing the Power Management Off Regime. The numerical values listed in FIG. 3 which are stored into register 22OH by the system logic control¬ ler 24 in response to writing either a binary value "01" or "10" into register 208H enables the system logic controller 24 to initiate the Five Volt Suspend mode of operation in either the Standard or Extended Power Management Regimes.

The numerical values listed in FIG. 3 which are stored into register 221H in either the Standard or Extended Power Management Regime enable clock throttling in which a STPCLK# signal transmitted from the system logic controller 24 to the CPU 12 periodically halts operation of the CPU 12 for a specified fraction of the clock pulses being supplied to the CPU 12. In the Standard Power Management Regime, i.e. the binary value "01" is written to register 208H, on average the STPCLK# signal from the system logic controller 24 halts operation of the CPU 12 for two (2) clock pulses for every six (6) clock pulses the CPU 12 operates. In the Extended Power Management Regime, i.e. the binary value "10" is written to register 208H, on average the STPCLK# signal from the system logic controller 24 halts operation of the CPU 12 for three (3) clock pulses for every five (5) clock pulses the CPU 12 operates. Furthermore, the numerical value stored into the register 221H for the Extended Power Management Regime also establishes a one (1) millisecond or shorter delay interval during which operation of the CPU 12 is completely halted whenever a clock doubling feature included in the CPU 12 is enabled or disabled. Operation of the CPU 12 must be suspended each time operation of the clock doubling circuit is enabled or disabled to permit stabilization of phase locked oscillators included in the clock doubling circuit.

Writing a binary value "01" or "10" to the register 208H, thereby selecting either the Standard or Extended Power Manage¬ ment Regimes, stores a numerical value 80h into register 240H. Storing this numerical value into register 240H turns on a continuously running master clock 142 illustrated in FIG. 4. The master clock 142 has a comparatively long interval, e.g. one hou or longer. The master clock 142 supplies timing signals to powe management timers 144a, 144b thru 144n via timing signal line 146. The master clock 142 and timers are described in greate detail in Patent Cooperation Treaty ("PCT") International Paten Application no. PCT/US94/04241 filed 18 April 1994, which i hereby incorporated by reference as though fully set forth here As illustrated in FIG. 4, in addition to receiving timing signal from the master clock 142, each of the power management timer 144a, 144b thru 144n includes a timer output signal line 148a 148b ^{• • •} 148n over which the power management timer 144a, 144 ^{■ ■ ■} 144n may transmit an output signal.

Within each of the power management timers 144a, 144b thr 144n, the timing signals present on the timing signal lines 14 are supplied to a first input of a timed event comparator 152 An output of each timed event comparator 152 is coupled to th timer output signal line 148a, 148b ^{• • •} 148n of the powe management timer 144a, 144b ^{■ • •} 144n to which the timed even comparator 152 belongs. Each of the power management timer 144a, 144b thru I44n also includes an interrupt time registe 154. Each interrupt time register 154 supplies the numerica value which it holds to a second input of the timed even comparator 152 respectively included in the power managemen timer 144a, 144b ^{• • •} 144n to which the interrupt time registe 154 belongs. Each timed event comparator 152 continuousl compares the number which it receives from its associate interrupt time register 154 with the timing signals that i receives from the master clock 142 via the timing signal line 146. If the numerical value which the timed event comparator 15 receives from the interrupt time register 154 equals the timin signals that the timed event comparator 152 receives from th master clock 142, then the timed event comparator 152 transmit an output signal on the timer output signal line 148a, 148b ^{• •} 148n to which it is coupled. Returning again to FIG. 3, establishing the Standard Powe Management Regime by writing the binary value "01" to registe 208H causes the system logic controller 24 to store the numerica value 07h into register 24AH, i.e. into a System Power Managemen Modes Control Register. Storing the number 07h into register 24AH enables the computer 10 to enter the System Doze Mode, the System Sleep Mode, and the Five Volt Suspend Mode if an appropri¬ ate operating history occurs for the computer 10. Writing binary value "10" to register 208H stores the numerical value OFh into register 24AH which, in the Extended Power Management Regime, enables the Zero Volt Suspend Mode of operation in addition to the three modes enabled in the Standard Power Management Regime. Writing the binary value "00" to register 208H causes the system logic controller 24 to store the numerical value OOh into register 250H, i.e. into a System Doze Mode Control Register. The numerical value present in register 250H specifies which particular events the system logic controller 24 monitors in determining if the computer 10 is to enter the System Doze Mode of operation. If the computer 10 is to enter System Doze Mode while operating in the Power Management Off Regime, the system logic controller 24 monitors the occurrence of non-periodic SMIs, cycles on the CPU bus 14, write operations to a video buffer (not illustrated in any of the FIG.s) , read operations to an output buffer included in the keyboard controller 62, and input/output activity on the I/O bus 48. If all of the preceding events do not occur during a pre-established time interval, then there exists no condition which prohibits the system logic controller 24 from placing the computer 10 in the System Doze Mode of operation. Writing the binary value "01" to register 208H causes the system logic controller 24 to store the numerical value lFh into register 250H. In the Standard Power Management Regime, the system logic controller 24 monitors none of the events identified above for the Power Management Off Regime in determining if the computer 10 is to enter the System Doze Mode of operation. Writing the binary value "10" to the register 208H causes the system logic controller 24 to store the numerical value 06h into register 250H. The presence of the numerical value 06h in register 250H causes the system logic controller 24 to monitor only write operations to a video buffer and reading an output buffer included in the keyboard controller 62 in determining if the computer 10 is to enter the System Doze Mode of operation. Writing a binary value "01" or "10" to register 208H stor a numerical value into register 251H that determines a ti interval during which the computer 10 must be idle before t system logic controller 24 places the computer 10 into the Syst Doze Mode of operation. In the Standard Power Management Regim the numerical value 80h stored into register 251H establishes time interval of 16 seconds during which the computer 10 must idle before the system logic controller 24 places the comput 10 into the System Doze Mode of operation. The numerical val lOh stored into the register 251H when the computer 10 operat in the Extended Power Management Regime establishes a ti interval of 4 seconds during which the computer 10 must be id before the system logic controller 24 places the computer 10 in the System Doze Mode of operation. Writing a binary value "01" or "10" to register 208H stor a numerical value into register 252H that determines a ti interval during which the computer 10 operating in System Do Mode must be idle before the system logic controller 24 plac the computer 10 into the System Sleep Mode of operation. In t Standard Power Management Regime, the numerical value 14h stor into register 252H establishes a time interval of 10 minut during which the computer 10 must be idle in the System Doze Mo before the system logic controller 24 places the computer 10 in the System Sleep Mode of operation. The numerical value 0 stored into the register 252H when the computer 10 operates the Extended Power Management Regime establishes a time interv of 2 minutes during which the computer 10 must be idle in t System Doze Mode before the system logic controller 24 places t computer 10 into the System Sleep Mode of operation. Writing a binary value "01" or "10" to register 208H stor a numerical value into register 254H that determines a ti interval during which the computer 10 operating in System Sle Mode must be idle before the system logic controller 24 plac the computer 10 into the Five Volt Suspend Mode of operatio In the Standard Power Management Regime, the numerical value 3 stored into register 254H establishes a time interval of minutes during which the computer 10 must be idle in the Syst Sleep Mode before the system logic controller 24 places t computer 10 into the System Sleep Mode of operation. The numerical value OAh stored into the register 254H when the computer 10 operates in the Extended Power Management Regime establishes a time interval of 5 minutes during which the computer 10 must be idle in the System Sleep Mode before the system logic controller 24 places the computer 10 into the Five Volt Suspend Mode of operation.

Writing a binary value "01" or "10" to register 208H stores a numerical value into register 256H that determines a time interval during which the computer 10 operating in Five Volt Suspend Mode must be idle before the system logic controller 24 places the computer 10 into the Zero Volt Suspend Mode of operation. In the Standard Power Management Regime, the numerical value 28h stored into register 256H establishes a time interval of 20 minutes during which the computer 10 must be idle in the System Sleep Mode before the system logic controller 24 places the computer 10 into the System Sleep Mode of operation. The numerical value 14h stored into the register 256H when the computer 10 operates in the Extended Power Management Regime establishes a time interval of 10 minutes during which the computer 10 must be idle in the Five Volt Suspend Mode before the system logic controller 24 places the computer 10 into the Zero Volt Suspend Mode of operation.

Writing a binary value "01" or "10" to register 208H causes the system logic controller 24 to store numerical values into registers 260H and 261H. The precise numerical values stored into the registers 260H and 261H enable operation of various power management timers 144a, 144b thru I44n illustrated in FIG. 4. Enabling any one of the power management timer 144a, 144b ^{• ■ ■} 144n permits generating a SMI if the enabled power management timer 144a, 144b ^{• • •} 144n times-out. The numerical value 3Fh stored into register 260H in the Standard Power Management Regime enables idle power management timers 144x for the two PCMCIA sockets 72, for the keyboard controller 62, for the video buffer, for the floppy disk drive, and for the hard disk drive, each of which is included in the computer 10. The numerical value FFh stored into register 260H in the Extended Power Management Regime enables idle power management timers 144x for all of the devices identified above for the Standard Power Management Regime, pl two additional programmable devices which may be specified duri design of the computer 10. The numerical value 08h stored in register 261H in both the Standard and Extended Power Manageme Regimes enables idle power management timers 144x for the sup I/O chip 54, for both COM and LPT ports provided by the super I/ chip 54, and for the COM port individually, and for the LPT po individually. If any power management timer 144x times-ou because the device with which it is associated is idle for a pr established interval of time, the time-out condition causes a S to be generated.

Writing a binary value "01" or "10" to register 208H caus the system logic controller 24 to store numerical values in registers 264H thru 269H which, in the illustration of FIG. are respectively included in one of the power management time 144a, 144b thru 144n as a time-out interval register 156. V the SLC data lines 132 illustrated in FIG. 4, the system log controller 24 stores the numerical values into each time-o interval register 156. The numerical value stored into particular time-out interval register 156 represents the interv of time during which a device must be idle before that pow management timer 144a, 144b ^{• • •} 144n which includes the time-o interval register 156 generates a SMI. Each of the pow management timers 144a, 144b thru 144n also preferably includ an adder 158 having a first input which receives the numeric value present in the time-out interval register 156. A seco input of the adder 158 receives the timing signals from t master clock 142. Each of the power management timers 144a, 14 thru 144n also includes a timer trigger signal line 162a, 16 ^{• • ■} 162n which respectively supplies a trigger signal to ea adder 158 included in the power management timers 144a, 144b th 144n. A signal sent to any power management timer 144a, 144b ^{■ •} 144n respectively via the timer trigger signal line 162a, 16 ^{• • •} 162n causes the adder 158 included in that power manageme timer 144a, 144b ^{■ ■ •} 144n to add the numerical value present the time-out interval register 156 to the numerical val represented by the timing signals present on the timing sign lines 146, and to store the result of that addition into t 6/18934 PCMJS94/14446

- 23 - interrupt time register 154. The interrupt time register 154, as described above, supplies that result to one input of the timed event comparator 152.

Referring again to FIG. 3, the numerical value 14h which the system logic controller 24 operating in the Standard Power Management Regime stores into registers 264H and 265H establishes a 10 minute time-out interval respectively both for the hard disk drive and for the floppy disk drive. In the Extended Power Management Regime, the numerical value 02h stored into registers 264H and 265H establishes a 1 minute time-out interval respec¬ tively for the hard disk drive and for the floppy disk drive. The numerical value OAh which the system logic controller 24 operating in the Standard Power Management Regime stores into register 266H establishes a 5 minute time-out interval for the video buffer. Similar to the hard and floppy disk drives, the numerical value 02h stored in the register 266H establishes a 1 minute time-out interval for the video buffer if the computer 10 operates in the Extended Power Management Regime. The numerical value 28h which the system logic controller 24 operating in the Standard Power Management Regime stores into registers 267H, 268H and 269H establishes 20 minute time-out intervals respectively for the keyboard controller 62 and for the two PCMCIA sockets 72. The numerical value 04h stored into registers 267H, 268H and 269H if the computer 10 operates in the Extended Power Management Regime establishes 2 minute time-out intervals respectively for the keyboard controller 62 and for the two PCMCIA sockets 72.

Automatic Event Monitoring

Referring now to FIGs. 4 and 5, the power management unit 128 of the system logic controller 24 includes an auto-event decode logic circuit 172 which, among other things, supplies trigger signals via the timer trigger signal line 162a, 162b ^{• ■ •} 162n to the adder 158 included in each of the power management timer 144a, 144b ^{• ■ •} 144n. The auto-event decode logic circuit 172 receives addresses via an I/O address bus 174 for various activities, e.g. reading or writing to particular memory location and I/O device address, as such activities occur on the CPU bus 14 and on the I/O bus data lines 42. The auto-event decode logic circuit 172 also receives signals indicating PCMCIA I/O activit from the PCMCIA controller 122 respectively via a PCMCIA Socke A activity signal line 176a and via a PCMCIA Socket B activit signal line 176b. As illustrated in FIG. 5, the auto-event decode logi circuit 172 includes a plurality of address comparators 182a 182b thru 182n-2. One input of each of the address comparator 182a, 182b thru 182n-2 respectively receives the addresses fro the I/O address bus 174, and another input of each addres comparators 182a, 182b thru 182n-2 receives a device addres 184a, 184b ^{• • •} 184n-2 that is associated with one of the device described above for registers 260H and 261H. The devic addresses 184a, 184b thru 184n-2 are preferably a ROM fabricate as part of the system logic controller 24. If the device addres 184a, 184b ^{• ■ ■} 184n-2 which a particular address comparator 182a 182b ^{• • •} 182n-2 receives equals the address which all the addres comparators 182a, 182b thru 182n-2 receive via the I/O addres bus 174, then that particular address comparator 182a, 182b ^{• •} 182n-2 produces an output signal. The output signal from each address comparator 182a, 182 ^{• • •} 182n-2 is respectively supplied to one input of a time trigger AND gate 186a, 186b ^{• • •} 186n-2, and to one input of device power on AND gate 188a, 188b ^{■ ■ •} 188n-2. A signal presen on the PCMCIA Socket A activity signal line 176a is supplied bot to a timer trigger AND gate 186n-l and to a device power on AN gate 188n-l. Similarly, a signal present on the PCMCIA Socke B activity signal line 176b is supplied both to a timer trigge AND gate I86n and to a device power on AND gate I88n. Th auto-event decode logic circuit 172 also includes a devic operating status monitoring register 192 which stores devic on/off status information for all of the devices identified abov for registers 260H and 261H. The device operating statu monitoring register 192 is a hidden register within the syste logic controller 24 that cannot be read or written from the CP 12. The device operating status monitoring register 192 supplie the device on/off status information which it maintains to second input of each of the timer trigger AND gates 186a, 186 thru 186n, and to an inverting input of each of the device power on AND gates 188a, 188b thru 188n.

If data present in the device operating status monitoring register 192 indicates that the device is then turned on and operating, each time a device's address becomes present on the I/O address bus 174 or a signal occurs on the PCMCIA activity signal lines 176a or 176b the corresponding timer trigger AND gate 186a, 186b ^{• • •} I86n supplies a trigger signal via one of the timer trigger signal line 162a, 162b • ^{• ■} 162n to the adder 158 included in the corresponding power management timer 144a, 144b ^{• • ■} 144n. Consequently, if a device is turned on and that device's address becomes present on the I/O address bus 174 or a signal occurs on the PCMCIA activity signal lines 176a or 176b, then the adder 158 included in the power management timer 144a, 144b ^{• • •} 144n re-initializes that devices' time-out interval being monitored by that power management timer 144a, 144b ^{• • •} 144n. However, as depicted in FIG. 4, if the devices' time-out interval expires and therefore the timed event comparator 152 included in that devices' power management timer 144a, 144b ^{• • ■} 144n produces an output signal, then that signal indicating expiration of the time-out interval is transmitted from the power management timer 144a, 144b ^{• • •} 144n via the timer output signal line 148a, 148b • ^{• •} 148n for storage as a single bit in a device power-off register 202a or 202b, and the system logic controller 24 transmits a SMI to the CPU 12. Setting of a bit in either device power-off register 202a or 202b indicates that the power management routine executed by the CPU 12 is to turn off the device associated with that particular bit to conserve electrical power. In response to the SMI, the power management routine executed by the CPU 12 reads data identifying the device to be turned off from the device power-off registers 202a and 202b. Reading of the device power-off registers 202a and 202b by a computer program executed by the CPU 12 causes the system logic controller 24 to automatically reset the device power-off registers 202a and 202b thereby preparing the device power-off registers 202a and 202b for the occurrence of a subsequent time¬ out condition. Alternatively, if the data present in the device operati status monitoring register 192 indicates that a device is turn off and that device's address becomes present on the I/O addre bus 174 or a signal occurs on the PCMCIA activity signal lin 176a or 176b, then the device power on AND gate 188a, 188b ^{• •} 188n which corresponds with the device whose address has beco present on the I/O address bus 174 or a signal occurs on t PCMCIA activity signal lines 176a or 176b transmits a signal v device power-on signal lines 204a, 204b thru 204n which sets bit in a device power-on register 206a or 206b, and the syst logic controller 24 transmits a SMI to the CPU 12. Setting a bit in either device power-on register 206a or 206b indicat that the device is turned off, and the power management routi executed by the CPU 12 is to turn on the device associated wi that particular bit because a computer program executed by t CPU 12 needs to access the device. In response to the SMI, t power management routine executed by the CPU 12 reads da identifying the device to be turned on from the device power- registers 206a and 206b. Reading of the device power- registers 206a and 206b by a computer program executed by the C 12 causes the system logic controller 24 to automatically res the device power-on registers 206a and 206b thereby preparing t device power-on registers 206a and 206b for the occurrence of subsequent device turn-on condition.

Accessing The Real-Time Clock 92

Referring now to FIG. 6, depicted there are waveforms various electrical signals that are required for operating real-time clock IC 92 which conforms to the Intel protoc described above. The upper one-third of FIG. 6 depicts address strobe ("AS") signal waveform 252, a chip select ("CS signal waveform 254, and multiplexed address/data input/outp AD₀-AD signal waveforms 256. The AS waveform 252, the waveform 254, and the AD -AD waveforms 256 remain the sa regardless of whether data is being read from or is being writt to the real-time clock IC 92 coupled to the system log controller 24 via the I/O bus 48. The center one-third of FIG. 6 depicts particular waveforms of signals required for reading data from the real-time clock IC 92, i.e. a data strobe read ("DS ') waveform 262 and a read/write read ("R/W,") signal waveform 264. The lower one-third of FIG. 6 depicts particular waveforms of signals required for writing data to the real-time clock IC 92, i.e. a data strobe read ("DS_W") waveform 272 and a read/write ("R/W_r") signal waveform 274. Either the waveforms 262 and 264 or the waveforms 272 and 274 are applied to the same pins of the real-time clock IC 92. The respective shapes of the waveforms 262 and 264 or 272 and 274 determine whether the real-time clock IC 92 receives and stores data from AD₀-AD^ signal lines included in the I/O bus 48, or transmits data over the AD₀-AD- signal lines to the system logic controller 24. FIG. 6 depicts the waveforms 252, 254, 256, 262, 264, 272 and 274 throughout an entire bus cycle consisting of the address phase and the data-transfer phase required to access the real-time clock IC 92. A vertical line 282 in FIG. 6 indicates the beginning of the bus cycle's address phase. A vertical line 284 in FIG. 6 indicates the end of the bus cycle's address phase and the beginning of the bus cycle's data-transfer phase. A vertical line 286 in FIG. 6 indicates the end of the bus cycle's data transfer phase. The bus cycle for the address phase of the real-time clock IC 92 lying between the vertical lines 282 and 284 in FIG. 6 is equivalent to a single cycle of the I/O bus 48. The bus cycle for the data-transfer phase of the real-time clock IC 92 lying between the vertical lines 284 and 286 of FIG. 6 is equivalent to an immediately subsequent single cycle of the I/O bus 48. Waveforms for standard signals I/O read ("IOR") and I/O write ("IOW") generated by the system logic controller 24 during the bus cycle of the data-transfer phase of the real-time clock IC 92 between the vertical lines 284 and 286 are respectively equivalent to the DS waveforms 262 or 272, and R/W waveforms 264 or 274 required by the real-time clock IC 92. Consequently the signals IOR and IOW may be applied directly to the real-time clock IC 92 during the data-transfer phase between the vertical lines 284 and 286 respectively as the DS signal, and R/W signal required for proper operation of the real-time clock IC 92. Th system logic controller 24 suppresses transmission of the IOR an IOW to the real-time clock IC 92 during the address phase betwee the vertical lines 282 and 284. Moreover the I/O bus 48 include the AD₀-AD₇ signal lines. Thus, the only signals required by th real-time clock IC 92 which are missing from those signal normally included in the I/O bus 48 generated by the system logi controller 24 are the CS signal and the AS signal.

With regard to the AS signal, a bus address latch enabl ("BALE") signal generated by the system logic controller 24 i equivalent to the AS signal required during the address phase o the bus cycle for the real-time clock IC 92. However, becaus the BALE signal normally occurs during every cycle of the I/O bu 48, the standard BALE signal generated by the system logi controller 24 is not equivalent to the AS signal required by th real-time clock IC 92 during the data-transfer phase of the bu cycle lying between the vertical lines 284 and 286. However because generation of the CS signal required by the real-tim clock IC 92 requires that the system logic controller 24 decod address signals for the real-time clock IC 92 transmitted fro the CPU 12, the system logic controller 24 in accordance with th present invention suppresses transmission of the BALE signal o the I/O bus 48 during the cycle of the I/O bus 48 immediatel following a cycle in which the system logic controller 2 generates the CS signal, i.e. the cycle of the I/O bus 4 immediately following that in which the system logic controlle 24 first generates the CS signal. Consequently, the system logi controller 24 of the present invention need not use a separat pin to provide the AS signal to the real-time clock IC 92 Rather, the BALE signal line originating at the system logi controller 24 may be applied directly to the real-time clock I 92 as the AS signal required for proper operation of that IC. Industrial Applicability

Using the invention disclosed herein for managing power consumption by a computer 10 requires proper initialization of the various registers listed in FIG. 3 in accordance with the description set forth herein above. In establishing a particular Power Management Regime during booting of the computer 10, the system logic controller 24, as described previously, sequentially broadcasts various numerical values from the power management data storage array 140 to the registers listed in FIG. 3. During this broadcasting process the system logic controller 24 must observe a certain precedence in broadcasting numerical values. Specifically, one (1) of the three (3) possible numerical values must not be broadcast to the System Management Mode Master Timer Control register 240H until near the end of the broadcasting sequence. Similarly, one (1) of the (3) possible numerical values must not be broadcast to the SMI Mode Control register 200H until the very end of the broadcasting sequence.

If either the Standard or Extended Power Management Regime is established during booting of the computer 10, SMI interrupts will be enabled by the numerical value stored into register 200H, and the various power management modes, i.e. the Full System Speed Mode, the System Doze Mode, the System Sleep Mode, the Five Volts Suspend Mode, and the Zero Volt Suspend Mode, will be enabled by numerical values stored into register 24AH. Then, during operation of the computer while the computer program executed by the CPU 12 accesses a device, e.g. the hard disk, frequently enough, the computer 10 will maintain the device in a power on state. For example, each time the computer program executed by the CPU 12 access the hard disk, the auto-event decode logic circuit 172 will transmit a trigger signal to a particular one of the power management timer 144a, 144b ^{• • •} 144n, e,g. power management timer 144a, which causes the power management timer 144a to re-initialize the time-out interval for the hard disk. If, however, the hard disk remains idle for a sufficiently long interval of time, then an output signal from the power management timer 144a sets a bit in the device power-off register 202a, and the system logic controller 24 transmits a SMI to the CPU 12. Upon receiving the SMI, the CPU 12 commences execution of a power management routine which read the device power-off registers 202a and 202b and thereb determines that the event which caused the SMI is the timing-ou of the hard disk power management timer 144a. Upon determinin that the hard disk is to be turned off, the power managemen routine executes a prescribed sequence of operations which i unique for the hard-disk drive to turn the hard disk drive off, and thereby conserve the electrical power which the hard dis drive would otherwise consume. If after the hard disk drive has been turned off a compute program executed by the CPU 12 attempts to read or write tha device, then the auto-event decode logic circuit 172 transmit an output signal via the device power-on signal lines 204a, 204 thru 204n which sets a bit in the device power-on register 206a, and the system logic controller 24 transmits a SMI to the CPU 12. Upon receiving the SMI, the CPU 12 again commences execution o the power management routine which reads the device power-o registers 206a and 206b and thereby determines that the hard dis needs to be turned on. Upon determining that the hard disk i to be turned on, the power management routine executes a uniqu sequence of operations that causes the hard disk to resum operating.

While ROMs are presently preferred for the power managemen data storage array 140 and the device addresses 184a, 184b thr 184n-2 included in the power management unit 128 of the syste logic controller 24, it is readily apparent that other forms o non-volatile memory such as an electrically erasable memory o "FLASH" memory could also be used for storing such data.

Although the present invention has been described in term of the presently preferred embodiment, it is to be understoo that such disclosure is purely illustrative and is not to b interpreted as limiting. Consequently, without departing fro the spirit and scope of the invention, various alterations, modifications, and/or alternative applications of the inventio will, no doubt, be suggested to those skilled in the art afte having read the preceding disclosure. Accordingly, it is intende that the following claims be interpreted as encompassing al alterations, modifications, or alternative applications as fall within the true spirit and scope of the invention.

Claims

The ClaimsWhat is claimed is:

1. An improved system logic controller for use in digital computer that includes a central processing unit whic is coupled to a CPU bus having CPU address lines and CPU dat lines; said system logic controller also being coupled to the CP address lines and to the CPU data lines, and including both a CP data interface controller and a power management unit particular ly adapted for use in regulating electrical power consumption b the digital computer; wherein the improvement comprises: a plurality of power management control registers locate within said system logic controller for receiving control dat used in regulating electrical power consumption by the digita computer; a power management data storage array located within sai system logic controller that stores at least two different set of control data, one or the other of which sets of control dat if transferred into said plurality of power management contro registers establishes either one or another power managemen operating regime for the digital computer; and power management data broadcast means located within sai system logic controller which is responsive to a command from th central processing unit for selecting a particular set of th control data from said power management data storage array, an transferring the selected set of control data into said pluralit of power management control registers thereby establishing selected power management operating regime.

2. The improved system logic controller of claim 1 wherei said power management data storage array included in said syste logic controller is a read only memory ("ROM") .

3. The improved system logic controller of claim 1 wherei said system logic controller further comprises: a plurality of power management timers which respectivel include one of said power management control registers, sai power management control registers included in said powe management timers respectively receiving control data from the power management data storage array that represent time intervals which, if respectively exceeded, result in said power management timers generating a power management time-out condition.

4. The improved system logic controller of claim 3 wherein said system logic controller further comprises: a master clock which generates timing signals that are supplied to said power management timers, and wherein supplying of such timing signals to the power management timers is inhibited until after the control data has been transferred from the power management data storage array into the power management control registers respectively included in each of the power management timers.

5. The improved system logic controller of claim 3 wherein the digital computer includes a device whose operation may be suspended and resumed by a computer program executed by the central processing unit, the device also being addressable by a computer program executed by the central processing unit for exchanging data with the device, said system logic controller further comprising: auto-event monitoring logic circuit which upon detecting that the computer program executed by the central processing unit has addressed the device causes the system logic controller to establish a new time at which a particular one of said power management timers that is associated with the device will generate a power management time-out condition.

6. The improved system logic controller of claim 5 wherein the central processing unit upon receiving a system management interrupt begins executing a power management routine which regulates electrical power consumption by the digital computer, said system logic controller further comprising: a device power-off register which may be read by a computer program executed by the central processing unit, said device power-off register having a pre-specified bit associated with the particular power management timer that is associated with the device, said bit in said device power-off register being set a power management time-out condition occurs in the particul power management timer; and

SMI generating means for generating a system manageme interrupt in response to setting of the pre-specified bit in sa device power-off register.

7. The improved system logic controller of claim 5 where all bits that have been set in the device power-off register a cleared upon reading of the device power-off register.

8. The improved system logic controller of claim 5 where said auto-event monitoring logic circuit further includes: device operating status monitoring means for preserving operating status record for the device which indicates if t device is operating or if the operation of the device has be suspended; and a device power-on register which may be read by a comput program executed by the central processing unit, said devi power-on register having a pre-specified bit that is associat with the device which is bit set to indicate that operation the device is to be resumed if a computer program executed by t central processing unit addresses the device while the devi operating status monitoring means indicates that the device not operating; said SMI generating means generating a system manageme interrupt in response to setting of the pre-specified bit in sa device power-on register.

9. The improved system logic controller of claim 8 where all bits that have been set in the device power-on register a cleared upon reading of the device power-on register.

10. An improved system logic controller for use in digital computer that includes a central processing unit whi is coupled to a CPU bus having CPU address lines and CPU da lines; said system logic controller also being coupled to the C address lines and to the CPU data lines, and including both a C data interface controller and a power management unit particu¬ larly adapted for use in regulating electrical power consumption by the digital computer, the digital computer including a device whose operation may be suspended and resumed by a computer program executed by the central processing unit, the device also being addressable by a computer program executed by the central processing unit for exchanging data with the device; wherein the improvement comprises: a plurality of power management timers located within said system logic controller which respectively generate a power management time-out condition upon expiration of a pre-estab¬ lished time interval; and auto-event monitoring logic circuit located within said system logic controller which upon detecting that the computer program executed by the central processing unit has addressed the device causes the system logic controller to establish a new time at which a particular one of said power management timers that is associated with the device will generate a power management time-out condition.

11. The improved system logic controller of claim 10 wherein the central processing unit upon receiving a system management interrupt begins executing a power management routine which regulates electrical power consumption by the digital computer, said system logic controller further comprising: a device power-off register which may be read by a computer program executed by the central processing unit, said device power-off register having a pre-specified bit associated with the particular power management timer that is associated with the device, said bit in said device power-off register being set if a power management time-out condition occurs in the particular power management timer; and

SMI generating means for generating a system management interrupt in response to setting of the pre-specified bit in said device power-off register.

12. The improved system logic controller of claim 11 wherein all bits that have been set in the device power-off register are cleared upon reading of the device power-o register.

13. The improved system logic controller of claim wherein said auto-event monitoring logic circuit furth includes: device operating status monitoring means for preserving operating status record for the device which indicates if t device is operating or if the operation of the device has be suspended; and a device power-on register which may be read by a comput program executed by the central processing unit, said devi power-on register having a pre-specified bit that is associat with the device which is bit set to indicate that operation the device is to be resumed if a computer program executed by t central processing unit addresses the device while the devi operating status monitoring means indicates that the device not operating; said SMI generating means generating a system manageme interrupt in response to setting of the pre-specified bit in sa device power-on register.

14. The improved system logic controller of claim wherein all bits that have been set in the device power- register are cleared upon reading of the device power- register.

15. The improved system logic controller of claim wherein said auto-event monitoring logic circuit furth includes: device operating status monitoring means for preserving operating status record for the device which indicates if t device is operating or if the operation of the device has be suspended; and a device power-on register which may be read by a comput program executed by the central processing unit, said devi power-on register having a pre-specified bit that is associat with the device which is bit set to indicate that operation the device is to be resumed if a computer program executed by the central processing unit addresses the device while the device operating status monitoring means indicates that the device is not operating; said SMI generating means generating a system management interrupt in response to setting of the pre-specified bit in said device power-on register.

16. The improved system logic controller of claim 15 wherein all bits that have been set in the device power-on register are cleared upon reading of the device power-on register.

17. An improved method by which a system logic controller included in a digital computer exchanges data with a real-time clock integrated circuit which is coupled to the system logic controller by an I/O bus included in the digital computer, the I/O bus including standard signal lines and operating in accordance with a bus protocol in which for each exchange of data via the I/O bus a signal normally occurs on a BALE signal line included in the I/O bus during every I/O bus data transfer cycle, the real-time clock integrated circuit operating in accordance with a protocol in which during each exchange of data the real-time clock integrated circuit may receive a signal on the BALE signal line during only a first of two immediately succes¬ sive I/O bus data transfer cycles, the improved method comprising the step of: if the system logic controller accesses the real-time clock integrated circuit via only the standard signal lines of the I/O bus: a. during the first I/O bus data transfer cycle the system logic controller transmitting a signal to the real-time clock integrated circuit via the BALE signal line; and b. during the immediately successive I/O bus data trans¬ fer cycle the system logic controller suppressing transmission of a signal to the real-time clock integrated circuit via the BALE signal line; whereby the system logic controller exchanges data with t real-time clock integrated circuit using only the standard sign lines normally included in the I/O bus.