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WO1996013056A2 - Hermetically sealed hybrid ceramic integrated circuit package - Google Patents

Hermetically sealed hybrid ceramic integrated circuit package Download PDF

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Publication number
WO1996013056A2
WO1996013056A2 PCT/US1995/012809 US9512809W WO9613056A2 WO 1996013056 A2 WO1996013056 A2 WO 1996013056A2 US 9512809 W US9512809 W US 9512809W WO 9613056 A2 WO9613056 A2 WO 9613056A2
Authority
WO
WIPO (PCT)
Prior art keywords
ceramic
ceramic base
integrated circuit
central portion
thermal conductivity
Prior art date
Application number
PCT/US1995/012809
Other languages
French (fr)
Other versions
WO1996013056A3 (en
Inventor
Satya Chillara
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to EP95937354A priority Critical patent/EP0740850A1/en
Publication of WO1996013056A2 publication Critical patent/WO1996013056A2/en
Publication of WO1996013056A3 publication Critical patent/WO1996013056A3/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3731—Ceramic materials or glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Definitions

  • the present invenuon relates generally to an integrated circuit package and more specifically to a hybrid ceramic base for use in, for example, an hermetically sealed integrated circuit package
  • Package 10 includes a ceramic base 12 having a recessed central portion 14, and a peripheral portion 16 An integrated circuit die 18 is attached to ceramic base 12 in the recessed central portion 14 using a die attaching adhesive 20 As shown in Figure 1 , a leadframe 22 is attached to the peripheral portion of ceramic base 12 using a glass sealing material 24 and an array ot bonding w ires 26 electrically connects die 18 to leadframe 22 Finally, a ceramic lid 2S is attached to leadframe 22 directly above the peripheral portion of ceramic base 12 herrnet ⁇ call> sealing die 18 within a bpace defined by ceramic lid 28 and the recessed portion ol ceramic base 12 O 96/13056
  • prior art ceramic bases like base 12, have been made in one continuous piece using one of two different types of ceramic
  • the first type of ceramic material is a low thermal conductivity ceramic, such as alumina or mullite This material has the advantage of low cost, however, its low thermal conductivity restricts the heat dissipating characteristics of a base made from this material
  • the second type of ceramic is a high thermal conductivity ceramic such as aluminum nitride (A1N), beryllium oxide (BeO), or silicon carbide This material has the advantage of high thermal conductivity, however, it is substantially more expensive than the low thermal conductivity ceramic Because prior art ceramic bases have been made from either one or the other of these two materials there has been a definite trade off between cost and thermal performance of the ceramic base
  • the present invention provides a hybrid ceramic base which provides high thermal conductivity at a low cost
  • a ceramic base for use in. for example, an hermetically sealed integrated circuit package
  • the ceramic base includes an outermost circumferential peripheral portion having a top surface, a bottom surface, and an inner circumferential edge surface
  • the peripheral portion of the ceramic base is adapted to receive a conventional integrated circuit package leadframe and ceramic lid forming the hermetically sealed integrated circuit package
  • the peripheral portion of the ceramic base is made from a low thermal conductivity and therefore less costly ceramic material
  • the ceramic base also includes a central portion surrounded by the peripheral portion
  • the central portion has a top surface, a bottom surface, and an outer circumferential edge surface
  • the central portion of the ceramic base is adapted to have an integrated circuit die attached directly to the top surface of the central portion
  • the central portion of the ceramic base is made from a high thermal conductivity ceramic material thereby providing a more efficient heat sink Together the two ceramic portions provide a more economical, higher efficiency heat sink for the overall package.
  • the outer circumferential edge surface of the central portion of the ceramic base is attached to the inner circumferential edge surface of the peripheral portion of the ceramic base with the top surface of the central portion recessed with respect to the top surface of the peripheral portion using a devit ⁇ fying glass sealing material.
  • a separate heat sink is attached to the bottom surface of the central portion of the ceramic base, further improving the thermal dissipating capability of the base.
  • Figure 1 is a diagrammatic cross sectional view of a prior art hermetically sealed ceramic integrated circuit package
  • Figure 2 is a diagrammatic cross sectional view of a ceramic base designed in accordance with the present invention for use in, for example, an hermeticalh sealed integrated circuit package;
  • Figure 3 is a diagrammatic cross sectional view of the ceramic base of Figure 2 including additional integrated circuit package components attached to the base
  • Figure 4 is a diagrammatic cross sectional view of an integrated circuit package designed and assembled in accordance with the present invention including a heat sink attached to the bottom of the ceramic base.
  • ceramic base 30 which illustrates a ceramic base for use in, for example, an hermetically sealed integrated circuit package and generally designated by reference numeral 30.
  • ceramic base 30 includes an outermost circumferential peripheral portion 32 having a top surface 34, a bottom surface 36 and an inner circumferential edge surface 38.
  • Top surface 34 of peripheral portion 32 is adapted to have a conventional integrated circuit package leadframe (not shown in Figure 1 ) attached to it using a conventional and readily available adhesive material such as vitrifying glass sealing material 40.
  • This material is typically screen printed onto peripheral portion 32 using conventional and readily available screen printing methods
  • Peripheral portion 32 of ceramic base 30, in accordance with the present invention is made from any suitable low thermal conductivity ceramic material such as alumina or mulhte.
  • ceramic base 30 also includes a central portion 42 having a ten surface 44. a bottom surface 46, and an outer circumferential edge surface 48 Central portion 42 is adapted to have an integrated circuit die (not shown in Figure 2 ) attached to top surface 44 using a conventional and readily available die attaching adhesive material (also not shown in Figure 2).
  • Central portion 42 of ceramic base 30, in accordance w ith the present invention, is made from any suitable high thermal conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide In the particular embodiment shown in Figure 2, central portion 42 of ceramic base 30 has a thickness less than the thickness of peripheral portion 32.
  • central portion 42 is attached to peripheral portion 32 such that the top surface of central portion 42 is recessed with respect to the top surface of peripheral portion 32. This recessed space directly above central portion 42 provides space for an integrated circuit die (not shown in Figure 2).
  • the outer circumferential edge surface 48 of central portion 42 is attached to the inner circumferential edge surface 38 of peripheral portion 32 using a devitrifying glass sealing material 50. This devitrifying glass sealing material 50 forms a permanent bond such that sealing material 50 will not melt during subsequent high temperature manufacturing processes of the production of an integrated circuit package using ceramic base 30.
  • the present invention of using a high thermal conductivity ceramic for the central portion of a ceramic base and using a low thermal conductivity ceramic provides a substantially less expensive ceramic base with good thermal conductivity This is because, as described above, the cost of high conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide is much higher than the cost of low conductivity ceramic material such as alumina or mullite.
  • the overall cost of the ceramic base of the present invention is substantially less than the cost of a prior art high thermal conductivity ceramic base made entirely from high thermal conductivity ceramic material while maintaining a significant percentage of the improvement in heat dissipating capability.
  • thermal resistance or Theta JA of a prior art package using a ceramic base made entirely from high thermal conductivity ceramic provides a 15.5% improvement in thermal resistance as compared to a prior art package using a ceramic base made entirely from low thermal conductivity ceramic This improvement comes at a relatively high cost with the high thermal conductivity ceramic base being approximately thirty five times the cost of the low thermal conductivity material.
  • an 8.6% improvement in thermal resistance is provided at a cost approximately one third that of a ceramic base made entirely from the high thermal conductivity ceramic
  • an external heat sink 52 which for example may be made from aluminum or copper, may be attached to the bottom surface 46 of central portion 42 of ceramic base 30, thereby improving the thermal resistance of the package to achieve essentially the same improvement made by using a ceramic base made entirely from high thermal conductivity ceramic
  • Heat sinks for example the ones made from aluminum or copper, are relatiu K inexpensive and are conventional and readily available Therefore, a ceramic lu ⁇ designed in accordance with the present invention including a heat sink made t: > > ⁇ aluminum or copper is able to achieve the same thermal characteristics of a p ⁇ ci . ceramic base made entirely from high thermal conductivity ceramic mate ⁇ al at a t. • • of the cost Specifically, applicant has found that a ceramic base designed accordance with the present invention using aluminum nitride for the high therm. ⁇ conductivity central portion of the base, alumina for the low thermal conduciiv ir.
  • peripheral portion of the base and aluminum or copper for the heat sink attached to the bottom of the ceramic base may be produced at a cost approximately forty percent of that of a ceramic base made entirely from high thermal conductiv ity aluminum nitride ceramic while providing an equivalent theta JA or thermal resistance
  • Ceramic base 30 includes outermost circumferential peripheral portion 32 having top surface 34, bottom surface 36 and innei O 96/13056
  • Peripheral portion 32 of ceramic base 30, in accordance with the present invention is made from a low thermal conductivity ceramic material such as alumina or mullite, as stated previously Ceramic base 30 also includes central portion 42 having top surface 44, bottom surface 46, and outer circumferential edge surface 48. Central portion 42 of ceramic base 30, in accordance with the present invention, is made from a high thermal conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide, also as stated previously
  • an integrated circuit die 56 having a bottom surface 58 and a top surface 60 including a plurality of die input/output pads 62 is attached to top surface 44 of central portion 42 using a conventional and readily available die attaching adhesive material 64.
  • a leadframe 66 having a top surface 68, a bottom surface 70, and including an array of electrically conductive leads 72 is attached to top surface 34 of peripheral portion 32 using a conventional and readily available adhesive material such as vitrifying glass sealing material 40 This material is typically screen printed onto peripheral portion 32 using conventional and readily available screen printing methods.
  • the input/output pads 62 on integrated circuit die 56 are elect ⁇ calh connected to leads 72 on leadframe 66 using conventional wire bonding equipment and techniques to form an array of bonding wires 74
  • a ceramic lid 76 is attached to the top surface 68 of leadframe 66 directly above the peripheral portion 32 of ceramic base 30 using a conventional and readily available adhesive material such as vit ⁇ f ing glass sealing material 78.
  • heat sink 52 may be attached to the bottom surface 46 of the central portion of ceramic base 30 further improving the heat dissipating characteristics of the integrated circuit package 54 as described above
  • the low thermal conductivity ceramic materials desc ⁇ bed (such as alumina or mullite) have a thermal resistance in the range of 5-20 w/mk
  • the high thermal conductiv ity materials described such as aluminum nitride, beryllium oxide, or silicon carbide
  • these ranges of thermal resistance are tv pical for high and low thermal conductivity ceramics, it should be understood that these ranges are given as examples and the present invention is not limited to materials m these thermal resistance ranges In fact, the present invention would equallv applv regardless of the specific thermal resistance of the materials used so long as two materials having different thermal resistance are used to make up the base

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A ceramic base (30) for use in, for example, a hermetically sealed integrated circuit package (54) is herein disclosed. The ceramic base (30) includes an outermost circumferential peripheral portion (32) having a top surface (34), a bottom surface (36), and an inner circumferential edge surface (38). The peripheral portion (32) of the ceramic base (30) is adapted to receive a conventional integrated circuit package leadframe (22) and ceramic lid (28) forming the hermetically sealed integrated circuit package (54). Also, in accordance with the present invention, the peripheral portion (32) of the ceramic base is made from a low thermal conductivity ceramic material. The ceramic base also includes a central portion (42) surrounded by the peripheral portion (32). The central portion (42) has a top surface (44), a bottom surface (46), and an outer circumferential edge surface (48). The central portion (42) of the ceramic base (30) is adapted to have an integrated circuit die (18) attached directly to the top surface (44) of the central portion (42). And in accordance with the present invention, the central portion (42) of the ceramic base (30) is made from a high thermal conductivity ceramic material thereby reducing the thermal resistance of the integrated circuit package (54).

Description

O 96/13056 PC17US95/12809
HERMETICALLY SEALED HYBRID CERAMIC INTEGRATED CIRCUIT PACKAGE
BACKGROUND OF THE INVENTION
The present invenuon relates generally to an integrated circuit package and more specifically to a hybrid ceramic base for use in, for example, an hermetically sealed integrated circuit package
In the field of integrated circuit packaging, the cost of the components making up the package is a major concern Any reduction in the cost of these components making up the package can provide a significant commercial advantage To this end, the packaging of integrated circuits is continuously being improved to prov ide more cost effective designs and methods for producing integrated circuit packages
Referring to Figure 1 , the prior art approaches to providing a ceramic hermetically sealed integrated circuit package, generally designated b\ reference numeral 10, will be described Package 10 includes a ceramic base 12 having a recessed central portion 14, and a peripheral portion 16 An integrated circuit die 18 is attached to ceramic base 12 in the recessed central portion 14 using a die attaching adhesive 20 As shown in Figure 1 , a leadframe 22 is attached to the peripheral portion of ceramic base 12 using a glass sealing material 24 and an array ot bonding w ires 26 electrically connects die 18 to leadframe 22 Finally, a ceramic lid 2S is attached to leadframe 22 directly above the peripheral portion of ceramic base 12 herrnetιcall> sealing die 18 within a bpace defined by ceramic lid 28 and the recessed portion ol ceramic base 12 O 96/13056
In the case of ceramic hermetically sealed integrated circuit packages, prior art ceramic bases, like base 12, have been made in one continuous piece using one of two different types of ceramic The first type of ceramic material is a low thermal conductivity ceramic, such as alumina or mullite This material has the advantage of low cost, however, its low thermal conductivity restricts the heat dissipating characteristics of a base made from this material The second type of ceramic is a high thermal conductivity ceramic such as aluminum nitride (A1N), beryllium oxide (BeO), or silicon carbide This material has the advantage of high thermal conductivity, however, it is substantially more expensive than the low thermal conductivity ceramic Because prior art ceramic bases have been made from either one or the other of these two materials there has been a definite trade off between cost and thermal performance of the ceramic base The present invention provides a hybrid ceramic base which provides high thermal conductivity at a low cost
SUMMARY OF THE INVENTION
As will be described in more detail hereinafter, a ceramic base for use in. for example, an hermetically sealed integrated circuit package is disclosed The ceramic base includes an outermost circumferential peripheral portion having a top surface, a bottom surface, and an inner circumferential edge surface The peripheral portion of the ceramic base is adapted to receive a conventional integrated circuit package leadframe and ceramic lid forming the hermetically sealed integrated circuit package
Also, in accordance with the present invention, the peripheral portion of the ceramic base is made from a low thermal conductivity and therefore less costly ceramic material The ceramic base also includes a central portion surrounded by the peripheral portion The central portion has a top surface, a bottom surface, and an outer circumferential edge surface The central portion of the ceramic base is adapted to have an integrated circuit die attached directly to the top surface of the central portion In accordance w ith the present invention, the central portion of the ceramic base is made from a high thermal conductivity ceramic material thereby providing a more efficient heat sink Together the two ceramic portions provide a more economical, higher efficiency heat sink for the overall package.
In one embodiment of the present invention, the outer circumferential edge surface of the central portion of the ceramic base is attached to the inner circumferential edge surface of the peripheral portion of the ceramic base with the top surface of the central portion recessed with respect to the top surface of the peripheral portion using a devitπfying glass sealing material. This permanently attaches the central portion of the ceramic base to the peripheral portion of the ceramic base such that the sealing material will not melt during subsequent processes in the production of the integrated circuit package In another embodiment of the present invention, a separate heat sink is attached to the bottom surface of the central portion of the ceramic base, further improving the thermal dissipating capability of the base.
BRIEF DESCRIPTION OF THE DRAWINGS
The features of the present invention may best be understood by reference to the following description of the presently preferred embodiments together w ith the accompanying drawings in which.
Figure 1 is a diagrammatic cross sectional view of a prior art hermetically sealed ceramic integrated circuit package,
Figure 2 is a diagrammatic cross sectional view of a ceramic base designed in accordance with the present invention for use in, for example, an hermeticalh sealed integrated circuit package;
Figure 3 is a diagrammatic cross sectional view of the ceramic base of Figure 2 including additional integrated circuit package components attached to the base, and Figure 4 is a diagrammatic cross sectional view of an integrated circuit package designed and assembled in accordance with the present invention including a heat sink attached to the bottom of the ceramic base.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Inasmuch as Figure 1 was discussed previously, attention is directed to Figure
2 which illustrates a ceramic base for use in, for example, an hermetically sealed integrated circuit package and generally designated by reference numeral 30. In accordance with the present invention, ceramic base 30 includes an outermost circumferential peripheral portion 32 having a top surface 34, a bottom surface 36 and an inner circumferential edge surface 38. Top surface 34 of peripheral portion 32 is adapted to have a conventional integrated circuit package leadframe (not shown in Figure 1 ) attached to it using a conventional and readily available adhesive material such as vitrifying glass sealing material 40. This material is typically screen printed onto peripheral portion 32 using conventional and readily available screen printing methods Peripheral portion 32 of ceramic base 30, in accordance with the present invention, is made from any suitable low thermal conductivity ceramic material such as alumina or mulhte.
Still referring to Figure 2 and in accordance with the present invention, ceramic base 30 also includes a central portion 42 having a ten surface 44. a bottom surface 46, and an outer circumferential edge surface 48 Central portion 42 is adapted to have an integrated circuit die (not shown in Figure 2 ) attached to top surface 44 using a conventional and readily available die attaching adhesive material (also not shown in Figure 2). Central portion 42 of ceramic base 30, in accordance w ith the present invention, is made from any suitable high thermal conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide In the particular embodiment shown in Figure 2, central portion 42 of ceramic base 30 has a thickness less than the thickness of peripheral portion 32. Also, central portion 42 is attached to peripheral portion 32 such that the top surface of central portion 42 is recessed with respect to the top surface of peripheral portion 32. This recessed space directly above central portion 42 provides space for an integrated circuit die (not shown in Figure 2). In this embodiment, the outer circumferential edge surface 48 of central portion 42 is attached to the inner circumferential edge surface 38 of peripheral portion 32 using a devitrifying glass sealing material 50. This devitrifying glass sealing material 50 forms a permanent bond such that sealing material 50 will not melt during subsequent high temperature manufacturing processes of the production of an integrated circuit package using ceramic base 30.
The present invention of using a high thermal conductivity ceramic for the central portion of a ceramic base and using a low thermal conductivity ceramic provides a substantially less expensive ceramic base with good thermal conductivity This is because, as described above, the cost of high conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide is much higher than the cost of low conductivity ceramic material such as alumina or mullite. By using the expensive high thermal conductivity material only in the central portion of the ceramic base where it is most effective for dissipating heat and using inexpensive low thermal conductivity ceramic material for the peripheral portion of the ceramic base, which is the majority of the material required, the overall cost of the ceramic base of the present invention is substantially less than the cost of a prior art high thermal conductivity ceramic base made entirely from high thermal conductivity ceramic material while maintaining a significant percentage of the improvement in heat dissipating capability.
For example, applicant has found that for a 16 LD CDIP package, the thermal resistance or Theta JA of a prior art package using a ceramic base made entirely from high thermal conductivity ceramic provides a 15.5% improvement in thermal resistance as compared to a prior art package using a ceramic base made entirely from low thermal conductivity ceramic This improvement comes at a relatively high cost with the high thermal conductivity ceramic base being approximately thirty five times the cost of the low thermal conductivity material. However, applicant has found that using a ceramic base designed in accordance with the present invention, an 8.6% improvement in thermal resistance is provided at a cost approximately one third that of a ceramic base made entirely from the high thermal conductivity ceramic Furthermore, as shown in Figure 2, an external heat sink 52, which for example may be made from aluminum or copper, may be attached to the bottom surface 46 of central portion 42 of ceramic base 30, thereby improving the thermal resistance of the package to achieve essentially the same improvement made by using a ceramic base made entirely from high thermal conductivity ceramic
Heat sinks, for example the ones made from aluminum or copper, are relatiu K inexpensive and are conventional and readily available Therefore, a ceramic lu^ designed in accordance with the present invention including a heat sink made t: > > ■ aluminum or copper is able to achieve the same thermal characteristics of a pπci . ceramic base made entirely from high thermal conductivity ceramic mateπal at a t. •• of the cost Specifically, applicant has found that a ceramic base designed accordance with the present invention using aluminum nitride for the high therm. ■ conductivity central portion of the base, alumina for the low thermal conduciiv ir. peripheral portion of the base and aluminum or copper for the heat sink attached to the bottom of the ceramic base, may be produced at a cost approximately forty percent of that of a ceramic base made entirely from high thermal conductiv ity aluminum nitride ceramic while providing an equivalent theta JA or thermal resistance
Referring now to Figures 3 and 4, a method of manufacturing an integrated circuit package designed in accordance with the present invention and generallv designated by reference numeral 54 will be described. As described above in detail, a ceramic base 30 is provided. Ceramic base 30 includes outermost circumferential peripheral portion 32 having top surface 34, bottom surface 36 and innei O 96/13056
circumferential edge surface 38. Peripheral portion 32 of ceramic base 30, in accordance with the present invention, is made from a low thermal conductivity ceramic material such as alumina or mullite, as stated previously Ceramic base 30 also includes central portion 42 having top surface 44, bottom surface 46, and outer circumferential edge surface 48. Central portion 42 of ceramic base 30, in accordance with the present invention, is made from a high thermal conductivity ceramic material such as aluminum nitride, beryllium oxide, or silicon carbide, also as stated previously
Referring to Figure 3, an integrated circuit die 56 having a bottom surface 58 and a top surface 60 including a plurality of die input/output pads 62 is attached to top surface 44 of central portion 42 using a conventional and readily available die attaching adhesive material 64. Also, a leadframe 66 having a top surface 68, a bottom surface 70, and including an array of electrically conductive leads 72 is attached to top surface 34 of peripheral portion 32 using a conventional and readily available adhesive material such as vitrifying glass sealing material 40 This material is typically screen printed onto peripheral portion 32 using conventional and readily available screen printing methods. Next, the input/output pads 62 on integrated circuit die 56 are electπcalh connected to leads 72 on leadframe 66 using conventional wire bonding equipment and techniques to form an array of bonding wires 74
Referring now to Figure 4, a ceramic lid 76 is attached to the top surface 68 of leadframe 66 directly above the peripheral portion 32 of ceramic base 30 using a conventional and readily available adhesive material such as vitπf ing glass sealing material 78. This hermetically seals integrated circuit 56 within a space formed between the central portion 42 of ceramic base 30 and ceramic lid 76 Optionally, heat sink 52 may be attached to the bottom surface 46 of the central portion of ceramic base 30 further improving the heat dissipating characteristics of the integrated circuit package 54 as described above Although only a few embodiments of the present invention have been described in detail, it should be understood that the present invention may be embodied in many other specific forms without departing from the spirit and scope of the invention For instance, although the ceramic base has been described as having the central portion recessed with respect to the peripheral portion, this is not a requirement of the present invention Also, although the ceramic base has been described as providing space for a single integrated circuit die to be attached to the ceramic base, it should be understood that the present invention would equally apply to a ceramic base designed for a multi- chip package in which multiple die are attached to the ceramic base Furthermore, although the ceramic base in the examples given has its central portion fully surrounded by the peripheral portion, it should be understood that this is not a requirement of the present invention The present invention would apply to a wide v aπetv of specif ic configurations so long as materials of differing thermal conductivity arc used to make up the base
In the examples given for the present invention, the low thermal conductivity ceramic materials descπbed (such as alumina or mullite) have a thermal resistance in the range of 5-20 w/mk The high thermal conductiv ity materials described ( such as aluminum nitride, beryllium oxide, or silicon carbide) have a thermal resistance in the range of 150-218 w/km Although these ranges of thermal resistance are tv pical for high and low thermal conductivity ceramics, it should be understood that these ranges are given as examples and the present invention is not limited to materials m these thermal resistance ranges In fact, the present invention would equallv applv regardless of the specific thermal resistance of the materials used so long as two materials having different thermal resistance are used to make up the base
Therefore, the present examples are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but mav be modified within the scope of the appended claims

Claims

O 96/13056WHAT IS CLAIMED IS:
1 . A ceramic base for use in, for example, an hermetically sealed integrated circuit package, said base comprising; a) an outermost circumferential peripheral portion having a top surface, a bottom surface, and an inner circumferential edge surface, said peripheral portion of said ceramic base being adapted to receive a conventional integrated circuit package leadframe and ceramic lid forming said hermetically sealed integrated circuit package and said peripheral portion of said ceramic base being made from a low thermal conductivity ceramic material, and b) a central portion surrounded by said peripheral portion, said central portion having a top surface , a bottom surface, and an outer circumferential edge surface, said central portion of said ceramic base being adapted to have an integrated circuit die attached directly to said top surface of said central portion and said central portion of said ceramic base being made from a high thermal conductivity ceramic material thereby reducing the thermal resistance of said integrated circuit package.
2. A ceramic base as set forth in Claim 1 wherein said low thermal conductivity ceramic is made from alumina.
3. A ceramic base as set forth in Claim 1 wherein said low thermal conductivity ceramic is made from mullite.
4. A ceramic base as set forth in Claim 1 wherein said high thermal conductivity ceramic is made from aluminum nitride.
5. A ceramic base as set forth in Claim 1 wherein said high thermal conductivity ceramic is made from beryllium oxide. PC17US95/12809 O 96/13056
6 A ceramic base as set forth in Claim 1 wherein said high thermal conductivity ceramic is made from silicon carbide
7 A ceramic base as set forth in Claim 1 wherein said outer circumferential edge surface of said central portion of said ceramic base is attached to said inner circumferential edge surface of said peπpheral portion of said ceramic base with said top surface of said central portion being recessed with respect to said top surface of said peripheral portion using a devitrifying glass sealing material, thereby attaching said central portion of said ceramic base to said peπpheral portion of said ceramic base such that the sealing mateπal will not melt duπng subsequent processes in the production of said integrated circuit package.
8 A ceramic base as set forth in Claim 1 further comprising a heat sink attached to said bottom surface of said central portion of said ceramic base
9 A ceramic hermetically sealed integrated circuit package comprising a) a ceramic base including an outermost circumferential peripheral portion surrounding a central portion, said peπpheral portion hav ing a top surface, a bottom surface, an inner circumferential edge surface, and said peripheral portion of said ceramic base being made from a low thermal conductivity ceramic material, said central portion having a top surface, a bottom surface, an outer circumferential edge surface, and said central portion of said ceramic base being made f rom a high thermal conductivity ceramic material thereby reducing the thermal resistance of said ceramic base, b) an integrated circuit die having a top surface including a plurality of die input/output pads, said die being attached to said top surface of said central portion of said ceramic base using a die attaching adhesive, c) a leadframe having a top surface, a bottom surlace and including an array of electrically conductive leads, said bottom surface of said leadf rame being attached to said top surface of said peripheral portion of said ceramic base using a glass sealing material; d) . an array of bonding wires electrically connecting at least some of said die input/output pads on said die to corresponding electrically conductive leads on said leadframe; and e) a ceramic lid having a bottom surface attached to said top surface of said leadframe using a glass sealing material, thereby hermetically sealing said integrated circuit die within a space formed between said central portion of said ceramic base and said ceramic lid.
10. An integrated circuit package as set forth in Claim 9 wherein said low thermal conductivity ceramic is made from alumina.
1 1 . An integrated circuit package as set forth in Claim 9 wherein said low thermal conductivity ceramic is made from mullite.
12. An integrated circuit package as set forth in Claim 9 wherein said high thermal conductivity ceramic is made from aluminum nitride.
1 3. An integrated circuit package as set forth in Claim 9 wherein said high thermal conductivity ceramic is made from beryllium oxide.
14. An integrated circuit package as set forth in Claim 9 wherein said high thermal conductivity ceramic is made from silicon carbide.
15. An integrated circuit package as set forth in Claim 9 wherein said outer circumferential edge surface of said central portion of said ceramic base is attached to said inner circumferential edge surface of said peripheral portion of said ceramic base with said top surface of said central portion being recessed with respect so said top surface of said peripheral portion using a devitrifying glass sealing material, thereby attaching said central portion of said ceramic base to said peripheral portion of said
I I O 96/13056 ceramic base such that the sealing material will not melt during subsequent processes in the production of said integrated circuit package
16 An integrated circuit package as set forth in Claim 9 further comprising a heat sink attached to said bottom surface of said central portion of said ceramic base
17 A base for use in an integrated circuit, said base compπsing a first and second segment, said second segment being adapted to receive an electronic component, such as an integrated circuit die or other such component, attached directly to said second segment, said first segment being adapted to receive means, such as a conventional integrated circuit package leadframe, for electrically connecting said electronic component to external elements, and said second segment of said base being made from a mateπal having a higher thermal conductivity than the material making up said first segment thereby reducing the thermal resistance of said integrated circuit package
18 A base as set forth in Claim 17 wherein said first segment is ceramic made from alumina and mullite
19 A base as set forth in Claim 17 wherein said low thermal conductivity ceramic is made from mullite
20 A base as set forth in Claim 17 wher in said high thermal conductivity ceramic is made from aluminum nitride
21 A base as set forth in Claim 17 wherein said high thermal conductivity ceramic is made from beryllium oxide
22 A base as set forth in Claim 17 wherein said high thermal conductιv ιt> ceramic is made from silicon carbide O 96/13056
23. A base as set forth in Claim 17 wherein said second segment is attached to said first segment using a devitrifying glass sealing material, thereby attaching said second segment to said first segment such that the sealing material will not melt during subsequent processes in the production of said integrated circuit package.
24. A method of manufacturing a ceramic base for use in, for example, an hermetically sealed integrated circuit package, said method comprising the steps of; a) providing an outermost circumferential peripheral portion of said ceramic base having a top surface, a bottom surface, and an inner circumferential edge surface, said peripheral portion of said ceramic base being adapted to receive a conventional integrated circuit package leadframe and ceramic lid to form said hermetically sealed integrated circuit package and said peripheral portion of said ceraπiu base being made from a low thermal conductivity ceramic material, b) providing a central portion of said ceramic base having a top surface, a bottom surface, an outer circumferential edge surface, and a thickness le^ than the thickness of said peripheral portion of said ceramic base, said central poii i. x • said ceramic base being adapted to have an integrated circuit die attached directly in .t . ' top surface of said central portion and said central portion of said ceramic base beii - made from a high thermal conductivity ceramic material, and c) attaching said outer circumferential edge surface of said central portion of said ceramic base to said inner circumferential edge surface of said peripheral portion of said ceramic base with said top surface of said central portion being rccessetl with respect to said top surface of said peripheral portion using a devitrifying glass sealing material, thereby attaching said central portion of said ceramic base to said peripheral portion of said ceramic base such that the sealing material will not melt during subsequent processes in the production of said integrated circuit package.
25. A method as set forth in Claim 24 wherein said low thermal conductivity ceramic is made from alumina.
26. A method as set forth in Claim 24 wherein said low thermal conductivity ceramic is made from mullite.
27. A method as set forth in Claim 24 wherein said high thermal conductivity ceramic is made from aluminum nitride.
28. A method as set forth in Claim 24 wherein said high thermal conductivity ceramic is made from beryllium oxide.
29. A method as set forth in Claim 24 wherein said high thermal conductivity ceramic is made from silicon carbide.
30. A method as set for in Claim 24 further comprising the step of attaching a heat sink to said bottom surface of said central portion of said ceramic base.
3 1 . A method of manufacturing a ceramic hermetically sealed integrated circuit package comprising the steps of: a) providing a ceramic base including an outermost circumferential peπpheral portion suπounding a central portion, said peripheral portion having a top surface a bottom surface, an inner circumferential edge surface, and said peripheral portion of said ceramic base being made from a low thermal conductivity ceramic material, said central portion having a top surface, a bottom surface, an outer circumferential edge surface, and said central portion of said ceramic base being made from a high thermal conductivity ceramic material thereby reducing the thermal resistance of said ceramic base; b) attaching a bottom surface of an integrated circuit die having a top surface including a plurality of die input/output pads to said recessed top surface of said central portion of said ceramic base using a die attaching adhesive. c) attaching a bottom surface of a leadframe having a top surface and including an array of electrically conductive leads to said top surface of said Λ,„ ,Λ_^ O 96/13056
peripheral portion of said ceramic base using a glass sealing material; d) electrically connecting at least some of said die input/output pads on said die to corresponding electrically conductive leads on said leadframe using a wire bonding tool; and e) attaching the bottom surface of a ceramic lid to said top surface of said leadframe using a glass sealing material, thereby hermetically sealing said integrated circuit die within the space formed between said recessed central portion of said ceramic base and said ceramic lid.
32. A method as set forth in Claim 31 wherein said low thermal conductivity ceramic is made from alumina.
33. A method as set forth in Claim 31 wherein said low thermal conductivity ceramic is made from mullite.
34. A method as set forth in Claim 31 wherein said high thermal conductivity ceramic is made from aluminum nitride.
35. A method as set forth in Claim 31 wherein said high thermal conductivity ceramic is made from beryllium oxide.
36. A method as set forth in Claim 31 wherein said high thermal conductivity ceramic is made from silicon carbide.
37. A method as set forth in Claim 31 wherein the step of providing said ceramic base includes the step of attaching said outer circumferential edge surface of said centra] portion of said ceramic base to said inner circumferential edge surface of said peripheral portion of said ceramic base with said top surface of said central portion recessed with respect to said top surface of said peripheral portion using a devitrifying glass sealing material, thereby attaching said central portion of said ceramic base to said peπpheral portion of said ceramic base such that the sealing material will not melt duπng subsequent processes in the production of said integrated circuit package
38. A method as set forth in Claim 31 further comprising the step of attaching a heat sink to said bottom surface of said central portion of said ceramic base
PCT/US1995/012809 1994-10-14 1995-10-13 Hermetically sealed hybrid ceramic integrated circuit package WO1996013056A2 (en)

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US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
EP2159837A1 (en) * 2007-05-29 2010-03-03 Kyocera Corporation Electronic component storing package and electronic device
US8536626B2 (en) 2011-04-28 2013-09-17 Honeywell International Inc. Electronic pH sensor die packaging
EP3014668A4 (en) * 2013-06-27 2016-06-15 Byd Co Ltd LED SUPPORT ASSEMBLY AND LED MODULE HAVING THE SAME
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6054338A (en) * 1996-05-17 2000-04-25 National Semiconductor Corporation Low cost ball grid array device and method of manufacture thereof
US6140708A (en) * 1996-05-17 2000-10-31 National Semiconductor Corporation Chip scale package and method for manufacture thereof
US6284566B1 (en) 1996-05-17 2001-09-04 National Semiconductor Corporation Chip scale package and method for manufacture thereof
DE19820319B4 (en) * 1997-07-08 2005-12-01 National Semiconductor Corp.(N.D.Ges.D.Staates Delaware), Santa Clara Semiconductor device
EP2159837A1 (en) * 2007-05-29 2010-03-03 Kyocera Corporation Electronic component storing package and electronic device
EP2159837A4 (en) * 2007-05-29 2012-02-29 Kyocera Corp STORAGE BOX FOR AN ELECTRONIC COMPONENT AND ELECTRONIC DEVICE
US8536626B2 (en) 2011-04-28 2013-09-17 Honeywell International Inc. Electronic pH sensor die packaging
EP3014668A4 (en) * 2013-06-27 2016-06-15 Byd Co Ltd LED SUPPORT ASSEMBLY AND LED MODULE HAVING THE SAME
US9601676B2 (en) 2013-06-27 2017-03-21 Byd Company Limited LED support assembly and LED module
CN113782504A (en) * 2021-09-08 2021-12-10 中国矿业大学 Simplified packaging structure of power module of integrated radiator and manufacturing method
CN113782504B (en) * 2021-09-08 2024-06-25 中国矿业大学 Simplified packaging structure of power module of integrated radiator and manufacturing method

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