WO1996010841A1

WO1996010841A1 - Global signal net

Info

Publication number: WO1996010841A1
Application number: PCT/US1995/013078
Authority: WO
Inventors: Robert E. Eisenstadt; Kurt D. Rohrs
Original assignee: Vlsi Technology, Inc.
Priority date: 1994-09-30
Filing date: 1995-09-28
Publication date: 1996-04-11

Abstract

A semiconductor die (18) includes a multiplicity of die bonding pads (20) arrayed about the periphery of a surface of the die (18), and has a plurality of global signal bonding pad (21) located centrally to the peripheral die bonding pads (20). Global signals are those signals which are routed extensively throughout the semiconductor die (18), and include, for example, the power signal, ground signal, and clock signal. When a global signal is provided to the center of the semiconductor chip (18), the signal can be transmitted across the chip with a minimum of skew. In addition, the size of the electrically conductive traces which transmit the global signal within the chip can be decreased, allowing reductions in both semiconductor chip size, and cost. In some embodiments, the global signal inputs are provided in an interconnected lead net (17G) at or near the center of the die surface.

Description

Global Signal Net

Robert Eiβenstadt

Kurt Rohrs

Technical Field

This invention relates to the input and output of signals to a semiconductor chip, and especially to a semiconductor die which is connected to a lead system using tape automated (TAB) bonding.

Background of the Invention

Semiconductor devices communicate with their environment of use by accepting electrical impulses supplied by an external circuit (such as on a circuit board) and conducting these impulses to electrical circuits contained on a semiconductor chip. The semiconductor chip reacts to the input in a predetermined manner to generate output. The input and output of electrical impulses to the semiconductor device occur over multiple paths of electrically conducting material, commonly referred to as leads.

Connections between a semiconductor die and the electrically conductive leads can be made by wire bonding, in which a thin connecting wire is bonded at one end to a die bonding pad (die input or output), and at the opposite end to a lead finger of an electrical lead. When wire bonding is used to connect a semiconductor chip and its associated leads, a protective rigid housing is often added to enclose and protect the fragile connecting wires.

As the number of inputs and outputs to a single semiconductor chip have increased, and as desirable size parameters have decreased, the limitations of wire bonding have become apparent. TAB (tape automated bonding) methods have been developed to provide both a large number of package leads and a small overall package size.

In order to maximize the number of individual bonding pads which are available on the surface of semiconductor die, the trend has been to include a multiplicity of chip bonding pads arrayed about the periphery of a surface of a rectangular semiconductor die. While it is possible to include bonding pads along only one, two, or three sides of the surface of a semiconductor die, it is usual to include bonding pads along the perimeter of all four sides of the surface of a semiconductor die. This configuration maximizes the number of leads which can be connected to a single die. The bonding pads may be staggered or interdigitated as necessary to maximize the lead count.

TAB technology is commonly used when high lead counts and small package size are desired. TAB packages having leads extending from four sides of the semiconductor die commonly include 20 to 400 or more leads. When TAB connections are made, a bead (or "bump") of conductive material is used to connect the die input or output to an electrical lead. Figure la shows a partially cut-away view of a TAB semiconductor device package 10. Figure lb (taken through line lb-lb of Figure la) shows the semiconductor device package 10 in cross- section. TAB semiconductor device packages 10 generally have a solid or patterned insulative layer 12, and a lead layer 14 including a multiplicity of electrical leads 16. A semiconductor chip 18 is electrically connected to the lead layer 14 with a connective bump 20. An electrically nonconductive protective material 22, such as a standard epoxy semiconductor packaging encapsulant, can be present to maintain the semiconductor chip 18, the lead layer 14, and the connective bumps 20 in relative position. A rigid supporting member 24 can be present surrounding the periphery of the insulative layer 12 to provide rigidity to the package and to provide ease of handling.

The leads 16 of TAB semiconductor device packages 10 are typically connected to the semiconductor chip 18 at or near the periphery of the semiconductor chip 18. This configuration maximizes the number of leads which can be connected to a single semiconductor chip

18. Certain "global" inputs, such as power (VDD)_» ground (Vss). and clock (Tcκ)_> sSTe generally input at one site, and then routed extensively, as needed within the semiconductor chip 18. Figure 2 shows a sample routing pattern for a dual-input global signal, such as a clock input (TCK)- The clock input sites 26 are located at the periphery of the semiconductor chip 18. The clock trunk 28 runs across the width of the chip 18. Clock branches 30 extend from the clock trunk 28 to individual sites at which the clock signal is used. The specific embodiment for the clock trunk 28 and clock branches 30 will vary with the individual chip and its application. However, for a standard semiconductor chip 18 having a width of up to 580 mils, the length of the clock trunk 28 will generally run up to about 560 mils. The clock trunk 28 will generally have a cross-sectional diameter of up to 5 mils. The clock branches 30 will commonly have a length of up to 250 mils each, and a cross- sectional diameter of up to 1 mil.

In addition, due to of the length and width of the routing required, a phenomenon known as "skewing" of the signal can occur. For example, the lag in time between application of a clock signal at the clock input sites 26 and the transmission of the signal to the far end of a branch 30e can range from 1 nanosecond to as much as 4 nanoseconds. This skewing effect limits the accuracy, reUability, and function of the semiconductor device.

Similar difficulties of uneven application of signal and large trace requirements are encountered with power and ground inputs. The large trace sizes required for the transmission of global signals (e.g., clock, power, and ground signals) Umits the minimum size of the chip

18, and increases the cost of the chip 18. The maximum size of the chip is also limited due to signal skew which degrades the function of larger circuits on the chip.

fiii-m-mflrv of the Invention

A semiconductor die of this invention includes a multipUάty of chip bonding pads arrayed about the periphery of a surface of the die. In addition to the peripheral chip bonding pads, it includes a network of bonding pads located at or near the center of the die. These central bonding pads are used with one or more global signals. Global signals are those signals which are routed extensively throughout the semiconductor die, and include, for example, the power signal (VDD), ground signal (Vss). and clock signal (TCK)- When a global signal is provided to the center of the semiconductor chip, the global signal can be transmitted with a reduced skew to the rest of the chip. In addition, the size of the electrically conductive traces which transmit the global signal within the chip can be decreased, allowing reductions in semiconductor chip size and cost. By providing global signals at more than one centrally located chip bonding pad the number and size of electrical pathways within the chip can be minimized while still permitting a wide distribution of the signal.

Semiconductor dies of this invention can be processed to form a variety of semiconductor package types. Generally such packages include a number of electrically conductive leads which extend from individual bond pads to and beyond the periphery of the semiconductor die. The outer ends of these leads form, or can be processed into, package leads. A dielectric layer, especially a patterned dielectric layer, can be present as necessary to maintain the position of the various leads within the lead system.

Generally, semiconductor dies according to this invention are formed into packages using TAB processes. Using current technology,

TAB bonding permits the maximum number of connections between the semiconductor die and its associated leads. However, it is envisioned that alternate methods of connecting the semiconductor die to the lead system, including wire bonding, C4 methods, and the like, can be used. A variety of housing schemes can be used to protect the semiconductor dies of this invention. For example, a semiconductor die of this invention can be processed into plastic, ceramic, metal, chip-on- tape, PGA, and other such package types.

Brief Descrintion of the Drawings

Figure la shows a cutaway view of a TAB device of the prior art. Figure lb shows a cross-sectional representation of the device of Figure la, taken through line lb-lb.

Figure 2 shows a sample routing pattern for a clock input (TCK) of the prior art having two peripheral input sites.

Figure 3a shows a cutaway view of a TAB device of this invention. Figure 3b shows a cross-sectional representation of the device of Figure 3a, taken through line 3b-3b.

Figure 4 shows a sample routing pattern for a clock input (TCK) of this invention having multiple central input sites.

Figures 5 and 6 show various embodiments of lead patterns for devices of this invention.

The Figures are drawn for clarity and are not drawn to scale. A limited number of individual leads and chip bonding pads are shown for purposes of clarity only. Lead counts of 200 to 400 or greater are common for TAB packages such as those shown. It will also be understood that the specific lead embodiments shown are representative only, and that bonding pad placement and lead patterns in accordance with this invention will vary with specific chip applications. Similar numbers refer to similar structures throughout the Figures.

Disclosure of the Invention Including Best Mode

Semiconductor dies of this invention generally include a multiplicity of chip bonding pads arrayed about the periphery of a surface of the semiconductor die. While it is possible to include bonding pads along only one, two, or three sides of the surface of a semiconductor die, it will generally be preferred to include bonding pads about the perimeter of all four sides of the surface of a rectangular semiconductor die and thus to maximize the number of leads which are connected to the die.

"Global signals" are those signals which are commonly routed throughout the semiconductor die, and include, for example, the power signal (VDD)_» ground signal (Vss a d clock signal (TCK)-

GeneraUy, semiconductor dies of this invention include a multiplicity of chip bonding pads arrayed at or near the periphery of one or more edge of the die (the "peripheral bonding pads"). These peripheral bonding pads generally provide the bulk of the I/O access to and from the semiconductor die. Individual peripheral bonding pads may also provide connection for global signals. For example, it is common to provide ground leads at or near the corners of a semiconductor die.

The semiconductor dies of this invention include "central bonding pads". Central bonding pads are those bonding pads located centrally to the surface of the die, i.e., within the border provided by the traditionally arrayed peripheral bonding pads. While the central bonding pads may provide access to I/O, they will generally provide access to global signals. Because these central bonding pads are conveniently accessible from any edge, non-traditional lead systems are possible. For example, central bonding pads may be connected to one, two, or a network of leads which extend into and/or across the center of the die. Each central bonding pad may be connected to a single lead (see, for example, Figure 5). Alternatively, a two or more central bonding pads may be connected to a single lead (see Figure 6), or to a network of leads (see Figures 3, 7, and 8).

A "lead network" refers to two or more leads which are connected to each other at or near a surface of the semiconductor die, and are also connected to two or more bonding pads. A lead network will be connected to one or more central bonding pads, and may also be connected to one or more peripheral bonding pads.

Specific chip designs may provide that all of the global signals are provided centrally to the chip surface. Alternatively, only specific global signals may be provided centrally at the semiconductor chip surface. In some embodiments, global signals may be provided to peripheral bonding pads as well as to central bonding pads.

Semiconductor dies of this invention can be included in a variety of semiconductor package types. Generally such packages include a number of electrically conductive leads which extend from individual bond pads to, and beyond, the parameters of the semiconductor die. The outer ends of these leads form, or can be connected to, package leads. A dielectric layer, commonly a patterned dielectric layer, can be present to maintain the position of the individual leads within the lead system.

Preferably, semiconductor dies according to this invention are included in semiconductor packages which are formed using TAB processes, as TAB bonding currently permits a maximized number of connections between the semiconductor die and its associated leads. However, it is envisioned that alternate methods of connecting the semiconductor die to the lead system, including wire bonding, C4 methods, and the like, can be used.

A variety of housing schemes can be used to protect the semiconductor dies of this invention. For example, a semiconductor die of this invention can be processed into plastic, ceramic, metal, TAB, PGA, and other such package types. For purposes of clarity, and not by way of limitation, the invention herein will be described with reference to a TAB package which includes a dielectric layer and an optional external holder.

Figure 3a shows a partially cut away view of a TAB semiconductor device package 11 of this invention. Figure 3b (taken through line 3b-3b of Figure 3a) shows the semiconductor device package 11 in cross-section. The majority of the leads 17 are arrayed about the perimeter of the semiconductor chip 19. However, two contiguous leads combine to form a unified lead structure 17g which spans the surface of the semiconductor chip 19, and provides connection for one or more global input. As shown in the cross-sectional view of Figure 3b, three separate bonding pads have been connected to the unified lead structure 17g using TAB bonds (21a, 21b, 21c).

The semiconductor chip 19 can have any desired function or configuration. The specific pattern of the lead layer and the insulative layer can vary with the semiconductor die, its intended use, the method of affixing the semiconductor die to the lead layer, and the package type. For purposes of example, and not by way of limitation, a TAB bonded package will be described. It will be readily understood that other bonding methods, such as wire bonding and the like, can be used to connect the semiconductor chip 19 to individual leads 17 of the lead system 15.

The lead layer 15 is made of a conductive material, generally a metal. The metal used will generally depend upon the desired conductive attributes and cost. Leads of copper, gold, nickel, lead, tin, alloys or combinations thereof, or plated layers are typical. The lead layer 15 is patterned to provide a pluraUty of electrical leads 17 which extend between the periphery of the semiconductor chip 19 and the periphery of the completed package 11. In standard (peripheral) leads, the innermost edge of a lead 17 is electrically connected to a chip bonding pad (input or output connection) on the surface of the semiconductor chip 19. The outermost edge of the electrical lead 17 is the package lead, which provides connections between the semiconductor package 11 and the environment in which the package finds its ultimate use.

The majority of leads 17 of the improved semiconductor package 11 are connected to the semiconductor chip 19 at the periphery of the chip 19. This configuration maximizes the number of leads which can be connected to a single semiconductor chip 19.

In the improved semiconductor chip herein, one or more global input lead 17g, providing a global signal such as power (VDD ground (Vss). and/or clock (TCK). is electrically connected to the semiconductor chip 19 at one or more sites centrally located on the surface of the chip. This global signal is routed according to design parameters within the semiconductor chip 19. Due to the centralized distribution of the global signal(s), and to the integration of leads providing a specific global signal, signal skew is minimized.

The leads of the lead layer are connected both mechanically and electrically to the semiconductor chip 19, using known TAB processes. In this process, a conductive bump 21 is positioned between each semiconductor chip bonding pad (not visible) on the semiconductor chip 19 and an electrical lead 17. The connecting bump 21 is then heated under pressure to provide an electrical connection between the lead and the chip bonding pad. The connecting bumps 21 are made of an electrically conductive material, generally a metal. The metal used will depend upon the desired attributes of the connecting bump 21. Copper, gold, nickel, lead, and tin connecting bumps 21 are generally appropriate and can be used. Gold connecting bumps 21 are particularly appropriate.

A dielectric encapsulant material 23 can be used to protect the TAB bond, and to maintain the semiconductor chip 17, the lead layer 15, and the connective bumps 21 in relative position. Suitable encapsulant materials 23 are well known to the art, and include epoxies and silicones. Additional packaging structures, such as rigid plastic or metallic enclosing structures, protective structures, and/or heat sinks, can be present if desired. A rigid supporting member 25 can be present surrounding the periphery of the tape substrate to provide rigidity to the package and to provide ease of handling. Such supporting members are well known in the art.

The pictured TAB semiconductor package 11 includes a flexible sheet or cut-out insulative (dielectric) layer 13 such as an insulative tape. Such insulative layers are well known in the art, and are used to provide a structural support for the lead layer 15. When the insulative layer 13 is patterned (as shown), it does not form a continuous surface, but rather is patterned with voids of different shapes and sizes to provide a combination of conductive regions (encompassing a void through which the conductive layer is accessible) and insulative regions (encompassing a surface which insulates and isolates the conductive layer).

Generally, at least one bonding pad for a global signal is located within the central 70% of the chip surface. More generally, at least one bonding pad for a global signal is located within the central 50% of the chip surface. Conveniently, at least one bonding pad for a global signal is located within the central 30% of the chip surface.

Figure 4 shows a sample routing pattern for a global signal, such as a clock input (Tcκ)_> using a bonding pad placement herein. The bonding pad placement shown is consistent with the lead embodiment shown in Figures 3a and 3b. The clock input sites 27 are located in a linear pattern centrally at the surface of the chip 19. Dual clock trunks 29 each run less than half the width of the chip 19. Clock branches 31 extend from the clock trunks 29 to individual sites at which the clock signal is used. The specific embodiment for each clock trunk 29 and clock branch 31 will vary with the individual chip and its uses.

However, for a chip 19 having a width of 580 mils, the length of the clock trunk 29 will generally be less than about 220 mils. The clock trunk 29 will generally have a width of about 2 mils. The branches 31 will each commonly have a length of about 125 mils or less, and a width of about 0.5 mils.

Because the length and width of the routing pathways are significantly reduced, "skewing" of the signal is minimized. For example, the lag in time between application of a clock signal at the clock input sites 27 and the transmission of the signal to the end of a branch 31e using the global input placement herein will generally be reduced by a factor of two or more when contrasted to traditional global input methods. For example, "skewing" in the range of from less than 0.5 nanosecond to less than 2 nanoseconds will be easily achieved. Similar advantages in the reduction of length and width of trace sizes and signal skew will be encountered with power and ground inputs.

The reduction of trace size required for the transmission of global signals will permit the reduction of the minimum size of the chip 19, and decrease the cost of the chip 19.

Figure 5 shows a top view of a lead layer 15 and semiconductor chip 19 which can be processed into a TAB semiconductor device package of this invention. As pictured, the majority of the leads 17 are arrayed about the perimeter of the semiconductor chip 19. This configuration maximizes the number of leads which can be connected to a single semiconductor chip 19. However, four leads 17g, which provide connections for one or more global input, terminate at or near the center of the semiconductor chip 19. Bonding pads which are placed under the inner terminus of each of the four leads 17g are centrally located. That is, they are centrally located to the border provided by the peripheral leads which circumscribe the perimeter of the semiconductor chip 19.

The specific pattern of bonding pads located beneath the pattern of four leads 17g is not shown. However, in general, at least one bonding pad will be located at or near the inner terminus of each lead 17g. Additional bonding pads may be connected to each lead (similar to the bonding pad pattern shown in Figure 3) between the inner terminus and the edge of the semiconductor chip 19.

Each of the four leads 17g will provide a separate signal to the bonding pads to which it is connected. For example, one lead 17g may provide a clock signal to one or more bonding pads. .Another lead 17g may provide a ground to one or more bonding pads. When multiple leads provide signals go central bonding pads, each lead can carry the same signal (e.g., a clock signal), or a different signal can be provide by separate leads (e.g., a clock signal and a power signal can be provided on separate leads). The global signal or signals are routed as needed within the semiconductor chip 19. Figure 6 shows a top view of a lead layer 15 and semiconductor chip 19 which can be processed into a TAB semiconductor device package of this invention. As pictured, the majority of the leads 17 are arrayed about the perimeter of the semiconductor chip 19. However, two separate leads 17g, which each provides connection for a global input, terminate at or near the center of the semiconductor chip 19. Each of the leads 17g pictured includes multiple branches, so that each lead has multiple termination sites.

Bonding pads which are placed under each inner terminus of each of the two leads 17g are centrally located. That is, they are centrally located to the border provided by the peripheral leads which circumscribe the perimeter of the semiconductor chip 19. However, multiple bonding pads may be present at non-terminus sites along each lead. Additional bonding pads may be connected to each lead (similar to the bonding pad pattern shown in Figure 3) between the inner terminus of each branch, and the edge of the semiconductor chip 19.

As discussed above, each of the leads 17g will provide a separate signal to the bonding pads to which it is connected. For example, one lead 17g may provide a clock signal to multiple bonding pads. Another lead 17g may provide a ground to one or more bonding pads. When multiple leads provide signals go to central bonding pads, each lead can carry the same signal (e.g., a clock signal), or a different signal can be provide by separate leads (e.g., a clock signal and a power signal can be provided on separate leads). The global signal or signals are routed as needed within the semiconductor chip 19. Figure 7 shows a top view of a lead layer 15 and semiconductor chip 19 which can be processed into a TAB semiconductor device package of this invention. As pictured, the majority of the leads 17 are arrayed about the perimeter of the semiconductor chip 19. However, three integrated leads 17g combine to provide connection for a global input at or near the center of the semiconductor chip 19. Each of the three integrated leads 17g provide a common global signal in the pictured signal bus structure. A bus structure such as that shown is especially useful for distribution of power or ground signals, as the integration of the leads ensures that any voltage will be evenly distributed between the three separate leads. This, in turn, ensures that the voltage will be evenly distributed across the bonding pads serviced by the lead bus.

Bonding pads can be placed under the inner terminus bar which connects the three leads 17g as well as beneath each of the three leads themselves. Such embodiments have been discussed above.

Figure 8 shows a top view of a lead layer 15 and semiconductor chip 19 which can be processed into a TAB semiconductor device package of this invention. Again, the majority of the leads 17 are arrayed about the perimeter of the semiconductor chip 19. However, four integrated leads 17g combine to provide a ladder-shaped connection for a global input across the center of the semiconductor chip 19. Each of the four integrated leads 17g provide a common global signal in the pictured signal bus structure. A ladder structure such as that shown is especially useful for distribution of power or ground signals, as the integration of the leads ensures that any voltage will be evenly distributed between the separate leads. This, in turn, ensures that the voltage will be evenly distributed across the bonding pads serviced by the lead ladder. The specific pattern of bonding pads located beneath the pattern of four leads 17g is not shown, but can include multiple bonding pads at sites along the length of each lead as well as beneath each terminus.

While the invention has been described in connection with several exemplary embodiments, it will be understood that many modifications will be apparent to those of ordinary skiU in the art in light of the above disclosure. Such modifications may include providing distinctive lead patterns, integrating leads and bonding pads at one or more than one site per lead, using substitute materials, alternate bonding methods for connecting bonding pads and leads, smaller or greater dimensions, more than one die in a package, different types of encapsulated integrated circuit devices, a variety of different shapes for conductors, insulators and so forth, to achieve substantially the same results in substantially the same way. Reference to the following claims should be made to determine the scope of the claimed invention.

Claims

ξ___m_We Claim:

1. A TAB semiconductor package comprising:

(a) a semiconductor die having a multiplicity of chip bonding pads arrayed about the periphery of a surface of said die, said semiconductor die also including a plurality of global signal chip bonding pads central to said surface of said die; and

(b) a multiplicity of electrically conductive leads extending beyond the periphery of the semiconductor die, each of said electrically conductive leads being electrically connected by a TAB conductive bump to at least one bonding pad selected from the group consisting of peripheral bonding pads and global signal chip bonding pads on said surface of said semiconductor die; and

(c) a lead network of electrically conductive leads extending beyond the periphery of the semiconductor die, each lead of said lead network being electrically connected to at least one other lead of said lead network; said lead network being connected to at least one central global signal chip bonding pad, and to at least one bonding pad selected from the group consisting of peripheral bonding pads and central global signal chip bonding pads.

2. A semiconductor package of Claim 1 further comprising a dielectric layer which supports said electrically conductive leads in a specified pattern.

3. A semiconductor package of Claim 1 wherein said array of global signal bond pads are for connection to at least one of a power signal, a ground signal, and a clock signal.

4. A semiconductor package of Claim 1 wherein at least one global signal bonding pad is located within a central 50% of said die surface.

5. A semiconductor package of Claim 1 wherein said pattern of electrically conductive leads further comprises a dielectric layer which supports said electrically conductive leads on a single surface of said dielectric layer.

6. A method of bonding a semiconductor die to a lead system, said method comprising:

(a) providing a semiconductor die including a surface having: (i) a multiplicity of peripheral chip bonding pads arrayed about the periphery of said surface, and (ii) a plurality of global signal bonding pads centrally located at the surface;

(b) placing a pattern of electrically conductive leads in position for tape automated bonding said electrically conductive leads to said peripheral bonding pads and said global signal bonding pads; said electrically conductive lead pattern including individual leads and networked leads: (i) a multiplicity of electrically conductive individual leads extending beyond the periphery of the semiconductor die, each of said electrically conductive leads being electrically connected by a TAB conductive bump to at least one bonding pad selected from the group consisting of peripheral bonding pads and central global signal chip bonding pads; and

(ii) a lead network of electrically conductive leads, each lead of said lead network extending beyond the periphery of the semiconductor die, being electrically connected to at least one other lead of said lead network; said lead network being connected to at least one central global signal chip bonding pad, and to at least one bonding pad selected from the group consisting of peripheral bonding pads and central global signal chip bonding pads; and (c) using tape automated bonding processes to electrically connect said electrically conductive leads with said peripheral chip bonding pads and with said global signal bonding pads.

7. A method of Claim 6 wherein said pattern of electrically conductive leads further comprises a dielectric layer which supports said electrically conductive leads.

8. A method of Claim 6 wherein said global signal bonding pads comprise bonding pads for at least one of a power signal, a ground signal, and a clock signal.

9. A method of Claim 6 wherein said pattern of electrically conductive leads further comprises a dielectric layer which supports said electrically conductive leads on a single surface of said dielectric layer.

10. A method of producing an integrated circuit device package comprising:

(a) providing a lead layer including a multiplicity of individual electrically conductive leads and at least one lead network, wherein

(i) a multiplicity of individual leads extend beyond the periphery of the semiconductor die, each of said individual leads being electrically connected by a TAB conductive bump to a single bonding pad selected from the group consisting of peripheral bonding pads and global signal chip bonding pads on said surface of said semiconductor die;

(ii) a lead network of electrically conductive leads, each lead of said lead network extending beyond the periphery of the semiconductor die, being electrically connected to at least one other lead of said lead network; said lead network being electrically connected to at least one global signal chip bonding pad, and to at least one bonding pad selected from the group consisting of peripheral bonding pads and global signal chip bonding pads;

(b) providing a semiconductor die having a surface including a multiplicity of peripheral chip bonding pads arrayed about the periphery of said die surface, and a plurality of central global signal die bonding pads located centrally on said die surface; and (c) forming tape automated bonding electrical connections between the bonding pads of the semiconductor die and individual electrically conductive leads.

11. A method of Claim 10 further comprising:

(d) disposing a rigid protective layer over said electrical leads and integrated circuit die, at least partially covering the electrical leads and integrated circuit die.

12. A method of Claim 10 further comprising:

(d) disposing a first rigid protective layer over said electrical leads and integrated circuit die, at least partially covering said electrical leads and integrated circuit die; and

(e) disposing a second protective layer opposite said first rigid protective layer.

13. A method of Claim 10 wherein said central die bonding pads are electrically connected to at least one of a power signal, a ground signal, and a clock signal.

14. A method of Claim 10 wherein at least one central die bonding pad is located within a central 50% of said die surface.

15. A method of Claim 10 wherein said pattern of electrically conductive leads further comprises a dielectric layer which supports said electrically conductive leads on a single surface of said dielectric layer.