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WO1996002939A1 - Method of introducing material in holes - Google Patents

Method of introducing material in holes Download PDF

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Publication number
WO1996002939A1
WO1996002939A1 PCT/GB1995/001569 GB9501569W WO9602939A1 WO 1996002939 A1 WO1996002939 A1 WO 1996002939A1 GB 9501569 W GB9501569 W GB 9501569W WO 9602939 A1 WO9602939 A1 WO 9602939A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
hole
pressure
trench
wafer
Prior art date
Application number
PCT/GB1995/001569
Other languages
French (fr)
Inventor
Arthur John Mcgeown
Original Assignee
Electrotech Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Electrotech Limited filed Critical Electrotech Limited
Publication of WO1996002939A1 publication Critical patent/WO1996002939A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76882—Reflowing or applying of pressure to better fill the contact hole
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

Definitions

  • the present relates to arrangements in which a layer of material is formed on a surface, and then that material is introduced into holes or trenches in the surface. It is particularly, but not exclusively, concerned with arrangements in which that surface is a surface of a semiconductor wafer (or substrate used for integrated circuits) .
  • an electrically insulating layer is to be formed over the wafer, in order to isolate active regions and/or conductive tracks from each other, or to form a protective covering known as a passivation layer.
  • a passivation layer is often required to cover conductive tracks or other structures on the wafer, and these structures may be close to each other so that the gaps between them form narrow trenches.
  • the insulating material covers all the surface with sufficient thickness to provide good electrical insulation, be free of any pores or voids and that the top surface of the insulating layer shall be sufficiently smooth for the next stage of wafer processing.
  • the present invention seeks to provide another way of providing an elevated pressure in the layer, and proposes that a non-gaseous body is brought into contact with the layer and is forced against the layer so that a pressure is reached which causes the layer to deform in a similar way to the application of pressure by a gas.
  • a non-gaseous body is brought into contact with the layer and is forced against the layer so that a pressure is reached which causes the layer to deform in a similar way to the application of pressure by a gas.
  • elevated temperatures are also used.
  • elevated temperatures are not essential, and ultrasonic agitation may obviate the need for heating as a separate step.
  • the non-gaseous body may be an optically flat plate of rigid material which, applied to the exposed surface of the layer and the position of which is controlled precisely relative to the wafer to put the layer under pressure, and cause it to deform. It may also be possible for the non- gaseous body to be a roller which is rolled across the surface of the layer, which again results in a pressure being applied to the layer. Again, the spacing and the pressure between the roller and the layer must be controlled precisely.
  • non-gaseous body An important feature of the non-gaseous body is that it must not contaminate the layer, or any other part of the article. It may therefore be necessary to provide a coating for the body which achieves this (eg a diffusion barrier) .
  • the body is a solid, it must be extremely flat and stiff to prevent local deformations in its surface affecting the layer.
  • the body is a plate, it may be possible to move that plate by ultrasonic techniques and/or by means of a floating bearing. Electrostatic, electromagnetic or explosive movement methods may also be possible.
  • suitable support means will normally be needed to ensure that the article is positioned correctly relative to the non-gaseous body and must also be capable of handling the loads transmitted from the action of the body without suffering damage, either to the support or to the workpiece.
  • One advantage of the present invention is that it should be possible to apply the pressure to the layer more rapidly than can be achieved by gaseous methods.
  • the present invention is therefore particularly applicable to batch-processing arrangements in which a series of articles are processed sequentially with a relatively short time gap between each processing. This makes the present invention applicable to the deformation of layers on a single semiconductor die ("chip"), as well as applicable to whole semiconductor wafers.
  • the precise pressure conditions of the pressure pulse necessary to achieve the deformation of the layer will depend on the materials used, but for aluminium or aluminium alloys, the pressure will have to be higher than 10 x 10 6 Pa and pressures in excess of 20 to 70 x 10 6 Pa (200 to 700 bar) have been found to be suitable. Even higher pressures may be used.
  • Alloys commonly used for forming conductive tracks are of composition l/0-2%Si/0-4%Cu/0-10%Ti, and these have been found to deform suitably under such conditions.
  • the present invention is not limited to one particular method for forming the layer, and sputtering or chemical vapour deposition techniques may be used as discussed above, although other alternatives such as vacuum evaporation or application of a liquid may also be used. Indeed, it is possible for the layer to be pre-formed, as a film, which film is then positioned on the article.
  • material for forming the layer eg aluminium or other suitable material
  • material for forming the layer is first deposited on the surface of the underlying layer by eg sputtering.
  • the material may then be deposited on the sides and base of the hole or trench, although the thickness at the mouth of the structure will be greater.
  • deposition stops and the resulting structure is subject to elevated pressure to cause movement of the material to fill the structure, or to move into the structure sufficiently to allow a reliable electrical contact and sufficient cross- section for conduction if the material is a metal, or to provide a reliable electrical insulation if the material is an insulator.
  • Aluminium or some aluminium alloys, are particularly suitable for use with the present invention because their yield strengths are lower than other metals commonly used. Thus, they will deform to move into or fill the hole at relatively lower pressures and/or temperatures. For other materials having a higher yield strength, the pressures will need to be higher.
  • Fig.l shows a cross-sectional view of a semiconductor wafer prior to the formation of a layer according to the present invention
  • Pig 2 shows a cross-sectional view of the wafer of Fig 1, after formation of a layer thereon;
  • Fig 3 shows a cross-sectional view of the wafer of Fig
  • Fig 4 shows the wafer of Fig 3 after the body has applied pressure to the layer.
  • Fig.l shows a semiconductor wafer 1 with a pre-existing layer 2 thereon.
  • the wafer 1 itself may contain a plurality of layers and/or regions of different properties, to form a semiconductor device, and will be the result of a fabrication process involving a plurality of stages for forming those layers and/or regions.
  • the internal structure of the wafer 1 is not of significance in the present invention, and therefore these layers and/or regions will not be discussed further.
  • the layer 2 has a hole or trench structure 3 therein, and this embodiment of the present invention is particularly concerned with the problem of forming a layer over the pre ⁇ existing layer 2, e.g.
  • an electrical contact can be made by a metal layer to the surface 4 of the wafer 1 within the hole or trench structure 3, or an electrical insulator can be formed on the surface 4 of the wafer 1 within the hole or trench structure 3, or a layer can be formed that can be made semiconductive in known matter. That surface 4 may thus be in contact with e.g. active regions within the wafer, of further conductive tracks within the structure on the wafer.
  • a material such as aluminium is sputtered onto the surface of the layer 2 e.g. in a downward or sideways direction in Fig.l. Sputtering can also be done upwards if desired.
  • a material such as silicon dioxide (typically doped with Boron and Phosphorous) , polymide or spin-on-glass (SOG) is deposited onto the surface of the layer 2. This process continues until the new layer over the pre-existing layer 2 has a suitable thickness. This is shown in Fig. 2 with the new layer shown at 10. With such deposition techniques, deposition of the material to form the layer 10 tends to occur more rapidly at the mouth of the structure 3, as compared with its side walls and its base, formed by surface 4.
  • the side walls 11 of the hole or trench structure 3, and the surface 4 have a relatively thin layer of material thereon, as compared with the layer 10 covering the surface of the pre-existing layer 2. It can thus be seen that satisfactorily reliable electrical connection or insulation to the wafer 1 at the surface 4 may not be achieved. Furthermore, it is not normally possible to increase the amount of deposition on the side walls 11 and the surface 4 by continuing the deposition process,because that deposition process will eventually close the gap 12 in the layer 10 above the hole or trench structure 3, preventing further deposition within that structure 3 and leaving a void.
  • the gap 12 in the layer 10 be closed above the hole or trench 3.
  • the primary consideration may therefore be the desired thickness of the layer 10, rather than the need to deposit sufficient material to close the gap 12 to permit the structure 3 to be filled by differential gas pressure.
  • a non- gaseous body 20 is brought into contact with the layer 10.
  • the body 20 is moved gradually towards the wafer 1, and this has the effect of applying pressure to the layer 10.
  • the layer 10 will then deform due to this pressure as has previously been described. It may also be desirable to subject the wafer, layer 10, etc to the elevated temperatures. Temperatures above 350°C to 400°C and pressures above 10 x 10 6 Pa are most suitable, assuming that the material 10 is of aluminium or an aluminium alloy. Indeed, by suitable control of the pressure, it may be possible to achieve the present invention at temperatures of 150°C, or possibly even as low as room temperature.
  • Such elevated temperature and the pressure created by the body 20 causes the material of the layer 10 to flow proximate to the structure 3, and this process may continue until the structure 3 is filled. Once the structure 3 has been filled, satisfactory electrical contact to, or insulation of, the surface 4 may then be achieved.
  • suitable support means (not shown) is provided to position the wafer 1 below the body 20.
  • the body 20 may then be withdrawn.
  • the result is shown in Fig.4, where it can be seen that there has been flow of material 13 into the structure 3 to fill it.
  • the upper surface 21 of the layer 10 confirms to the surface of the body 20, and may thus be optically flat. This may be contrasted with the results of the methods disclosed in EP- A-0516344 and PCT/GB93/02359 where there is usually a small depression in the layer 10 at the site of the structure 3.
  • the body 20 does not contaminate the layer 10 nor should adhere to it, and for this reason there may be a diffusion barrier layer 22 on the body 20. It should be noted that it is important that the structure 3 is wholly filled by the material 13, as shown in Fig. 4. If the body 20 is not maintained in place for sufficiently long, or the separation of the body 20 from the wafer 1 is not sufficiently small, the flow of material 13 into the structure 3 may not wholly fill it. Furthermore, as previously mentioned, the pressure which the body 20 applies, and the temperature of the wafer 1, must also be suitable. The temperature and pressure will depend on the materials of the layer, but suitable values have already been discussed.
  • the present invention is particularly useful where it is desired that the final thickness of the layer 10 is to be small, relative to the diameter and/or depth of the structure 3. Since it is not necessary to close the mouth of the structure before applying the body 20, and therefore the thickness of the layer 10 is determined by its desired thickness, rather than other considerations.
  • the present invention permits satisfactorily reliable electrical connection to the wafer 1 to be achieved.
  • the present invention also ensures that the trench or hole is completely filled, with no voids or holes at all. This is important because the cross-sectional area of the conductive material in the hole will also determine the maximum permitted current density within the conductive layer. In order to achieve a maximum current density, the hole or trench needs to be filled completely and this is achieved by the present invention.
  • the present invention is also applicable to methods known as Damascene methods, in which a solid pore-free layer is formed, and then that layer is polished to remove that part of the layer which is not within the hole.
  • Such polishing generally known as Chemical-Mechanical Polishing (CMP) or Damascene Polishing is now being developed for use on e.g. semiconductor wafers, and the present invention is particularly applicable to such methods, because it permits complete filling of the hole or trench with very high quality "defined" material.
  • the present invention should also permit holes or trenches to be filled with very high reliability.
  • Such high reliability is essential when manufacturing e.g. semiconductor wafers since a failure to fill any single trench or hole will compromise the performance of semiconductor devices formed from the wafers. Since the body 20 applies a force to the layer 10 which is directed towards the wafer, but the material of the layer 10 is pushed directly into the hole or trench, control of the spacing between the body and the wafer 1 can ensure that there is no possibility that insufficient metal be forced into the hole or trench, thus giving the high reliability that is needed.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Laminated Bodies (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

A method of forming a layer (10) is sputtered onto an existing layer (2) in which is formed a hole or trench (3). The sputtered layer (10) builds up around the hole (3) but does not necessarily close it. A body (20) is applied against the layer (10) to force material from the layer (10) into the hole (3) to fill it.

Description

METHOD OF INTRODUCING MATERIAL IN HOLES
The present relates to arrangements in which a layer of material is formed on a surface, and then that material is introduced into holes or trenches in the surface. It is particularly, but not exclusively, concerned with arrangements in which that surface is a surface of a semiconductor wafer (or substrate used for integrated circuits) .
There are a number of situations during the formation of a semiconductor device in a semiconductor wafer where it is necessary to deposit a layer on to the wafer. One such situation arises when conductive or semiconductive tracks are to be formed over the wafer, so that those tracks may make contact with active or conductive regions of the device or circuit. Normally, such tracks must then extend through an insulating layer on the surface of the wafer so as to make contact with active regions below that insulating layer, or with further conductive tracks below that insulating layer (when the holes are usually called "vias") . Where the track extends through a hole in this way, it is important that the amount of material, eg metal filling that hole, is sufficient to ensure good electrical contact.
Another situation is when an electrically insulating layer is to be formed over the wafer, in order to isolate active regions and/or conductive tracks from each other, or to form a protective covering known as a passivation layer. Such a layer is often required to cover conductive tracks or other structures on the wafer, and these structures may be close to each other so that the gaps between them form narrow trenches. It is important that the insulating material covers all the surface with sufficient thickness to provide good electrical insulation, be free of any pores or voids and that the top surface of the insulating layer shall be sufficiently smooth for the next stage of wafer processing.
In our European Patent Application No EP-A-0516344 we proposed that a layer was formed on the surface of an article, in which surface there was a recess such as a hole or trench. Then, it was proposed that the article, including the layer, was subjected to elevated pressure and elevated temperature sufficient to cause the layer to deform. By suitable control of the temperature and pressure, the layer is deformed sufficiently to cause the material of the layer to enter the recess to fill it.
It was thought that the primary factor causing the deformation was plastic flow, for example by dislocation slips in crystalline materials, activated by the elevated pressure and temperature. Surface diffusion, grain boundary diffusion and lattice diffusion were also thought to have an effect, activated by the elevated temperature. In our International Application No PCT/GB93/02359 we discussed the possibility of the same effect being achieved by elevated pressures, without the need for elevation of temperature.
The present invention seeks to provide another way of providing an elevated pressure in the layer, and proposes that a non-gaseous body is brought into contact with the layer and is forced against the layer so that a pressure is reached which causes the layer to deform in a similar way to the application of pressure by a gas. In EP-A-0516344 and PCT/GB93/02359, it was important that the mouth of the structure was completely closed during the deposition of the layer, leaving a void below the closed mouth within the structure. This closing of the mouth of the structure enabled the material to be pushed down into the structure, collapsing the void by the elevated pressure outside it. However, this has a disadvantage if it is important to have a very thin layer and, at the same time, to fill a relatively large structure. This is needed, for example, to fill a trench or to provide planarity over a large area of the article. In order to close the mouth of the structure, a relatively large amount of material needs to be deposited to form the layer, but then the resulting layer is very thick. With the present invention, on the other hand, the pressure imposed by the non-gaseous body is determined by its position relative to the article, rather than the differential pressure across the closed mouth of the structure. Hence, it is not necessary to close the mouth of the structure and thus the layer may be thinner than in EP-A-0516344 and PCT/GB93/02359. This ability to achieve satisfactory filling of a hole or trench with thinner layers than are needed in EP-A-0516344 and PCT/GB93/02359 is a significant advantage, since it is increasingly important in the manufacture of semiconductor wafers that the thickness of any metal may be minimised.
Preferably, as in EP-A-0516344, elevated temperatures are also used. However, elevated temperatures are not essential, and ultrasonic agitation may obviate the need for heating as a separate step.
There are several possibilities for the non-gaseous body. For example, it may be an optically flat plate of rigid material which, applied to the exposed surface of the layer and the position of which is controlled precisely relative to the wafer to put the layer under pressure, and cause it to deform. It may also be possible for the non- gaseous body to be a roller which is rolled across the surface of the layer, which again results in a pressure being applied to the layer. Again, the spacing and the pressure between the roller and the layer must be controlled precisely.
An important feature of the non-gaseous body is that it must not contaminate the layer, or any other part of the article. It may therefore be necessary to provide a coating for the body which achieves this (eg a diffusion barrier) .
Since the pressure applied to the layer is determined by the position of the non-gaseous body relative to the article, that position must be controlled accurately.
Moreover, assuming that the body is a solid, it must be extremely flat and stiff to prevent local deformations in its surface affecting the layer. Where the body is a plate, it may be possible to move that plate by ultrasonic techniques and/or by means of a floating bearing. Electrostatic, electromagnetic or explosive movement methods may also be possible.
Furthermore, suitable support means will normally be needed to ensure that the article is positioned correctly relative to the non-gaseous body and must also be capable of handling the loads transmitted from the action of the body without suffering damage, either to the support or to the workpiece.
One advantage of the present invention is that it should be possible to apply the pressure to the layer more rapidly than can be achieved by gaseous methods. The present invention is therefore particularly applicable to batch-processing arrangements in which a series of articles are processed sequentially with a relatively short time gap between each processing. This makes the present invention applicable to the deformation of layers on a single semiconductor die ("chip"), as well as applicable to whole semiconductor wafers.
The precise pressure conditions of the pressure pulse necessary to achieve the deformation of the layer will depend on the materials used, but for aluminium or aluminium alloys, the pressure will have to be higher than 10 x 106Pa and pressures in excess of 20 to 70 x 106Pa (200 to 700 bar) have been found to be suitable. Even higher pressures may be used.
Alloys commonly used for forming conductive tracks are of composition l/0-2%Si/0-4%Cu/0-10%Ti, and these have been found to deform suitably under such conditions. The present invention is not limited to one particular method for forming the layer, and sputtering or chemical vapour deposition techniques may be used as discussed above, although other alternatives such as vacuum evaporation or application of a liquid may also be used. Indeed, it is possible for the layer to be pre-formed, as a film, which film is then positioned on the article.
Thus, to form a layer on a semiconductor wafer, which layer is to extend through holes or into trenches in an underlying layer on the surface of the wafer, material for forming the layer (eg aluminium or other suitable material) is first deposited on the surface of the underlying layer by eg sputtering. The material may then be deposited on the sides and base of the hole or trench, although the thickness at the mouth of the structure will be greater. When a suitable amount of material has been deposited, deposition stops and the resulting structure is subject to elevated pressure to cause movement of the material to fill the structure, or to move into the structure sufficiently to allow a reliable electrical contact and sufficient cross- section for conduction if the material is a metal, or to provide a reliable electrical insulation if the material is an insulator.
Aluminium, or some aluminium alloys, are particularly suitable for use with the present invention because their yield strengths are lower than other metals commonly used. Thus, they will deform to move into or fill the hole at relatively lower pressures and/or temperatures. For other materials having a higher yield strength, the pressures will need to be higher.
An embodiment of the present invention will now be described in detail, by way of example, with reference to the accompanying drawings in which:
Fig.l shows a cross-sectional view of a semiconductor wafer prior to the formation of a layer according to the present invention;
Pig 2 shows a cross-sectional view of the wafer of Fig 1, after formation of a layer thereon;
Fig 3 shows a cross-sectional view of the wafer of Fig
2 when a non-gaseous body is applied thereto; and
Fig 4 shows the wafer of Fig 3 after the body has applied pressure to the layer.
Fig.l shows a semiconductor wafer 1 with a pre-existing layer 2 thereon. The wafer 1 itself may contain a plurality of layers and/or regions of different properties, to form a semiconductor device, and will be the result of a fabrication process involving a plurality of stages for forming those layers and/or regions. The internal structure of the wafer 1 is not of significance in the present invention, and therefore these layers and/or regions will not be discussed further. The layer 2 has a hole or trench structure 3 therein, and this embodiment of the present invention is particularly concerned with the problem of forming a layer over the pre¬ existing layer 2, e.g. so that either an electrical contact can be made by a metal layer to the surface 4 of the wafer 1 within the hole or trench structure 3, or an electrical insulator can be formed on the surface 4 of the wafer 1 within the hole or trench structure 3, or a layer can be formed that can be made semiconductive in known matter. That surface 4 may thus be in contact with e.g. active regions within the wafer, of further conductive tracks within the structure on the wafer.
To form a metal layer, a material such as aluminium is sputtered onto the surface of the layer 2 e.g. in a downward or sideways direction in Fig.l. Sputtering can also be done upwards if desired. To form an insulating layer, a material such as silicon dioxide (typically doped with Boron and Phosphorous) , polymide or spin-on-glass (SOG) is deposited onto the surface of the layer 2. This process continues until the new layer over the pre-existing layer 2 has a suitable thickness. This is shown in Fig. 2 with the new layer shown at 10. With such deposition techniques, deposition of the material to form the layer 10 tends to occur more rapidly at the mouth of the structure 3, as compared with its side walls and its base, formed by surface 4. As a result, as shown in Fig. 2, the side walls 11 of the hole or trench structure 3, and the surface 4, have a relatively thin layer of material thereon, as compared with the layer 10 covering the surface of the pre-existing layer 2. It can thus be seen that satisfactorily reliable electrical connection or insulation to the wafer 1 at the surface 4 may not be achieved. Furthermore, it is not normally possible to increase the amount of deposition on the side walls 11 and the surface 4 by continuing the deposition process,because that deposition process will eventually close the gap 12 in the layer 10 above the hole or trench structure 3, preventing further deposition within that structure 3 and leaving a void.
In the present invention, it is not necessary, however, that the gap 12 in the layer 10 be closed above the hole or trench 3. The primary consideration may therefore be the desired thickness of the layer 10, rather than the need to deposit sufficient material to close the gap 12 to permit the structure 3 to be filled by differential gas pressure.
Therefore, according to the present invention, a non- gaseous body 20 is brought into contact with the layer 10. The body 20 is moved gradually towards the wafer 1, and this has the effect of applying pressure to the layer 10. The layer 10 will then deform due to this pressure as has previously been described. It may also be desirable to subject the wafer, layer 10, etc to the elevated temperatures. Temperatures above 350°C to 400°C and pressures above 10 x 106Pa are most suitable, assuming that the material 10 is of aluminium or an aluminium alloy. Indeed, by suitable control of the pressure, it may be possible to achieve the present invention at temperatures of 150°C, or possibly even as low as room temperature. Such elevated temperature and the pressure created by the body 20 causes the material of the layer 10 to flow proximate to the structure 3, and this process may continue until the structure 3 is filled. Once the structure 3 has been filled, satisfactory electrical contact to, or insulation of, the surface 4 may then be achieved.
It should also be noted that suitable support means (not shown) is provided to position the wafer 1 below the body 20.
Once the structure 3 has been filled (which in practice is determined by the spacing of the body 20 and the wafer 1) , the body 20 may then be withdrawn. The result is shown in Fig.4, where it can be seen that there has been flow of material 13 into the structure 3 to fill it. The upper surface 21 of the layer 10 confirms to the surface of the body 20, and may thus be optically flat. This may be contrasted with the results of the methods disclosed in EP- A-0516344 and PCT/GB93/02359 where there is usually a small depression in the layer 10 at the site of the structure 3.
It is important that the body 20 does not contaminate the layer 10 nor should adhere to it, and for this reason there may be a diffusion barrier layer 22 on the body 20. It should be noted that it is important that the structure 3 is wholly filled by the material 13, as shown in Fig. 4. If the body 20 is not maintained in place for sufficiently long, or the separation of the body 20 from the wafer 1 is not sufficiently small, the flow of material 13 into the structure 3 may not wholly fill it. Furthermore, as previously mentioned, the pressure which the body 20 applies, and the temperature of the wafer 1, must also be suitable. The temperature and pressure will depend on the materials of the layer, but suitable values have already been discussed. Furthermore, care needs to be taken if there are multiplicity of adjacent structures 3, to ensure that there is sufficient material in the layer 10 to fill them all. However, the present invention is particularly useful where it is desired that the final thickness of the layer 10 is to be small, relative to the diameter and/or depth of the structure 3. Since it is not necessary to close the mouth of the structure before applying the body 20, and therefore the thickness of the layer 10 is determined by its desired thickness, rather than other considerations.
As has previously been mentioned, where the layer 10 is conductive, the present invention permits satisfactorily reliable electrical connection to the wafer 1 to be achieved. The present invention also ensures that the trench or hole is completely filled, with no voids or holes at all. This is important because the cross-sectional area of the conductive material in the hole will also determine the maximum permitted current density within the conductive layer. In order to achieve a maximum current density, the hole or trench needs to be filled completely and this is achieved by the present invention.
The present invention is also applicable to methods known as Damascene methods, in which a solid pore-free layer is formed, and then that layer is polished to remove that part of the layer which is not within the hole. Such polishing, generally known as Chemical-Mechanical Polishing (CMP) or Damascene Polishing is now being developed for use on e.g. semiconductor wafers, and the present invention is particularly applicable to such methods, because it permits complete filling of the hole or trench with very high quality "defined" material.
Within the present invention, it is not necessary to use a solid plate 20, and it may be possible to make use of a solid roller which is moved along the surface of the layer 10. The present invention should also permit holes or trenches to be filled with very high reliability. Such high reliability is essential when manufacturing e.g. semiconductor wafers since a failure to fill any single trench or hole will compromise the performance of semiconductor devices formed from the wafers. Since the body 20 applies a force to the layer 10 which is directed towards the wafer, but the material of the layer 10 is pushed directly into the hole or trench, control of the spacing between the body and the wafer 1 can ensure that there is no possibility that insufficient metal be forced into the hole or trench, thus giving the high reliability that is needed.

Claims

1. A method for forming a layer of material on the surface of an article, in which surface there is a recess such as a hole or trench, comprising the steps of depositing a layer of material on to the surface and subjecting the deposited layer to an elevated pressure sufficient to cause the layer to deform into the recess characterised in that the elevated pressure is created by bringing an non-gaseous body into contact with the layer and forcing the body against the layer so that a pressure is reached which causes the layer to deform to fill the recess.
2. A method as claimed in claim 1 wherein the deposited layer does not close the mouth of the recess.
3. A method as claimed in Claim 2 wherein the deposited layer overhangs the mouth of the recess.
4. A method as claimed in any of the preceding claims wherein the layer is heated prior to or simultaneously with the application of pressure.
5. A method as claimed in any one of the preceding claims wherein the layer is ultrasonically agitated prior to or simultaneously with the application of pressure.
6. A method as claimed in any one of the preceding claims wherein the body is an optically flate plate of rigid material or a roller.
7. A method as claimed in any one of the preceding claims wherein the body is coated with an anti-contamination layer.
8. A method as claimed in any one of the preceding claims wherein the body is moved ultrasonically and/or by means of a floating bearing; electrostatically; electromagnetically or explosively.
9. A method as claimed in any one of the preceding claims wherein the pressure exceeds 10 x 106Pa.
10. A method as claimed in Claim 7 wherein the pressure is in the range of 20 to 70 x 106Pa.
11. A method for forming a layer on a semiconductor wafer, which layer is to extend through holes or into trenches in an underlying layer on the surface of the wafer. Material is first deposited on the surface of the underlayer or on the surface of the underlayer and the sides of the hole or trench until the mouth of the hole or trench is at least partially closed, subjecting the material to an elevated pressure by means of a non-gaseous body to cause movement of the material to fill the hole or trench.
12. A method as claimed in Claim 11 wherein the material is electrically conducting and the hole or trench is filled sufficiently to allow a reliable electrical contact of sufficient cross-section for good conduction.
13. A method as claimed in Claim 11 wherein the material is an insulator and the hole or trench is sufficiently filled to become electrically insulated.
PCT/GB1995/001569 1994-07-13 1995-07-05 Method of introducing material in holes WO1996002939A1 (en)

Applications Claiming Priority (2)

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GB9414145.4 1994-07-13
GB9414145A GB9414145D0 (en) 1994-07-13 1994-07-13 Forming a layer

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KR (1) KR100357508B1 (en)
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EP1162656A3 (en) 2004-01-28
EP0719451B1 (en) 2002-10-16
KR960705350A (en) 1996-10-09
DE69528571T2 (en) 2003-07-03
JPH09503104A (en) 1997-03-25
DE69534555D1 (en) 2005-12-01
DE69534555T2 (en) 2006-07-20
EP1162656A2 (en) 2001-12-12
GB9414145D0 (en) 1994-08-31
CA2171092A1 (en) 1996-02-01
DE69528571D1 (en) 2002-11-21
WO1996002938A1 (en) 1996-02-01
EP1162656B1 (en) 2005-10-26
EP0719451A1 (en) 1996-07-03
KR100357508B1 (en) 2003-01-24

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