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WO1996002042A1 - Element support a monter dans des cartes a memoire ou dans d'autres cartes supports d'informations - Google Patents

Element support a monter dans des cartes a memoire ou dans d'autres cartes supports d'informations Download PDF

Info

Publication number
WO1996002042A1
WO1996002042A1 PCT/EP1995/002154 EP9502154W WO9602042A1 WO 1996002042 A1 WO1996002042 A1 WO 1996002042A1 EP 9502154 W EP9502154 W EP 9502154W WO 9602042 A1 WO9602042 A1 WO 9602042A1
Authority
WO
WIPO (PCT)
Prior art keywords
carrier element
contact surfaces
chip
component
contact
Prior art date
Application number
PCT/EP1995/002154
Other languages
German (de)
English (en)
Inventor
Frank Druschke
Roland Diemer
Gerhard Elsner
Wolfgang Schmid
Reinhold Braun
Harald Gruber
Wolfgang Beck
Rainer Kratzert
Original Assignee
International Business Machines Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation filed Critical International Business Machines Corporation
Publication of WO1996002042A1 publication Critical patent/WO1996002042A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases

Definitions

  • the invention relates to the establishment of an electrical connection between an IC component (chip) and a carrier element which is provided for installation in chip cards or other data carrier cards.
  • the chip cards used recently for information processing usually consist of a single or multi-layer insulated carrier element which e.g. carries the integrated semiconductor circuit (chip) in a recess. After contacting, the chip is cast with a casting resin to protect the chip from environmental influences.
  • connection points of the chip are connected to the contact surfaces of the carrier element via fine gold wires.
  • United States Patent US-A-4,474,292 discloses tape automated bonding (TAB) as a way of making contact between the chip and the contact surfaces of the carrier element.
  • TAB tape automated bonding
  • the wiring pattern contains contact fingers, which are guided in the form of a so-called contact spider from the outside towards the inside of the chip.
  • the chip is then applied, for example by ultrasonic welding, to the ends of these contact fingers of the circuit.
  • the teaching of this document forms the preamble of claim 1.
  • the respective contact surfaces can only be localized along the outer sides of the contact surface of the chip on the carrier element. This means that higher integration densities with a correspondingly large number of required connections cannot be achieved or can only be achieved with great difficulty.
  • Find carrier element that enables high integrations of the chip with a correspondingly high number of contacts for communication of the chip with its surroundings. It is a further object of the invention to find a contacting option which makes contacting possible over the entire contact surface of the chip.
  • the objects are achieved in that the "Controlled Collapse Chip Connection” (C4) technique, known as such, is used to establish the electrical connection between the IC component and the carrier element.
  • C4 Controlled Collapse Chip Connection
  • This C4 technique is e.g. known from
  • LFMiller Controlled Collapse Reflow Chip Joining, IBM J.Res.Develop.13, No.3, 239-250 (1969) and was developed to mount up to 120 chips on a multilayer ceramic carrier (MLC).
  • MLC multilayer ceramic carrier
  • C4 technology the wiring lengths between the chips become very short, which in turn leads to shorter signal delays.
  • a correspondingly high chip packaging density cannot be achieved with "wire bonding" or TAB technology.
  • the compact design of the contacts means that the C4 technology enables more favorable heat dissipation via the contacts into the substrate.
  • the above-mentioned tasks of the C4 technology play only a subordinate role both for producing high chip packaging densities and for dissipating heat.
  • the process according to the invention enables the use of the C4 technology to distribute the contact areas, both on the chip and on the carrier element, over the entire contact area of the chip on the carrier element and can be correspondingly realize any integration densities of the chips.
  • the possibility of contacting according to the invention also enables the respective contact surfaces to be sharply delimited on the region imaged by the projection of the chip, perpendicular to the contact surface of the chip on the carrier element, on the carrier element. On the one hand, this reduces the risk of the electromagnetic interference of the contact surfaces and corresponding feeds with one another, especially since the overall contact surfaces can also be made smaller than in the prior art. On the other hand, the necessary further wiring to the contact side of the carrier element to the outside world is eliminated, in particular if so-called vias are exclusively used in the carrier element.
  • the sharp delimitation of the respective contact areas on the respective projection area of the chip enables a higher area compression of several chips next to one another on the carrier element.
  • several small chips can be combined in the area, which in turn has a favorable effect on the mechanical durability of the overall arrangement.
  • the mechanical durability of chip cards plays an essential role, since these are mobile everyday objects.
  • the process according to the invention results in mechanically more favorable contacting of the chip on the carrier element than is known from the prior art.
  • the contacting process according to the invention results in the contact areas on and on the chip describe the carrier element in approximately the same area. This in turn results in essentially uniform distributions of the current densities along the contacts, which likewise leads to more favorable electromagnetic behavior.
  • the carrier element has a non-conductive layer and a conductive layer, and the IC module can be inserted into a recess in the non-conductive layer.
  • plated-through holes are introduced into the non-conductive layer, on which the IC module is then placed.
  • the vias can be recessed relative to a contact surface of the chip on the carrier element. All of these embodiments enable the production of carrier elements which are as flat as possible and assembled with chips, as is required for use in chip cards.
  • La shows an inventive method for contacting a chip on a carrier element
  • 1c shows the process of potting the chip soldered on the contact level
  • 2 shows the type of chip mounting on a flexible carrier element
  • Figure 3a shows the process of applying the
  • 3b shows the solder balls formed on the contact surfaces by a heat process as lead / tin alloys
  • Fig. 4 shows a further embodiment of the
  • FIG. 1 a shows a method according to the invention for contacting a chip 2 on a carrier element 4.
  • the carrier element 4 consists of a contact plane 8, which is applied flat on an insulator 6, the insulator 6 having a recess 10 into which the Chip 2 is to be introduced.
  • the insulator 6 is preferably made of fiber-reinforced polyimide.
  • the carrier element 4 is inserted into a so-called chip card, on which data can be stored and processed.
  • the contact plane 8 of the carrier element 4 then serves to contact the chip 2 with the outside world, e.g. a smart card reader, according to the applications of the smart card.
  • solder balls 14 are applied to contact surfaces 16-24 on the side of the chip 2 to be contacted.
  • the solder balls 14 can also be placed on those corresponding to the contact surfaces 16-24.
  • Contact surfaces 26-34 are applied to the contact plane 8 of the carrier element 4.
  • a combined application of the solder balls 14 is also possible both on contact surfaces of the chip 2 and on the contact plane 8.
  • Fig. Lb shows the process of contacting the chip 2 with the contact plane 8.
  • the chip 2 is roughly aligned approximately on the contact plane 8, so that the contact surfaces of the chip 2 and the contact plane 8 to be contacted essentially opposite each other and each Include solder balls 14. Furthermore, at least as much heat is supplied by a soldering process until the solder balls 14 melt and a galvanic contact is established between the corresponding contact surfaces of the chip 2 and the contact plane 8. Due to the effect of equalizing and minimizing the total sum of the surface tensions of the solder balls, provided the geometry of the contact areas is essentially the same, the chip 2 adjusts itself independently on the contact plane 8.
  • the contact surfaces to be contacted on the chip 2 and on the carrier element 4 are oriented in such a way that the respective contact surfaces of the chip 2 and the carrier element 4 are essentially centered. This ensures a simple and highly precise alignment process of the chip 2 on the carrier element 4, which can also automatically compensate for smaller inaccuracies in the contact geometries.
  • the area between the contact surfaces to be contacted on the chip 2 and on the carrier element 4 form the contacts between the chip 2 and the carrier element 4.
  • a slight pulling apart of the chip 2 and the contact plane 8 perpendicular to the contact surface of the chip 2 on the contact plane 8, without the contact surfaces being detached from one another, can increase the mechanical strength of the resulting soldered connection.
  • the latter is encased in an appropriate casting compound 36 in a process following the soldering process.
  • the potting compound 36 must have such a viscosity that the chip 2 can be cast in and is thereby permanently fixed.
  • 1c shows the process of potting the chip 2 soldered on the contact plane 8. The potting is carried out in such a way that the chip 2 lying in the recess 10 is completely embedded in the insulator 6 of the carrier element 4.
  • Figs. La-c embodiment shown it is also possible not to mount the chip 2 in a recess 10 or an opening of the insulator 6, but directly on the surface of the carrier element 4. 2 shows this type of chip mounting on the flexible carrier element 4.
  • the insulator 6 has so-called plated-through holes 38-40 for producing conductive connections between contacts on an upper side 42 and a lower side 44 of the insulator 6.
  • a further contact plane 52 corresponding to the contact plane 8 can be applied to the insulator 6 on the underside 44.
  • the plated-through holes 38-40 now allow removal of those connected to the chip 2 on the surface 42.
  • FIG. 3a now shows the process of applying the soldered connection as individual components to the contact surfaces 16-24 of the side of the chip 2 to be contacted for an exemplary embodiment.
  • a lead / tin metallurgy is vacuum coated onto those not covered by a mask 60. Brought contact surfaces 16-24.
  • the solder balls 14 form as lead / tin alloys on the contact surfaces 16-24 due to the heat energy from the cylindrical lead and tin deposits (FIG. 3b).
  • the chip can then be assembled and soldered analogously to the method described above.
  • the melting temperature of the eutectic is Composition about 183 ° C.
  • other desired melting temperatures can be set according to the lead-tin ratio.
  • materials for the insulator 6 are, in particular, polyimides or polycyanate esters or BT resins (bismaleimide triazine), which can also be fiber-reinforced.
  • FIG. 4 shows a further embodiment of the invention, which enables a reduction in the total height of the connection between chip 2 and insulator 6.
  • the plated-through holes 38-40 are in this case made smaller than the thickness of the insulator 6 between the upper side 42 and the lower side 44.
  • the plated-through holes 38-40 have further contact surfaces 60-64 on the side opposite the contact surfaces 46-50. These contact surfaces 60-64 are now approximately aligned with the underside 44 of the insulator 6, so that the contact surfaces 46-50 are no longer approximately aligned with the upper side 42 as in FIG. 2, but are recessed between the upper side 42 and the underside 44 lie.
  • the solder balls 14 can now be dimensioned such that after the chip 2 and the insulator 6 of the carrier element 4 have been joined together, the chip 2 lies approximately on the insulator 6 or at least the total height of the chip 2 and carrier element 4 is reduced.
  • the contact surfaces 16-24 can also be deepened relative to the contact surface of the contact side of the chip 2.
  • the chip 2 would have to have a correspondingly designed shape of the connection side with the contact surfaces 16-24.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

L'invention concerne l'utilisation de la technique C4 connue en tant que telle, pour réaliser une connexion électrique entre un module CI (2) et un élément support (4) destiné à être monté dans des cartes à mémoire ou dans d'autres cartes supports d'informations. Il en résulte une possibilité de mise en contact entre le module CI (2) et l'élément support (4), qui permet d'atteindre un haut degré d'intégration du module CI (2) avec un nombre important correspondant de contacts pour que le module CI (2) communique avec son entourage. Cela permet également de réaliser une mise en contact sur toute la surface portante du module CI (2) et de parvenir à des encombrements en hauteur moins importants de la connexion entre le module CI (2) et l'élément support (4), avec des exigences inchangées en ce qui concerne la mise en contact entre le module CI (2) et l'élément support (4).
PCT/EP1995/002154 1994-07-11 1995-06-06 Element support a monter dans des cartes a memoire ou dans d'autres cartes supports d'informations WO1996002042A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DEP4424396.0 1994-07-11
DE4424396A DE4424396C2 (de) 1994-07-11 1994-07-11 Trägerelement zum Einbau in Chipkarten oder anderen Datenträgerkarten

Publications (1)

Publication Number Publication Date
WO1996002042A1 true WO1996002042A1 (fr) 1996-01-25

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ID=6522837

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1995/002154 WO1996002042A1 (fr) 1994-07-11 1995-06-06 Element support a monter dans des cartes a memoire ou dans d'autres cartes supports d'informations

Country Status (2)

Country Link
DE (1) DE4424396C2 (fr)
WO (1) WO1996002042A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7575173B2 (en) 2003-07-28 2009-08-18 Infineon Technologies, Ag Smart card, smart card module, and a method for production of a smart card module
US7609527B2 (en) 2003-02-26 2009-10-27 Imbera Electronics Oy Electronic module

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19541039B4 (de) * 1995-11-03 2006-03-16 Assa Abloy Identification Technology Group Ab Chip-Modul sowie Verfahren zu dessen Herstellung
DE19616424A1 (de) * 1996-04-25 1997-10-30 Manfred Dr Michalk Elektrisch isolierendes Material mit einem elektronischen Modul
DE19639902C2 (de) * 1996-06-17 2001-03-01 Elke Zakel Verfahren zur Herstellung kontaktloser Chipkarten und kontaktlose Chipkarte
DE19708617C2 (de) 1997-03-03 1999-02-04 Siemens Ag Chipkartenmodul und Verfahren zu seiner Herstellung sowie diesen umfassende Chipkarte
DE19716342C2 (de) * 1997-04-18 1999-02-25 Pav Card Gmbh Verfahren zur Herstellung einer Chipkarte
DE19728693C2 (de) * 1997-07-04 1999-04-29 Siemens Ag Halbleitermodul
DE19735170A1 (de) * 1997-08-13 1998-09-10 Siemens Ag Chipmodul, insbesondere für kontaktbehaftete Chipkarten, mit nebeneinander angeordneten Chips
US6651891B1 (en) 1997-11-04 2003-11-25 Elke Zakel Method for producing contactless chip cards and corresponding contactless chip card
DE10214314A1 (de) * 2002-03-28 2003-10-23 Nedcard B V Chipmodul
FI20030293L (fi) * 2003-02-26 2004-08-27 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
DE102004011702B4 (de) 2004-03-10 2006-02-16 Circle Smart Card Ag Verfahren zur Herstellung eines Kartenkörpers für eine kontaktlose Chipkarte
EP1947691A1 (fr) * 2007-01-18 2008-07-23 Tyco Electronics AMP GmbH Stratifié support de circuit et support de circuit pour monter une puce semi-conductrice d'un module à carte intelligente et leur procédé de fabrication
EP1947690A1 (fr) * 2007-01-18 2008-07-23 Tyco Electronics AMP GmbH Support de circuit laminé et support de circuit pour monter une puce de semi-conducteur d'un module de carte intelligente, et ses procédés de fabrications
DE202018002528U1 (de) 2018-05-18 2018-07-02 Sagross Designoffice Gmbh Steckbausteine

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0071311A2 (fr) * 1981-07-31 1983-02-09 Philips Patentverwaltung GmbH Procédé de fabrication d'élements de contact montés sur les surfaces de connection d'un composant intégré
EP0207852A1 (fr) * 1985-06-26 1987-01-07 Bull S.A. Procédé de montage d'un circuit intégré sur un support, dispositif en résultant et son application à une carte à microcircuits électroniques
EP0207853A1 (fr) * 1985-06-26 1987-01-07 Bull S.A. Procédé de montage d'un circuit intégré sur un support, dispositif en résultant et son application à une carte à microcircuits électroniques
EP0367311A1 (fr) * 1988-09-27 1990-05-09 Alcatel N.V. Procédé de montage d'un composant électronique et carte à mémoire en faisant usage

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DE3151408C1 (de) * 1981-12-24 1983-06-01 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Ausweiskarte mit einem IC-Baustein
DE3917707A1 (de) * 1989-05-31 1990-12-06 Siemens Ag Elektronisches modul und verfahren zu seiner herstellung

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0071311A2 (fr) * 1981-07-31 1983-02-09 Philips Patentverwaltung GmbH Procédé de fabrication d'élements de contact montés sur les surfaces de connection d'un composant intégré
EP0207852A1 (fr) * 1985-06-26 1987-01-07 Bull S.A. Procédé de montage d'un circuit intégré sur un support, dispositif en résultant et son application à une carte à microcircuits électroniques
EP0207853A1 (fr) * 1985-06-26 1987-01-07 Bull S.A. Procédé de montage d'un circuit intégré sur un support, dispositif en résultant et son application à une carte à microcircuits électroniques
EP0367311A1 (fr) * 1988-09-27 1990-05-09 Alcatel N.V. Procédé de montage d'un composant électronique et carte à mémoire en faisant usage

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7609527B2 (en) 2003-02-26 2009-10-27 Imbera Electronics Oy Electronic module
US8817485B2 (en) 2003-02-26 2014-08-26 Ge Embedded Electronics Oy Single-layer component package
US10085345B2 (en) 2003-02-26 2018-09-25 Ge Embedded Electronics Oy Electronic module
US10765006B2 (en) 2003-02-26 2020-09-01 Imberatek, Llc Electronic module
US11071207B2 (en) 2003-02-26 2021-07-20 Imberatek, Llc Electronic module
US7575173B2 (en) 2003-07-28 2009-08-18 Infineon Technologies, Ag Smart card, smart card module, and a method for production of a smart card module

Also Published As

Publication number Publication date
DE4424396A1 (de) 1996-01-18
DE4424396C2 (de) 1996-12-12

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